S5U13513P00C100 Evaluation Board User Manual

Transcription

1 SD5 Display Controller S5U5P00C00 Evaluation Board User Manual Document Number: X78A-G-00-0 Status: Revision. Issue Date: 00/09/06 SEIKO EPSON CORPORATION All Rights. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Revision.

2 Page Epson Research and Development SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

3 Epson Research and Development Page Table of Contents Introduction Features Installation and Configuration Configuration DIP Switch Configuration Jumpers Technical Description Power Power Requirements Voltage Regulators SD5 Power Clocks Reset Host Interface Connecting to the Epson S5UU00P00C00 USB Adapter Board Connecting to the Epson PC Card Extender Board Direct Host Bus Interface Support LCD Panel Interface Camera Interface YUV Output for TV Display Keypad Interface PWM Outputs GPIO Connections JTAG Connector Parts List Schematic Diagrams S5U5P00C00 Board Layout References Documents Document Sources Technical Support EPSON Display Controllers (SD5) Ordering Information S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

4 Page Epson Research and Development SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

5 Epson Research and Development Page 5 Introduction This manual describes the setup and operation of the S5U5P00C00 Evaluation Board. The evaluation board is designed as an evaluation platform for the SD5 Display Controller. The S5U5P00C00 evaluation board can connect to the S5UU00P00C00 USB Adapter board so that it can be used with a laptop or desktop computer, via USB.0. With some minor modifications, it is possible to connect the S5U5P00C00 evaluation board to a Epson PC Card Extender board instead of a USB Adapter board. The S5U5P00C00 evaluation board can also be used with many other native platforms via the host connectors which provide the appropriate signals to support a variety of CPUs. This user manual is updated as appropriate. Please check the Epson Research and Development Website at for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via at documentation@erd.epson.com. S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

6 Page 6 Epson Research and Development Features The S5U5P00C00 Evaluation Board includes the following features: 56-pin PBGA SD5 Display Controller On-board SDRAM, selectable as 8MB x -bit or 8MB x 6-bit Headers for connection to the S5UU00P00C00 USB Adapter board or to the PC Card Extender board Headers for connecting to various Host Bus Interfaces Headers for connecting to LCD panels Headers for connecting to cameras On-board 0MHz crystal (used for OSC clock input) On-board 7MHz crystal (used for OSC clock input) -pin DIP socket (used to install an oscillator for CLKI clock input).v input power On-board voltage regulator with.8v output SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

7 Epson Research and Development Page 7 Installation and Configuration The S5U5P00C00 evaluation board incorporates a DIP switch, jumpers, and 0 ohm resistors which allow it to be used with a variety of different configurations.. Configuration DIP Switch The SD5 has configuration inputs (CNF[8:0]) which are read on the rising edge of RESET#. A 0-position DIP switch (SW) is used to configure the SD5 for multiple Host Bus Interfaces. The following figure shows the location of DIP switch SW on the S5U5P00C00. DIP SWITCH - SW Figure -: Configuration DIP Switch (SW) Location SDU5B00C SW-[0:] Config All SD5 configuration inputs (CNF[8:0]) are fully configurable using DIP switch SW as described below. Table -: Summary of Power-On/Reset Options SD5 CNF[8:0] Config SW-[0] - Not used Power-On/Reset State (ON) 0 (OFF) 00b CLKI is the PLL clock source 0b BUSCLK is the PLL clock source SW-[9:8] CNF[8:7] 0b OSC is the PLL clock source b OSC is the PLL clock source SW-[6] CNF5 Indirect access Direct access SW-[7] SW-[5:] CNF6 CNF[:0] See Table -: CNF[:0] Setting for CNF[6] = b 00000b See Table -: CNF[:0] Setting for CNF[6] = 0b Parallel Direct 80 Type : CS# (see Table -: CNF[:0] Setting for CNF[6] = b ) = Required settings when using S5UU00P00C00 USB Adapter board (SW-[9:] = b) S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

8 Page 8 Epson Research and Development Table -: CNF[:0] Setting for CNF[6] = b CNF[:0] Host Bus 00000b Parallel Direct 80 Type : CS# 0000b 0000b Parallel Indirect 80 Type 000b 0000b Parallel Direct 80 Type : CS# 000b Parallel Direct 68: CS# 000b Parallel Indirect 80 Type 00b Parallel Indirect b Parallel Direct 80 Type : CS# 000b 000b 00b 000b Parallel Direct 80 Type : CS# 00b Parallel Direct 68: CS# 00b 0b 0000b Serial on HVDD: Data valid on falling edge 000b Serial on HVDD: Data valid on falling edge 000b 00b 000b 00b 00b 0b 000b Serial on HVDD: Data valid on rising edge 00b Serial on HVDD: Data valid on rising edge 00b 0b 00b 0b 0b b = Required settings when using S5UU00P00C00 USB Adapter board (SW-[9:] = b) SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

9 Epson Research and Development Page 9 Table -: CNF[:0] Setting for CNF[6] = 0b CNF[:0] 00000b 0000b 0000b 000b 0000b 000b 000b 00b 0000b 000b 000b 00b 000b 00b 00b 0b 0000b 000b 000b 00b 000b 00b 00b 0b 000b 00b 00b 0b 00b 0b 0b b Host Bus Generic Little Endian: Active Low WAIT# with tri-state Generic Little Endian: Active Low WAIT# always driven Generic Little Endian: Active HIgh WAIT# with tri-state Generic Big Endian: Active Low WAIT# with tri-state Generic Big Endian: Active Low WAIT# always driven Generic Big Endian: Active HIgh WAIT# with tri-state MIPS/ISA Little Endian: Active Low WAIT# with tri-state MIPS/ISA Little Endian: Active Low WAIT# always driven MIPS/ISA Little Endian: Active HIgh WAIT# with tri-state MC68000 Big Endian: Active High WAIT# with tri-state MC6800 Big Endian: Active High WAIT# with tri-state PR500/700/TX9 Little Endian: Active Low WAIT# with tri-state (6-bit memory accesses only) PR500/700/TX9 Little Endian: Active Low WAIT# always driven (6-bit memory accesses only) MPC8/555/556 Big Endian: Active High WAIT# with tri-state SH Little Endian: Active Low WAIT# with tri-state SH Little Endian: Active Low WAIT# always driven SH Little Endian: Active High WAIT# with tri-state SH Big Endian: Active Low WAIT# with tri-state SH Big Endian: Active Low WAIT# always driven SH Big Endian: Active High WAIT# with tri-state S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

10 Page 0 Epson Research and Development. Configuration Jumpers The S5U5P00C00 has jumper blocks which configure various board settings. The jumper positions for each function are shown below. Table -: Configuration Jumper Summary Jumper Function Position - Position - No Jumper JP COREVDD Normal COREVDD current measurement JP PLLVDD Normal PLLVDD current measurement JP PLLVDD Normal PLLVDD current measurement JP OSCVDD Normal OSCVDD current measurement JP5 OSCVDD Normal OSCVDD current measurement JP6 HVDD Normal HVDD current measurement JP7 HVDD Normal HVDD current measurement JP8 HVDD Normal HVDD current measurement JP9 HVDD Normal HVDD current measurement JP0 HVDD5 Normal HVDD5 current measurement JP SDRAM Width Select -bit wide SDRAM 6-bit wide SDRAM SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

11 Epson Research and Development Page JP-JP0 - Power Supplies for the SD5 JP-JP0 can be used to measure current consumption of each SD5 power supply. When the jumper is at position -, normal operation is selected. When no jumper is installed, the current consumption for each power supply can be measured by connecting an ammeter to pin and of the jumper. The jumper associated to each power supply is as follows: JP for COREVDD JP for PLLVDD JP for PLLVDD JP for OSCVDD JP5 for OSCVDD JP6 for HVDD (Host interface) JP7 for HVDD (LCD Panel interface) JP8 for HVDD (Camera interface) JP9 for HVDD (Camera interface) JP0 for HVDD5 (SDRAM interface) JP0 JP9 JP7 JP6 JP JP8 JP JP5 JP JP Figure -: Configuration Jumper Locations (JP-JP0) S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

12 Page Epson Research and Development JP - SDRAM Width Select JP is used to select the bus width of the external SDRAM. When the jumper is at position -, the external SDRAM is -bit wide and memory size is MB. The memory consists of chips in parallel, each 6MB and 6-bit wide. When the jumper is at position -, the external SDRAM is 6-bit wide and memory size is 6MB. In this position one memory chip is disabled and only one chip is active (6MB and 6-bit wide). JP Figure -: Configuration Jumper Location (JP) SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

13 Epson Research and Development Page Technical Description. Power.. Power Requirements The S5U5P00C00 evaluation board requires an external regulated power supply (.V at A). The power is supplied to the evaluation board through pin 5 of the P header, or pin 9 of the H header. The green LED.V Power is turned on when.v power is applied to the board... Voltage Regulators The S5U5P00C00 evaluation board has an on-board linear regulator to provide the.8v power required by the SD5 Display Controller. Additionally, there is a step-up switching voltage regulator to generate 6~V. This output is adjustable and can be used to power the LED backlight on some LCD panels... SD5 Power The SD5 Display Controller requires.8v and.v power supplies..8v power is provided by the on-board linear voltage regulator. It is used for CoreVDD, PLLVDD, PLLVDD, OSCVDD, OSCVDD..V power must be provided by the external power supply. It is used for HVDD (host interface - HIOVDD), HVDD (LCD panel interface - PIOVDD), HVDD (camera interface - CIOVDD), HVDD (camera interface - CIOVDD), and HVDD5 (SDRAM interface). HIOVDD is connected to.v through a 0 ohm resistor, R. If it is desired to have a different voltage for HIOVDD, R must be removed and the desired supply connected to pin of connector P. PIOVDD is connected to.v through a 0 ohm resistor, R. If it is desired to have a different voltage for PIOVDD, R must be removed and the desired supply connected to pin of connector H. CIOVDD is connected to.v through a 0 ohm resistor, R. If it is desired to have a different voltage for CIOVDD, R must be removed and the desired supply connected to pin 5 of connector H7. S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

14 Page Epson Research and Development CIOVDD is connected to.v through a 0 ohm resistor, R70. If it is desired to have a different voltage for CIOVDD, R70 must be removed and the desired supply connected to pin 5 of connector H6. HVDD5 is always connected to.v. Note The recommended range for HVDD (HIOVDD), HVDD (PIOVDD), HVDD CIOVDD), and HVDD (CIOVDD) is.0v~.6v.. Clocks SD5 has four clock inputs: BUSCLK, OSC, OSC and CLKI. BUSCLK and CLKI require a clock provided by an external oscillator. OSC and OSC have an internal oscillator and can work with a crystal or with an external oscillator. For the S5U5P00C00 evaluation board, OSC and OSC use crystals (0MHz for OSC and 7MHz for OSC). For the S5U5P00C00 evaluation board, CLKI is not used and is pulled to ground by a 0kΩ resistor. However, if CLKI is required, connect a -pin, DIP package oscillator in the Y footprint. For the S5U5P00C00 evaluation board, BUSCLK is not used and is pulled to ground by a 0kΩ resistor. However, if BUSCLK is required, the BUSCLK pin is connected to the H connector and to the P connector where it may be provided by the host development platform.. Reset The S5U5P00C00 evaluation board can be reset using a push-button, or via an active low reset signal from the host development platform (see H connector or P connector). The reset signal will reset the SD5 Display Controller and is available on the H6 and H7 connectors. It is possible to remove the reset signal from the H6 and H7 connectors by removing the 0 Ohm resistor R80 from the board. SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

15 Epson Research and Development Page 5. Host Interface.. Connecting to the Epson S5UU00P00C00 USB Adapter Board The S5U5P00C00 evaluation board is designed to connect to a S5UU00P00C00 USB Adapter Board. The USB adapter board provides a simple connection to any computer via a USB.0 connection. The S5U5P00C00 directly connects to the adapter board through connectors P and P. The USB adapter board also supplies the.v power required by the S5U5P00C00... Connecting to the Epson PC Card Extender Board The S5U5P00C00 evaluation board may be connected to an Epson PC Card Extender Board, but it will require an external.v power supply and some modifications to the S5U5P00C00 board. The modifications required for the S5U5P00C00 board are:. Remove R07 and R08 (0 ohm resistors, size 060). Remove R09 and R (0 ohm resistors, size 00). Populate R0 and R with 0 ohm resistors, size 00 (or short the pads on the board). Set DIP switch SW-[5:] to 0000b (CNF[:0]=0000b) to select Parallel Direct 80 Type : CS# host interface To use a modified S5U5P00C00 with an Epson PC Card Extender board:. Connect the boards using connectors P and P.. Connect.V power supply to the S5U5P00C00. Connect the positive of the power supply to test point TP.VDD, and the negative to test point TPGND. Plug the PC Card Extender (with S5U5P00C00 connected to it) into a PC Card slot on a PC.. Turn on the.v power supply and the S5U5P00C00 is ready to use. Note that a windows driver is required to be installed on the PC (the SDxxx PCI/PC Card Bus driver is available from S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

16 Page 6 Epson Research and Development.. Direct Host Bus Interface Support The SD5 Display Controller directly supports many host bus interfaces. For detailed SD5 pin mapping, refer to the SD5 Hardware Functional Specification, document number X78B-A-00-xx. All SD5 host interface pins are available on connectors H and H which allow the S5U5P00C00 to be connected to a variety of development platforms. However, connectors H and H are not populated on the S5U5P00C00 evaluation board. If connectors H and H are added, all host interface signals must match HVDD of the SD5. For the maximum/minimum values of the voltages, refer to the SD5 Hardware Functional Specification, document number X78B-A-00-xx. The following diagram shows the location of the host bus connectors, H and H. They are 0.x0. -pin headers (7x). H H Figure -: Host Bus Connector Locations (H and H) For the pinout of connectors H and H, see Schematic Diagrams on page. SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

17 Epson Research and Development Page 7.5 LCD Panel Interface The LCD interface signals are available on connectors H and H5. Connector H5 includes GPIOG[:0] which may be used as additional signals for extended TFT interfaces. For SD5 LCD interface pin mapping, refer to the SD5 Hardware Functional Specification, document number X78B-A-00-xx. Connectors H and H5 are both 0.x0. 0-pin headers (0x). For the pinout of connectors H and H5, see Schematic Diagrams on page. On the evaluation board there is an adjustable 6~V, 0mA max. power supply. This voltage is provided only on connector H (it is not used elsewhere on the board). It is intended for use to power the LED backlight on some LCD panels. The voltage is adjusted by the R06 pot. Note For LCD panels that use CCFL backlight, an external power supply must be used to provide power to the inverter for CCFL backlight. Usually, the inverter current consumption is higher than the maximum 0mA current available from the on-board voltage regulator. The following diagram shows the location of the LCD panel connectors H and H5. H5 H Figure -: LCD Panel Connectors Locations (H, H5) S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

18 Page 8 Epson Research and Development.6 Camera Interface All the signals for the Camera interface are available on connector H6. All the signals for the Camera interface are available on connector H7. H6 and H7 are 0.x0. 0-pin headers (0x). For the pinout of connectors H6 and H7, see Schematic Diagrams on page. The SD5 Camera interface signals use the GPIOC[7:0] and GPIOD[:0] pins. The Camera interface signals use the GPIOA[7:0] and GPIOB[7:0] pins. These GPIO pins may be configured for a variety of SD5 supported functions. GPIOC[7:0] and GPIOD[:0] may be configured as GPIO pins, Camera interface pins, or as YUV output pins. GPIOA[7:0] and GPIOB[7:0] may be configured as GPIO pins, Camera interface pins, Keypad interface pins, or PWM output pins. For detailed SD5 GPIO pin mapping, refer to the SD5 Hardware Functional Specification, document number X78B-A-00-xx. Connector H6 and H7 may be used to evaluate any function for which the GPIOA[7:0], GPIOB[7:0], GPIOC[7:0], GPIOD[:0] can be configured. The SD5 has an IC interface which uses two signals that are connected to both the H6 and H7 connectors. The default configuration of the evaluation board has the IC signals, IC_SCL and IC_SDA, pulled high to CIOVDD. If the IC signals must be pulled high to CIOVDD, R6 and R75 must be removed and.7kω resistors must be mounted for R6 and R77. The reset signal provided on H6 and H7 is active low and is pulled to HIOVDD when inactive. The following diagram shows the location of the camera connectors H6 and H7. H6 H7 Figure -: Camera Expansion Connector Locations (H6, H7) SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

19 Epson Research and Development Page 9.7 YUV Output for TV Display The SD5 can output YUV data which can be used to display an image on a TV screen via an external video encoder. The YUV output is multiplexed with other functions on the GPIOC[7:0] and GPIOD[:0] pins. These pins are routed to connector H6..8 Keypad Interface The SD5 has a 5x5 keypad interface which is multiplexed with other functions on the GPIOA[:0] and GPIOB[:0] pins. These pins are routed to connectors H6 and H7. It is possible to use a Keypad device with the S5U5P00C00 evaluation board by connecting it to the H6 and H7 connectors..9 PWM Outputs The SD5 has PWM outputs which may be used to control the brightness of LEDs. It also has an input, AUDIN, which is used to control the overall operation of the PWM outputs. The PWM output function is multiplexed on the GPIOA[7:5] and GPIOB[7] pins. AUDIN is multiplexed on the GPIOD[] pin. These pins are routed to connector H6 and H7..0 GPIO Connections The SD5 Display Controller GPIO pins have multiple functions. All the GPIO pins are routed to the connectors on the S5U5P00C00 evaluation board. If any pin is configured as a GPIO, it will be available on the connectors as listed below: GPIOA[7:0] pins are routed to connector H7. GPIOB[7:5] and GPIOB[:0] pins are routed to connector H7. GPIOB[6:5] are also routed to connector H6. GPIOB[] pin is routed to connector H6. GPIOC[7:0] pins are routed to connector H6. GPIOD[:0] pins are routed to connector H6. GPIOG[:0] pins are routed to connector H5. FPDAT[:8] which may be used as GPIOH[5:0] are routed to connector H5. S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

20 Page 0 Epson Research and Development. JTAG Connector The SD5 design includes a JTAG interface. All the JTAG signals are available on connector H, however, connector H is not populated on the board. For the pinout of connector H, see Schematic Diagrams on page. The following diagram shows the location of the JTAG connector (H). H Figure -: JTAG Connector Location SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

21 Epson Research and Development Page 5 Parts List Table 5-: Parts List Item Qty Reference Part Description 9 C, C, C, C, C5, C6, C7, C8, C9, C9, C, C6, C8, C9, C0, C, C, C, C, C5, C, C, C5, C6, C7, C8, C9, C50, C5, C65, C66, C69, C70, C7, C7, C7, C7, C75, C76, C77, C78, C79, C80, C8, C8, C98, C00, C0, C05 C0, C, C, C, C, C5, C6, C7, C8, C5, C7, C6, C7, C8, C9, C0, C, C, C5, C5, C5, C55, C56, C57, C58, C59, C60, C8, C8, C85, C86, C87, C88, C89, C90, C9, C9, C9, C9, C95, C96 0.uF 0.0uF C0, C nf C, C 0uF 5 C6, C6, C6, C6 8pF 6 C67, C68 0uF Manufacturer / Part No. / Assembly Instructions Yageo America 00F0Z7B0D Yageo America 00ZRY5V7BB0 Yageo America 00R0K9B0D Panasonic - ECG ECJ- CV50J06M Panasonic - ECG ECJ- 0ECH80J Panasonic - ECG ECJ- FBA06K 7 C97, C99 uf Panasonic - ECG ECJ- 0EB0J05M 8 C0.7uF 0V T Kemet T9B75K00AS 9 C0 0pF Panasonic - ECG ECJ- 0ECH00D 0 C0 uf 50V TDK C6X7RH05K D DIODE D.V Power D MBR050 DIODE SCHOTTKY 0V00MA SSSMINI LED GREEN SS TYPE LOW CUR SMD Panasonic - SSG MA7D700L Panasonic - SSG LNJ08G8LRA Micro Commercial Co. MBR050-TP F, F ACF58- FILTER -TERM 60MHZ 00MA SMD TDK ACF H HEADER 6X Samtec TSW G-D 6 0 H, H HEADER_7X AMP H LCD Connector Samtec TST-0-0-G-D 8 H5 Extended LCD Connector Samtec TST-0-0-G-D S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

22 Page Epson Research and Development Item Qty Reference Part Description Manufacturer / Part No. / Assembly Instructions 9 H6, H7 HEADER_0X Samtec TSW-0-05-G-D 0 0 JP, JP, JP, JP, JP5, JP6, JP7, JP8, JP9, JP0 JP HEADER 9 L, L, L, L, L5, L6, L7, L8, L9 Ferrite L0 0uH CONN HEADER VERT POS.00 TIN or GENERIC CONN HEADER VERT POS.00 TIN or GENERIC FERRITE 00MA 98 OHMS 060 SMD COIL 0UH 00MA CHOKE SMD Steward HZ060B75R- 0 Panasonic - ECG ELL- 6SH00M P, P HEADER_0X M 50-8-RB R, R, R, R, R5, R6, R7, R8, R9, R0, R, R, R, R, R5, R6, R7, R8, R9, R0, R, R, R, R, R5, R6, R7, R8, R9, R0, R, R5, R6, R7, R8, R9, R0, R, R, R, R, R5, R6, R7, R8, R9, R50, R5, R5, R5, R5, R55, R56, R57, R58, R68, R69, R77 R, R, R, R70, R96, R07, R08 R59, R60, R6, R6, R6, R6, R65, R66, R67, R78, R79, R8 % 0 0k 8 6 R7, R76, R80, R0, R09, R 0 9 R7, R7 M 0 R7, R75 0 R8 70 % 5 R8, R85, R87, R88, R89, R90, R9, R9, R9, R9, R95, R97, R99, R0, R05 7k R8, R98.7k 0 R86, R00, R0, R NP 5 R0 887k % 6 R0 k 7 R06 00k 8 SH, SH, SH, SH, SH5, SH6, SH7, SH8, SH9, SH0, SH Table 5-: Parts List.00 in. Jumper Shunt JUMPER SHORTING TIN Panasonic - ECG EVN- 5ESX50B5 Sullins Electronics Corp. STC0SYAN SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

23 Epson Research and Development Page Table 5-: Parts List Item Qty Reference Part Description Manufacturer / Part No. / Assembly Instructions 9 SW SW DIP-0 CTS 8-0LPST 0 SW SW TACT-SPST TPGND, TPGND, TPGND, TP.VDD TP_SMT 0 T TP SIP U SD5 PBGA56 U, U ISS6800D-7TL 5 U TPS80L0DCKR SWITCH TACT SILVER PLT GULLWING PC TEST POINT MINIATURE SMT alternate Micron MT8LC8M6AP-7E IC.6V SUPPLY MON SOT--5 ITT Industries KSCGLFS Keystone 505 ISSI ISS6800D-7TL Texas Instruments TPS80L0DCKR 6 U5 MIC700-.8WS Alternate MIC900-.8WS Micrel MIC700-.8WS 7 U6 TPS600 IC CONV DC/DC BOOST LP SOT--5 TI TPS600DVBR 8 X MA M 9 X MA M 50 0 Y -Pin DIP AMP S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

24 5 5 Page Epson Research and Development 6 Schematic Diagrams CORE HVDD HVDD.00 in. Jumper Shunt SH.8VDD JP CORE HVDD HVDD5 OSC PLL HVDD OSC PLL COREVDD U C C C C C5 C6 C7 C8 C9 AB[0:0] FPDAT[:0] D D AB0 B M7 FPDAT0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF AB AB0 FPDAT0 A N7 FPDAT AB AB FPDAT B T7 FPDAT AB AB FPDAT A R7 FPDAT AB AB FPDAT B P7 FPDAT C0 C C C C C5 C6 C7 C8 AB5 AB FPDAT C L7 FPDAT5 AB6 AB5 FPDAT5 B M6 FPDAT6 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF AB7 A AB6 FPDAT6 K6 FPDAT7 AB8 AB7 FPDAT7 A5 R6 FPDAT8 AB9 AB8 FPDAT8 B5 P6 FPDAT9 AB0 AB9 FPDAT9 C5 M5 FPDAT0 AB AB0 FPDAT0 C6 N5 FPDAT Place a 0.0uF and a 0.uF cap on each AB D6 AB FPDAT T5 FPDAT COREVDD power pin of the SD5 AB AB FPDAT B6 T FPDAT AB AB FPDAT A6 R FPDAT AB5 AB FPDAT A7 T FPDAT5 AB6 AB5 FPDAT5 C7 P FPDAT6 AB7 AB6 FPDAT6 E6 N FPDAT7.00 in. Jumper Shunt.00 in. Jumper Shunt AB8 AB7 FPDAT7 D7 R5 FPDAT8 SH.8VDD SH.8VDD AB9 AB8 FPDAT8 FPDAT9 JP JP B7 K5 L PLL L PLL AB0 AB9 FPDAT9 FPDAT0 DB[5:0] E7 P5 Ferrite Ferrite AB0 FPDAT0 T FPDAT DB0 G FPDAT R FPDAT DB DB0 FPDAT F K FPDAT PLLVDD C9 C0 PLLVDD C C DB DB FPDAT F7 nf C nf C DB DB F R8 0.uF 0uF 0.uF 0uF FPFRAME DB DB FPFRAME F5 FPLINE DB5 F DB FPLINE T8 P8 FPSHIFT L L DB6 DB5 FPSHIFT F M8 Ferrite Ferrite FPDRDY MEMDQ[:0] DB7 DB6 FPDRDY E GND GND DB8 DB7 E5 C9 R % MEMDQ0 DB9 DB8 MEMDQ0 E A0 R % MEMDQ DB0 DB9 MEMDQ E B0 R % MEMDQ DB DB0 MEMDQ D C0 R % MEMDQ DB DB MEMDQ D B R5 % MEMDQ DB DB MEMDQ D D R6 % MEMDQ5 DB DB MEMDQ5 C E R7 % MEMDQ6.00 in. Jumper Shunt.00 in. Jumper Shunt C DB5 C DB MEMDQ6 A R8 % MEMDQ7 SH.8VDD SH5.8VDD C DB5 MEMDQ7 JP JP5 D R9 % MEMDQ8 L5 OSC L6 OSC MEMDQ8 MEMDQ9 CS# G6 C R0 % Ferrite Ferrite CS# MEMDQ9 MEMDQ0 M/R# G A R % M/R# MEMDQ0 MEMDQ RD# H B5 R % RD# MEMDQ RD/WR# H MEMDQ B6 R % OSCVDD C5 C6 OSCVDD C7 C8 RD/WR# MEMDQ MEMDQ WE0# H D R % WE0# MEMDQ G5 D5 R5 % MEMDQ 0.0uF 0.uF 0.0uF 0.uF WE# WE# MEMDQ J E R6 % MEMDQ5 WAIT# WAIT# MEMDQ5 J5 D9 R7 % MEMDQ6 L7 L8 MEMDQ6 MEMDQ7 BS# H F0 R8 % Ferrite Ferrite BS# MEMDQ7 MEMDQ8 GND GND BURST# J E0 R9 % BURST# MEMDQ8 MEMDQ9 Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each BDIP# J6 D0 R0 % BDIP# MEMDQ9 E R % MEMDQ0 OSCVDD power pin of the SD5 OSCVDD power pin of the SD5 MEMDQ0 H5 C R % MEMDQ INT# INT# MEMDQ H6 A R % MEMDQ INT# INT# MEMDQ MEMDQ RESET# J B R % RESET# MEMDQ SD5 PBGA56 A R5 % MEMDQ MEMDQ MEMDQ5.VDD.VDD.VDD CLKI K B R6 % CLKI MEMDQ5 MEMDQ6 BUSCLK G B R7 % BUSCLK MEMDQ6 A5 R8 % MEMDQ7 MEMDQ7 MEMDQ8 R OSCI L C5 R9 % R R OSCI MEMDQ8 L C6 R0 % MEMDQ9 OSCO OSCO MEMDQ9 E R % MEMDQ0.00 in. Jumper Shunt.00 in. Jumper Shunt.00 in. Jumper Shunt MEMDQ0 R5 % MEMDQ HIOVDD PIOVDD CIOVDD OSCI M D6 SH7 SH6 SH8 OSCI MEMDQ MEMA[:0] JP8 JP6 JP7 M HVDD HVDD HVDD OSCO OSCO F8 R6 % MEMA0 MEMA0 P0 E8 R7 % MEMA GPIOA0 GPIOA0 MEMA N0 C8 R8 % MEMA GPIOA GPIOA MEMA R0 B8 R9 % MEMA HVDD HVDD HVDD GPIOA GPIOA MEMA T0 A8 R0 % MEMA GPIOA GPIOA MEMA T F9 R % MEMA5 GPIOA GPIOA MEMA5 M0 E9 R % MEMA6 C9 C0 C C C C C5 GPIOA5 GPIOA5 MEMA6 L0 A9 R % MEMA7 GPIOA6 GPIOA6 MEMA7 M9 E6 R % MEMA8 Place Ohm series source termination 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF GPIOA7 GPIOA7 MEMA8 F R5 % MEMA9 resistors as close to the SD5 as MEMA9 R F R6 % MEMA0 possible. GPIOB0 GPIOB0 MEMA0 P F R7 % MEMA B GPIOB GPIOB MEMA B R F5 R8 % C6 C7 C8 C9 C0 C C GPIOB GPIOB MEMA T GPIOB GPIOB T F6 R9 % GPIOB MEMBA0 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF GPIOB MEMBA0 T G R50 % GPIOB5 GPIOB5 MEMBA MEMBA N GPIOB6 GPIOB6 M H R5 % GPIOB7 GPIOB7 MEMCS# MEMCS# G6 R5 % MEMWE# MEMWE# N6 G R5 % Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each GPIOC0 GPIOC0 MEMCAS# MEMCAS# M G5 R5 % CIOVDD HVDD power pin of the SD5 HVDD power pin of the SD5 HVDD power pin of the SD5 GPIOC GPIOC MEMRAS# MEMRAS# P6 H R55 % GPIOC GPIOC MEMDQM0 MEMDQM0 N5 H R56 % GPIOC GPIOC MEMDQM MEMDQM M H5 R57 % GPIOC GPIOC MEMDQM MEMDQM N J R58 % GPIOC5 GPIOC5 MEMDQM MEMDQM P5 R59 R60 R6 R6 R6 R6 R65 R66 R67.VDD GPIOC6 GPIOC6 R6 GPIOC7 GPIOC7 MEMCKE H6 R68 % MEMCKE 0k 0k MEMCLK J6 R69 % 0k 0k 0k 0k 0k 0k 0k MEMCLK M6 R70 GPIOD0 GPIOD0 L J5 GPIOD GPIOD CNF0 L J.00 in. Jumper Shunt.00 in. Jumper Shunt GPIOD GPIOD CNF M5 K SH9 CIOVDD SH0.VDD GPIOD GPIOD CNF JP9 J HVDD JP0 HVDD5 CNF L9 K6 GPIOG0 GPIOG0 CNF P9 K GPIOG GPIOG CNF5 R9 K5 GPIOG GPIOG CNF6 T9 L6 HVDD HVDD5 GPIOG GPIOG CNF7 N8 K GPIOG GPIOG CNF8 N R 5_TMS C C C5 C6 C7 C8 C9 C50 C5 VCP TMS R N 5_TDI SW VCP TDI L5 5_TDO 0.uF TESTEN TDO R5 SW DIP-0 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 5_TCK TCK P P 5_TRST CIOVDD H TRST C5 C5 C5 C55 C56 C57 C58 C59 C60 R7 5_TRST 5_TCK 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 5_TDO A 5_TDI 0 A 5_TMS GND GND Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each GND GND HEADER 6X HVDD power pin of the SD5 HVDD5 power pin of the SD5 JTAG / Boundary Scan Port Title SD5 PBGA56 Size Document Number Rev <Doc>.0 Thursday, January 0, 007 Date: Sheet of C 0 A A6 D D8 D G7 G8 G9 G0 G H7 H8 H9 H0 J J7 J8 J9 J0 K K7 K8 K9 K0 K N N6 N9 N T T6 N R L M PLL PLL OSC OSC C COREVDD COREVDD C F6 COREVDD COREVDD F COREVDD K COREVDD L6 L COREVDD COREVDD P P COREVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD HVDD5 HVDD5 HVDD5 HVDD5 HVDD5 HVDD5 OSCVDD OSCVDD PLLVDD PLLVDD D5 E G L5 L8 T6 R L M T5 B9 C E5 G H J L M P P Figure 6-: S5U5P00C00 Schematics ( of ) SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

25 Epson Research and Development Page 5.VDD MEMA[:0] U MEMA 5 MEMA0 A VDD MEMA9 A0 VDD MEMA8 A9 VDD 7 MEMA7 A8 VDDQ R7 M MEMA6 A7 VDDQ 9 OSCI R7 M OSCO OSCO OSCI MEMA5 A6 VDDQ 0 MEMA A5 VDDQ 9 9 R7 R75 MEMA A 6 MEMBA 0 0 D MEMA A BA MEMBA MEMBA0 D 5 0 X X MEMA A BA0 MEMBA0 MEMA0 A A0 DQMH 9 MEMDQM XIN XOUT XIN XOUT MEMDQ[:0] 5 DQML MEMDQM0 6 MEMWE# MEMWE# MEMDQ0 MEMCAS# NC NC WE# NC NC 7 MEMCAS# MEMDQ D0 CAS# 8 MEMRAS# C6 MA M C6 C6 MA M C6 MEMRAS# MEMDQ D RAS# 5 9 MEMCS# 8pF 8pF 8pF 8pF MEMCS# MEMDQ D CS# MEMDQ D 8 7 MEMCKE MEMCKE MEMDQ5 D CKE 0 8 MEMCLK MEMCLK MEMDQ6 D5 CLK GND GND GND GND MEMDQ7 D6 MEMDQ8 D7 NC 6 MEMDQ9 D8 NC 0 MEMDQ0 D9 5 5 MEMDQ D0 7 MEMDQ D 8 8 MEMDQ D 50 R76 0 MEMDQ D Q 5 5 HIOVDD L9 MEMDQ5 D Q 6 Ferrite Y 5 D5 Q Q 6 VDD OE C65 R77 % C 7 OUT 8 CLKI C ISS6800D-7TL GND 0.uF This resistor is used to.vdd R78 pull down CLKI input MEMA[:0] U -Pin DIP 0k when oscillator is not MEMA 5 TTL/CMOS Oscillator used. If an oscillator is MEMA0 A VDD used, then this resistor MEMA9 A0 VDD can be removed. MEMA8 A9 VDD 7 MEMA7 A8 VDDQ MEMA6 A7 VDDQ 9.00 in. Jumper Shunt MEMA5 A6 VDDQ 0 SH D MEMA A5 VDDQ 9 9.VDD MEMA A 6 MEMBA HOST_RESET# K A MEMA A BA 5 0 MEMBA0 MEMA A BA0 MEMA0 A HIOVDD DIODE A0 DQMH 9 R79 MEMDQM U MEMDQ[:0] 5 0k DQML MEMDQM 6 MEMWE# RESET# MEMDQ6 WE# MEMCAS# JP VDD RESET# 7 MEMDQ7 D0 CAS# 8 MEMRAS# C66 MEMDQ8 D RAS# MR# 5 9 MEMDQ9 D CS# MEMCS# 7 0.uF MEMDQ0 D MEMCKE GND 7 B MEMDQ D CKE MEMCLK HEADER GND 0 8 R80 0 CM_RST# B MEMDQ D5 CLK TPS80L0DCKR MEMDQ D6 SDRAM Width Select MEMDQ D7 NC 6 x SDRAM (MB) SW MEMDQ5 D8 NC 0 x6 SDRAM (6MB) SW TACT-SPST MEMDQ6 D9 5 MEMDQ7 D0 5 7 MEMDQ8 D 8 8 MEMDQ9 D 50 MEMDQ0 D Q 5 5 MEMDQ D Q 6 5 D5 Q Q 6.VDD U5.8VDD MIC700-.8WS ISS6800D-7TL IN OUT SDRAM Mb x 6-bit x banks SDRAM Mb x 6-bit x banks C05 C68 0.uF 0uF GND TAB C67 C0 0uF Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each 0.uF.VDD VDD power pin of the two SDRAM chips..vdd VDDQ power pin of the two SDRAM chips. C69 C70 C7 C7 C7 C7 C75 C76 C77 C78 C79 C80 C8 C8 A A 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF C8 C8 C85 C86 C87 C88 C89 C90 C9 C9 C9 C9 C95 C96 Title SDRAM / Clocks / Reset /.8V Supply 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF Size Document Number Rev B <Doc>.0 Friday, January 9, 007 Date: Sheet of Figure 6-: S5U5P00C00 Schematics ( of ) S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

26 5 5 Page 6 Epson Research and Development D D P DB[5:0] BUSCLK WAIT# HIOVDD WE# 7 8 R09 0 RD/WR# H 9 0 R0 NP R07 0 DB0 DB INT# R NP DB DB 5 6 R 0 WE0# DB 5 6 DB5 RD# 7 8 DB6 7 8 DB HOST_RESET# DB8 DB9 DB5 DB DB0 DB DB 5 6 DB DB 5 6 DB DB DB0 DB DB5 C C DB9 9 0 DB8 9 0 CS# CS# DB7 M/R# M/R# RD# RD# DB6 DB5 INT# INT# DB 5 6 DB WE0# WE# WE0# 5 6 WE# DB 7 8 DB RD/WR# RD/WR# 7 8 WAIT# WAIT# DB0 9 0 HOST_RESET#.VDD 9 0 HOST_RESET# BUSCLK BUSCLK AB AB HEADER_0X R8 TP.VDD HEADER_7X 0k TP_SMT P.VDD AB[0:0] CS# M/R# R H This resistor is used to pull 9 0 AB0 down BUSCLK input when it is AB not used. If BUSCLK input is AB AB5 used, then this resistor can 5 6 AB0 AB6 7 8 AB7 be removed. AB9 7 8 AB8 9 0 AB7 9 0 AB8 AB9 B AB6 AB0 AB B AB5 AB AB 5 6 AB AB 5 6 AB AB 7 8 AB5 AB 7 8 AB0 9 0 AB9 9 0 AB8 AB6 AB7 AB7 AB8 AB9 AB6 AB5 AB0 5 6 AB 5 6 AB 7 8 AB AB BDIP# BURST# 7 8 BS# BS# 9 0 INT# AB0 9 0 HEADER_0X HEADER_7X.VDD R8 70 % TPGND TPGND TPGND TP_SMT TP_SMT TP_SMT A A Title Host connectors Size Document Number Rev B <Doc>.0 Friday, January 9, 007 Date: Sheet of 7 8 A D.V Power K Figure 6-: S5U5P00C00 Schematics ( of ) SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

27 5 5 Epson Research and Development Page 7 H6 FPDAT[:0] CMDAT0 CMDAT GPIOC0 GPIOC CMDAT 5 6 CMDAT GPIOC GPIOC H CMDAT 7 8 CMDAT5 GPIOC GPIOC5 CMDAT6 9 0 CMDAT7 FPDAT0 GPIOC6 GPIOC7 CMCLKIN CMVREF FPDAT FPDAT6 GPIOD GPIOD0 CMCLKOUT CMHREF D GPIOD FPDAT FPDAT7 GPIOD D CIOVDD 5 6 FPDAT 7 8 IC_SCL 7 8 CM_RST# FPDAT 0 IC_SDA 9 0 GPIOB GPIOB FPDAT5 FPDAT6 FPDAT7 5 6 HEADER_0X FPDAT8 7 8 FPDAT9 9 0 CIOVDD FPDAT0 FPDAT FPDAT 5 6 FPDAT 7 8 PIOVDD C97 C98 Place these capacitors close FPDAT 9 0 VDD to pin 5 of the header. FPDAT5 uf 0.uF FPSHIFT 5 6 FPDRDY 7 8 FPLINE 9 0 FPFRAME H7 LCD Connector CMDAT0 CMDAT GPIOA0 GPIOA CMDAT CMDAT C 5 6 GPIOA GPIOA C H5 CMDAT 7 8 CMDAT5 GPIOA GPIOA5 CMDAT6 9 0 CMDAT7 GPIOA6 GPIOA7 CMCLKIN CMVREF GPIOG0 GPIOB0 GPIOB CMCLKOUT CMHREF GPIOG GPIOB GPIOB GPIOG CIOVDD 5 6 IC_SCL CM_RST# GPIOG GPIOB5 7 8 CM_RST# FPDAT8 9 0 IC_SDA CMSTROUT GPIOB6 9 0 GPIOB7 FPDAT9 FPDAT0 FPDAT 5 6 HEADER_0X FPDAT 7 8 FPDAT 9 0 CIOVDD GPIOG C99 C00 Place these capacitors close 9 0 to pin 5 of the header. uf 0.uF CIOVDD CIOVDD B B Extended LCD Connector.VDD R96 0 F ACF58- C0.7uF 0V T + Internal Step Up 6 to V Power Supply Typical 0mA U6 VIN L0 0uH SW FB CMDAT0 R8 7k R8 R86 CMDAT R85 7k.7k NP CMDAT R87 7k CMDAT R88 7k D CMDAT R89 7k IC_SCL MBR050 F VDD CMDAT5 R90 7k ACF58- CMDAT6 R9 7k A K T CMDAT7 R9 7k CIOVDD CIOVDD C0 CMSTROUT R9 7k 0pF R0 GPIOB R9 7k R0 k CMVREF R95 7k 887k % C0 CMHREF R97 7k R98 R00 uf 50V CMCLKOUT R99 7k.7k NP CMCLKIN R0 7k IC_SDA EN GND R05 TPS600 7k These resistors are to prevent GPIOA[7:0] and GPIOB7, GPIOB[:0] from floating if they A Vout=.x[+R0/(R05+R06)] (V) are not used. GPIOB[6:5] are A pulled up. If any of GPIOA[7:0], GPIOB7 or GPIOB[:0] are used, the corresponding pull down R06 resistor may be removed. 00k Title LCD and Camera/GPIO connectors Size Document Number Rev B <Doc>.0 Friday, January 9, 007 Date: Sheet of R Figure 6-: S5U5P00C00 Schematics ( of ) S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

28 Page 8 Epson Research and Development 7 S5U5P00C00 Board Layout Figure 7-: S5U5P00C00 Board Layout - Top View SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

29 Epson Research and Development Page 9 Figure 7-: S5U5P00C00 Board Layout - Bottom View S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

30 Page 0 Epson Research and Development 8 References 8. Documents Epson Research and Development, Inc., SD5 Hardware Functional Specification, document number X78B-A-00-xx. 8. Document Sources Epson Research and Development Website: SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

31 Epson Research and Development Page 9 Technical Support 9. EPSON Display Controllers (SD5) AMERICA EPSON ELECTRONICS AMERICA, INC. 580 Orchard Parkway San Jose, CA 95,USA Phone: FAX: EUROPE EPSON EUROPE ELECTRONICS GmbH Riesstrasse 5, 8099 Munich, GERMANY Phone: FAX: ASIA EPSON (CHINA) CO., LTD. 7F, Jinbao Bldg., No.89 Jinbao St., Dongcheng District, Beijing 00005, CHINA Phone: FAX: SHANGHAI BRANCH 7F, Block B, High-Tech Bldg., 900, Yishan Road, Shanghai 00, CHINA Phone: FAX: SHENZHEN BRANCH F, Dawning Mansion, Keji South th Road, Hi-Tech Park, Shenzhen 58057, CHINA Phone: FAX: EPSON HONG KONG LTD. 0/F, Harbour Centre, 5 Harbour Road Wanchai, Hong Kong Phone: FAX: Telex: 655 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. F, No. 7, Song Ren Road, Taipei 0, TAIWAN Phone: FAX: EPSON SINGAPORE PTE., LTD. HarbourFront Place, #0-0 HarbourFront Tower One, Singapore 0986 Phone: FAX: SEIKO EPSON CORP. KOREA OFFICE 5F, KLI 6 Bldg., 60 Yoido-dong Youngdeungpo-Ku, Seoul, 50-76, KOREA Phone: FAX: SEIKO EPSON CORP. SEMICONDUCTOR OPERATIONS DIVISION IC Sales Dept. IC International Sales Group -8, Hino, Hino-shi, Tokyo 9-850, JAPAN Phone: FAX: Ordering Information To order the S5U5P00C00 Evaluation Board, contact the Epson sales representative in your area and order part number S5U5P00C00. S5U5P00C00 Evaluation Board User Manual Issue Date: 00/09/06 Revision. SD5 X78A-G-00-0

32 Page Epson Research and Development Change Record X78A-G-00-0 Revision. - Issued: September 6, 00 remove references to type interface X78A-G-00-0 Revision.0 - Issued: March 0, 007 minor edits updated schematics updated parts list added board layout X78A-G Revision 0.0 revised manual due to design changes added new schematics added new parts list X78A-G Revision 0.0 Initial draft of manual SD5 S5U5P00C00 Evaluation Board User Manual X78A-G-00-0 Issue Date: 00/09/06 Revision.

33 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Epson: S5U5P00C00