S5U13515P00C100 Evaluation Board User Manual

Transcription

1 SD Display Controller SUP00C00 Evaluation Board User Manual SEIKO EPSON CORPORATION Rev.

2 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. All other product names mentioned herein are trademarks and/or registered trademarks of their respective companies. SEIKO EPSON CORPORATION , All rights reserved.

3 Table of Contents Chapter Introduction Chapter Features Chapter Installation and Configuration CNF[7:0] Configuration Inputs CNF[:0] CNF[7:] Host Interface Configuration Configuration Jumpers Chapter Technical Description Power Power Requirements Voltage Regulators SD Power LCD Backlight Power Clocks Reset Memory SDRAM Serial Flash Memory with SPI interface Host Interface Direct Host Bus Interface Support Connecting to the Epson SUU00P00C00 USB Adapter Board LCD Interface FPIO Interface FPIO Interface Camera / IC Interface Keypad Interface IS Interface PWM Connector C Debugger Port JTAG Interface Chapter Parts List Chapter 6 Schematic Diagrams Chapter 7 Board Layout SUP00C00 Evaluation Board User Manual (Rev.) EPSON

4 Chapter 8 References Documents Document Sources EPSON SUP00C00 Evaluation Board User Manual (Rev.)

5 Chapter Introduction Chapter Introduction This manual describes the setup and operation of the SUP00C00 Evaluation Board. The evaluation board is designed as an evaluation platform for the SD Display Controller. The SUP00C00 evaluation board can be used with many native platforms via the host connector which provides the appropriate signals to support a variety of CPUs. The SUP00C00 evaluation board can also connect to the SUU00P00C00 USB Adapter board so that it can be used with a laptop or desktop computer, via USB.0. This user manual is updated as appropriate. Please check the Epson Research and Development Website at for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via at documentation@erd.epson.com. SUP00C00 Evaluation Board User Manual (Rev.) EPSON

6 Chapter Features Chapter Features The SUP00C00 Evaluation Board includes the following features: 6-pin PBGA SD Display Controller On-board SDRAM, configurable as MB (-bit wide) or 6MB (6-bit wide) On-board Serial Flash Memory, Mbit Headers for connection to various Host Bus Interfaces (includes all SD Host Bus Interface signals) Headers for connection to the SUU00P00C00 USB Adapter board Headers for connection to various LCD panels (includes all SD FPIO and FPIO interface signals) Header for connection to cameras Header for IS outputs On-board x keypad On-board 0MHz crystal -pin DIP socket (if an oscillator for CLKI input is required).v input power On-board voltage regulator with.8v output On-board voltage regulator with adjustable ~V output, 60~00mA max., to provide power for LED backlight of LCD panels. 6 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

7 Chapter Installation and Configuration Chapter Installation and Configuration The SUP00C00 evaluation board incorporates a DIP switch, jumpers, and 0 ohm resistors which allow it to be used with a variety of different configurations.. CNF[7:0] Configuration Inputs The SD has 8 configuration inputs (CNF[7:0]), which can be configured through a combination of a DIP switch and 0 ohm resistors. CNF[:0] are dedicated inputs and are configured using DIP switch SW. CNF[7:] are multiplexed with some host interface signals and are configured by 0 ohm resistors... CNF[:0] CNF[:0] are configured using DIP switch SW as described below. Table -: CNF[:0] Configuration Settings CNF[:0] (connected to HIOVDD) 0 (connected to ) CNF CNF[:] are used in combination with CNF[7:] to select the host bus interface. For a CNF summary of the possible host bus interfaces, see Section Table - :, Host Interface Configuration Settings on page 9. CNF0 OSCI is the source for Input Clock CLKI is the source for Input Clock = suggested settings The following figure shows the location of DIP switch SW on the SUP00C00 evaluation board. Figure -: Configuration DIP Switch (SW) Location SUP00C00 Evaluation Board User Manual (Rev.) EPSON 7

8 Chapter Installation and Configuration.. CNF[7:] CNF[7:] are configured using 0 Ohm resistors as described below. Table -: CNF[7:] Configuration Settings CNF Pin (connected to HIOVDD) 0 (connected to ) CNF (see Note) CNF CNF CNF6 (see Note) CNF7 TEA# AB0 BDIP# BURST# AB BE# AB0 AB R00 populated R07 not populated R99 populated R06 not populated R9 populated R0 not populated R96 populated R0 not populated R98 populated R0 not populated R97 populated R0 not populated R99 populated R06 not populated R0 populated R08 not populated R00 not populated R07 populated R99 not populated R06 populated R9 not populated R0 populated R96 not populated R0 populated R98 not populated R0 populated R97 not populated R0 populated R99 not populated R06 populated R0 not populated R08 populated = default settings, required settings when using SUU00P00C00 USB Adapter Board Note CNF and CNF6 are mapped to different pins depending on the combination of the other CNF inputs. The following figure shows the location of the 0 Ohm resistors used to configure CNF[7:]. Figure -: CNF[7:] 0 Ohm Resistor Locations 8 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

9 Chapter Installation and Configuration.. Host Interface Configuration The host bus interface used by the SUP00C00 evaluation board is selected using a combination of the CNF[:] pins and unused host interface pins. Many host bus interfaces have unused pins that can be used as configuration pins (CNF[7:]) to select the host bus interface. The following table summarizes the available settings. Table - : Host Interface Configuration Settings CNF CNF CNF CNF CNF CNF6 CNF7 Host Interface (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB) X Indirect, 8-bit, Intel80 Type (TEA#) 0 (BDIP#) 0 (BURST#) (AB) X Indirect, 8-bit, Intel80 Type (TEA#) 0 (BDIP#) (BURST#) (AB) 0 (AB) SPI (TEA#) 0 (BDIP#) (BURST#) (AB) (AB) IC (TEA#) (BDIP#) 0 (BURST#) 0 (AB) X Indirect, 8-bit, NEC V80 Type (TEA#) (BDIP#) 0 (BURST#) (AB) X Indirect, 8-bit, NEC V80 Type (TEA#) (BDIP#) (BURST#) 0 (AB) X Indirect, 8-bit, Renesas SH 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB) X Indirect, 6-bit, Intel80 Type 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) (AB) X Indirect, 6-bit, Intel80 Type 0 0 (TEA#) 0 (BDIP#) (BURST#) (AB) 0 (AB) SPI (-stream) 0 0 (TEA#) 0 (BDIP#) (BURST#) (AB) (AB) IC 0 0 (TEA#) (BDIP#) 0 (BURST#) 0 (AB) X Indirect, 6-bit, NEC V80 Type 0 0 (TEA#) (BDIP#) 0 (BURST#) (AB) X Indirect, 6-bit, NEC V80 Type 0 0 (TEA#) (BDIP#) (BURST#) 0 (AB) X Indirect, 6-bit, Renesas SH 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (BE#) X Direct, 8-bit, Intel80 Type 0 0 (TEA#) 0 (BDIP#) 0 (BURST#) (BE#) X Direct, 8-bit, Intel80 Type 0 0 (TEA#) 0 (BDIP#) (BURST#) (BE#) 0 (AB) SPI 0 0 (TEA#) 0 (BDIP#) (BURST#) (BE#) (AB) IC 0 0 (TEA#) (BDIP#) 0 (BURST#) 0 (BE#) X Direct, 8-bit, NEC V80 Type 0 0 (TEA#) (BDIP#) 0 (BURST#) (BE#) X Direct, 8-bit, NEC V80 Type 0 0 (TEA#) (BDIP#) (BURST#) 0 (BE#) X Direct, 8-bit, Renesas SH 0 (TEA#) 0 (BDIP#) 0 (BURST#) 0 (AB0) X Direct, 6-bit, Intel80 Type 0 (TEA#) 0 (BDIP#) 0 (BURST#) (AB0) X Direct, 6-bit, Intel80 Type 0 (TEA#) 0 (BDIP#) (BURST#) 0 (AB0) X Direct, 6-bit, Intel PXAxxs 0 (TEA#) 0 (BDIP#) (BURST#) (AB0) 0 (AB) SPI 0 (TEA#) 0 (BDIP#) (BURST#) (AB0) (AB) IC 0 (TEA#) (BDIP#) 0 (BURST#) 0 (AB0) X Direct, 6-bit, NEC V80 Type 0 (TEA#) (BDIP#) 0 (BURST#) (AB0) X Direct, 6-bit, NEC V80 Type 0 (TEA#) (BDIP#) (BURST#) 0 (AB0) X Direct, 6-bit, Renesas SH 0 0 (AB0) X X X X Indirect, 6-bit, TI EBI 0 (AB0) X X X X Direct, 6-bit, TI EBI 0 (BE#) X X X X Indirect, 6-bit, MPC (BE#) X X X X Direct, 6-bit, MPC X = default settings, required settings when using SUU00P00C00 USB Adapter Board = don t care SUP00C00 Evaluation Board User Manual (Rev.) EPSON 9

10 Chapter Installation and Configuration. Configuration Jumpers The SUP00C00 has 6 jumpers which configure various evaluation board settings. The jumper positions for each function are shown below. Table -: Configuration Jumper Settings Jumper Function Position - Position - No Jumper JP COREVDD Normal COREVDD current measurement JP PLLVDD Normal PLLVDD current measurement JP PLLVDD Normal PLLVDD current measurement JP OSCVDD Normal OSCVDD current measurement JP PIOVDD Normal PIOVDD current measurement JP6 HIOVDD Normal HIOVDD current measurement JP7 HIOVDD Source H connector, pin.vdd JP8 PIOVDD Source H9 connector, pin 9.VDD JP9 PIOVDD Source H9 connector, pin 0.VDD JP0 CMVDD Normal CMVDD current measurement JP PIOVDD Normal PIOVDD current measurement JP CMDD Source H9 connector, pin 8.VDD JP IOVDD Source H9 connector, pin 7.VDD JP IOVDD Normal IOVDD current measurement JP SDVDD Normal SDVDD current measurement JP6 SDRAM Width Select (see Note) -bit wide SDRAM 6-bit wide SDRAM = Required settings when using SUU00P00C00 USB Adapter board 0 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

11 Chapter Installation and Configuration JP, JP, JP, JP, JP, JP6, JP0, JP, JP, JP - Power Supplies for the SD JP, JP, JP, JP, JP, JP6, JP0, JP, JP, and JP can be used to measure the current consumption of each SD power supply. When the jumper is at position -, normal operation is selected. When no jumper is installed, the current consumption for each power supply can be measured by connecting an ammeter to pin and of the jumper. The jumper associated with each power supply is as follows: JP for COREVDD JP for PLLVDD JP for PIOVDD JP0 for CMVDD JP for IOVDD JP for PLLVDD JP for OSCVDD JP6 for HIOVDD JP for PIOVDD JP for SDVDD Figure -: Configuration Jumper Locations (JP, JP, JP, JP, JP, JP6, JP0, JP, JP, JP) SUP00C00 Evaluation Board User Manual (Rev.) EPSON

12 Chapter Installation and Configuration JP7 - HIOVDD Source JP7 is used to select the source for the HIOVDD supply voltage. When the jumper is at position -, the HIOVDD voltage must be provided to pin on the H connector. When the jumper is at position -, the HIOVDD voltage is provided by the.v power supply of the board. Figure -: Configuration Jumper Location (JP7) JP8 - PIOVDD Source JP8 is used to select the source for the PIOVDD supply voltage. When the jumper is at position -, the PIOVDD voltage must be provided to pin 9 on the H9 connector. When the jumper is at position -, the PIOVDD voltage is provided by the.v power supply of the board. Figure -: Configuration Jumper Location (JP8) EPSON SUP00C00 Evaluation Board User Manual (Rev.)

13 Chapter Installation and Configuration JP9 - PIOVDD Source JP9 is used to select the source for the PIOVDD supply voltage. When the jumper is at position -, the PIOVDD voltage must be provided to pin 0 on the H9 connector. When the jumper is at position -, the PIOVDD voltage is provided by the.v power supply of the board. Figure -6: Configuration Jumper Location (JP9) JP - CMVDD Source JP is used to select the source for the CMVDD supply voltage. When the jumper is at position -, the CMVDD voltage must be provided to pin 8 on the H9 connector. When the jumper is at position -, the CMVDD voltage is provided by the.v power supply of the board. Figure -7: Configuration Jumper Location (JP) SUP00C00 Evaluation Board User Manual (Rev.) EPSON

14 Chapter Installation and Configuration JP - IOVDD Source JP is used to select the source for the IOVDD supply voltage. When the jumper is at position -, the IOVDD voltage must be provided to pin 7 on the H9 connector. When the jumper is at position -, the IOVDD voltage is provided by the.v power supply of the board. Figure -8: Configuration Jumper Location (JP) JP6 - SDRAM Width Select JP6 is used to select the bus width of the external SDRAM. When the jumper is at position -, the external SDRAM is bits wide and the memory size is M bytes. In this configuration, the memory consists of chips in parallel, each6m bytes and 6 bits wide. When the jumper is at position -, the external SDRAM is 6 bits wide and the memory size is 6M bytes. In this configuration, one memory chip is disabled and only one chip is active (6M bytes and 6 bits wide). Figure -9: Configuration Jumper Location (JP6) EPSON SUP00C00 Evaluation Board User Manual (Rev.)

15 Chapter Technical Description Chapter Technical Description. Power.. Power Requirements The SUP00C00 evaluation board requires an external regulated power supply (.V / A). The power is supplied to the evaluation board through pin of the H header, or pin of the P header. The green LED.V Power is turned on when.v power is applied to the board... Voltage Regulators The SUP00C00 evaluation board has an on-board linear regulator to provide the.8v power required by the SD Display Controller. It also has a step-up switching voltage regulator to generate adjustable ~V, which can be used to power the LED backlight on some LCD panels... SD Power The SD Display Controller requires.8v power and.~.7v or.0~.6v power. COREVDD, PLLVDD, PLLVDD, and OSCVDD require.8v power which is provided by an on-board linear voltage regulator. HIOVDD, PIOVDD, PIOVDD, CMVDD, and IOVDD input power may be in the range.v~.7v or.0v~.6v. When JP7, JP8, JP9, JP, or JP are set to the - position, the corresponding power input is connected to.v. If a different voltage is required, set the corresponding jumper to the - position and connect the external power supply to the evaluation board as indicated in Table -: Configuration Jumper Settings, on page 0. SDVDD input power may be in the range.v~.7v or.0v~.6v. On the evaluation board, SDVDD is connected to.v... LCD Backlight Power On the evaluation board there is an adjustable ~V power supply. At V, the maximum current available is 00mA. At V, the maximum current available is 60mA. This power supply is intended for use to power the LED backlight on some LCD panels. The voltage is adjusted by the R7 pot. Note For LCD panels that use a CCFL backlight, an external power supply must be used to provide power to the inverter for the CCFL backlight. Usually, the inverter current consumption is higher than the maximum 00mA current available from the on-board voltage regulator. SUP00C00 Evaluation Board User Manual (Rev.) EPSON

16 Chapter Technical Description. Clocks The clock for the SD Display Controller is provided by a 0MHz crystal connected to the OSCI and OSCO pins. Additionally, the SUP00C00 evaluation board can also use an oscillator if the DIP footprint is populated. If populated, the oscillator is connected to the CLKI input clock of the SD Display controller. Note For details on the SD clock structure, refer to the SD Hardware Functional Specification, document number X8A-A-00-xx.. Reset The SD Display Controller on the SUP00C00 evaluation board can be reset using a push-button switch (SW), or via an active low reset signal from the host development platform (pin 0 on the H connector). Figure -: Reset Switch (SW) Location 6 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

17 Chapter Technical Description. Memory.. SDRAM The SUP00C00 evaluation board has SDRAM ICs, each 8Mbit x6-bit, CL= in a TSOP package. When the SD Display Controller is configured for -bit wide DRAM bus, both SDRAM ICs are used. When the SD Display Controller is configured for 6-bit wide DRAM bus, only one of the SDRAM ICs is used and the other SDRAM ICs is disabled by having its chip select input pulled high to inactive state, by putting jumper JP6 in - position... Serial Flash Memory with SPI interface The SD Display Controller has a SPI Flash Memory interface which is connected to a Mbit Flash EPROM.. Host Interface.. Direct Host Bus Interface Support All SD host interface pins are available on connectors H and H. This allows the SUP00C00 evaluation board to be connected to a variety of development platforms. For SD host interface pin mapping, refer to the SD Hardware Functional Specification, document number X8A-A-00-xx. The following figure shows the location of host bus connectors H and H. H is a 0. x 0. 0-pin header (0x) and H is a 0. x 0. -pin header (7 x ). Figure -: Host Bus Connector Location (H and H) For the pinout of connectors H and H, see Section Chapter 6, Schematic Diagrams on page 9. SUP00C00 Evaluation Board User Manual (Rev.) EPSON 7

18 Chapter Technical Description.. Connecting to the Epson SUU00P00C00 USB Adapter Board The SUP00C00 evaluation board is designed to connect to a SUU00P00C00 USB Adapter Board. The USB adapter board provides a simple connection to any computer via a USB.0 connection. The SUP00C00 directly connects to the USB adapter board through connectors P and P. The USB adapter board also supplies the.v power required by the SUP00C00 evaluation board. HIOVDD should be configured for.v and JP7 should be set to the - position. When the SUP00C00 is connected to the SUU00P00C00 USB Adapter board, there are LEDs on the SUP00C00 which provide a quick visual status of the USB adapter. LED blinks to indicate that the USB adapter board is active. LED turns on to indicate that the USB has been enumerated by the PC. The following diagram shows the location of connectors P and P. P and P are mm x mm, 0-pin headers (0 x ) located on the underside of the board. Figure -: USB Adapter Connector Locations (P and P) For the pinout of connectors P and P, see Section Chapter 6, Schematic Diagrams on page 9. Note A windows driver must be installed on the PC when the SUP00C00 is used with the SUU00P00C00 USB Adapter Board. The SDxxxUSB driver is available at 8 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

19 Chapter Technical Description.6 LCD Interface The LCD interface uses the FPIO[:0] and FPIO[7:0] pins. All signals on these pins are available on connectors H, H6, and H7. Connectors H, H6, and H7 are 0. x 0., 0-pin headers (0 x ). The following diagram shows the location of these connectors. Figure -: FPIO and FPIO Connectors Location (H, H6, H7) For the pinout of connectors H, H6, and H7, see Section Chapter 6, Schematic Diagrams on page FPIO Interface The FPIO interface signals have multiplexed functions. All FPIO interface signals, except FPIO8 and FPIO9, are available on connector H6. FPIO8 and FPIO9 signals go through 0 ohm resistors and are available on connector H7. The FPIO interface can be configured as a LCD interface, 8-bit RGB input stream interface, or 8-bit YUV camera interface and keyboard interface. For SD FPIO interface pin mapping, refer to the SD Hardware Functional Specification, document number X8A-A-00-xx..6. FPIO Interface All FPIO interface signals are available on connectors H and H7. For SD FPIO interface pin mapping, refer to the SD Hardware Functional Specification, document number X8A-A-00-xx. SUP00C00 Evaluation Board User Manual (Rev.) EPSON 9

20 Chapter Technical Description.7 Camera / IC Interface The SD Display Controller has a Camera interface. All the camera interface signals are available on connector H0. To control the camera, the SD Display Controller has an IC master interface. The SDA and SCL signals are pulled high to CMVDD by. kω resistors and are available on connector H0. The reset signal provided on H0 is active low and is pulled to HIOVDD when inactive. Connector H0 is a 0. x 0., 0-pin header (0 x ). The following figure shows the location of the connector H0. Figure -: Camera Connector Location (H0) For the pinout of connector H0, see Section Chapter 6, Schematic Diagrams on page 9. 0 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

21 Chapter Technical Description.8 Keypad Interface Note The keyboard is non-operational with the buttons SW-SW, mounted as they are on the board. In order to make the keyboard operational, the user must remove the buttons SW-SW from the board and mount them back on the board, but rotated by 90 degrees or 70 degrees. The buttons will not match the footprint on the PCB, but this is how they must be mounted on the board. The SD Display Controller can support up to a x matrix keypad, but the SUP00C00 evaluation board includes only a x keypad. The keypad interface can be configured to use either the FPIO interface or Host interface pins. For SD pin mapping, refer to the SD Hardware Functional Specification, document number X8A-A-00-xx. The keypad interface is configured for either the FPIO interface or Host Interface pins using 0 ohm resistors. SD M/R#, AB[0:9], AB[6:] FPIO[:0], FPIO[6:] Zero Ohms Zero Ohms x Keypad Figure -6: Keypad Interface Zero Ohm Resistor Overview Diagram The keypad can be configured to connect to of source pins on the SD. Depending of the configuration, the input lines must be pulled high to corresponding power supply. The source connection for the keypad is determined by populating the correct set of zero ohm resistors as described below. Table -: Keypad Zero Ohm Resistor Summary Keypad Pin Function Populate only set of the zero ohm resistors below Zero Ohm For FPIO Zero Ohm For Host Interface KBR0 R9 R8 KBR R9 R86 KBR R9 R87 KBC0 R9 R88 KBC R9 R90 KBC R96 R89 Power (HIOVDD or PIOVDD) R8 R80 SUP00C00 evaluation board comes configured with the keyboard interface from the Host Interface pins, so resistors R8 ~ R90 and R80 are populated and R9 ~ R96 and R8 are not populated. SUP00C00 Evaluation Board User Manual (Rev.) EPSON

22 Chapter Technical Description.9 IS Interface The SD Display Controller has an IS Audio output interface. All of the IS interface signals are available on connector H8. The IC signals, available on the same connector, can be used to program an external IS Audio DAC IC. Connector H8 is a 0. x 0., -pin header (x). The following figure shows the location of the connector H8. Figure -7: IS Connector Location (H8) For the pinout of connector H8, see Section Chapter 6, Schematic Diagrams on page 9. EPSON SUP00C00 Evaluation Board User Manual (Rev.)

23 Chapter Technical Description.0 PWM Connector The SD Display Controller has two PWM outputs which are available on connector H9. The other pins on connector H9 are used to connect the external power supplies to CMVDD, IOVDD, PIOVDD, and PIOVDD, if a voltage level different than.v is required. Note that connector H9 is not populated on the SUP00C00 evaluation board. Connector H9 is a 0. x 0., 0-pin header (x). The following figure shows the location of the connector H9. Figure -8: PWM Connector Location (H9) For the pinout of connector H9, see Section Chapter 6, Schematic Diagrams on page 9. SUP00C00 Evaluation Board User Manual (Rev.) EPSON

24 Chapter Technical Description. C Debugger Port The SD contains an embedded C microprocessor core. The debug monitor interface is available on connector H for firmware debugging using C Debugger. In order to use connector H, zero ohm resistors must be configured depending on the desired SD configuration. The C debugger function can be sourced from sets of the host interface pins or from a set of FPIO pins. SD AB[:7], AB6 or BS# FPIO[7, 6,,,, 0] DB[:8] Zero Ohms Zero Ohms Zero Ohms H C Debugger Port Figure -9: C Debugger Zero Ohm Resistor Overview Diagram The connection to the C Debugger port is determined by populating the correct set of zero ohm resistors as described below. C Pin Function PEDST0 PEDST PEDST PEDCLK PEDSIO PEDCPCO Table -: C Debugger Port H7 Zero Ohm Selection C Debugger port from FPIO pins R7 populated R0 not populated R7 populated R not populated R7 populated R not populated R70 populated R not populated R7 populated R not populated R7 populated R not populated Populate only set of the zero ohm resistors below C Debugger port from AB[:7], AB6 or BS# pins R6 populated R0 not populated R66 populated R0 not populated R67 populated R00 not populated R69 populated R99 not populated R68 populated R98 not populated C Debugger port from DB[:8] pins R80 populated R08 not populated R79 populated R07 not populated R78 populated R06 not populated R76 populated R0 not populated R77 populated R0 not populated R6 populated (from AB6) R6, R97 not populated R8 populated R6 populated (from BS#) R0 not populated R6, R09 not populated SUP00C00 board comes configured for the C Debugger port from the Host Interface AB[:6] pins, so resistors R6, R6 ~ R69 are populated and R97 ~ R0 are not populated, R0 ~ R are populated and R6, R70 ~ R8 are not populated. EPSON SUP00C00 Evaluation Board User Manual (Rev.)

25 Chapter Technical Description Connector H is a 0. x 0., 0-pin header (x). The following figure shows the location of the connector H. Figure -0: C Debugger Connector Location (H) For the pinout of connector H, see Section Chapter 6, Schematic Diagrams on page 9.. JTAG Interface The SD Display Controller has a JTAG interface. All the JTAG signals are available on connector H. Note that connector H is not populated on the SUP00C00 evaluation board. Connector H is a 0. x 0., -pin header (6x). The following figure shows the location of the connector H. Figure -: JTAG Connector Location (H) For the pinout of connector H, see Section Chapter 6, Schematic Diagrams on page 9. SUP00C00 Evaluation Board User Manual (Rev.) EPSON

26 Chapter Parts List Chapter Parts List Table - : SUP00C00 Parts List Item Quantity Reference Part Description 0 C,C,C,C,C,C6,C7,C 8,C7,C0,C,C,C6, C7,C8,C9,C0,C,C 9,C0,C,C,C,C9, C0,C,C,C,C,C 0.uF Yageo America 00F0Z7B0D, C00,C6,C67,C69,C7,C7, C7,C7,C76,C77,C78,C7 9,C80,C8,C8,C8,C8, C8,C86,C87,C06 C9,C0,C,C,C,C,C,C6,C,C,C,C,C,C6,C7,C8,C, C,C6,C7,C8,C6,C 7,C8,C9,C60,C6,C6, 0.0uF Yageo America 00ZRYV7BB0, C00 C68,C88,C89,C90,C9,C9,C9,C9,C9,C96,C97, C98,C99,C00,C0 C8,C nf Yageo America 00R0K9B0D, C00 C9,C,C6,C70,C7 0uF Panasonic - ECG ECJ-CV0J06M, C080 C6,C66 8pF Panasonic - ECG ECJ-0ECH80J, C00 6 C0.uF 0V Taiyo Yuden LMKBJKG-T, C080, CAP CER.UF 0V X7R C0 0uF V Taiyo Yuden GMKBJ06KN-T, C0, CAP CER 0UF V XR 0 8 C0 0pF Panasonic - ECG ECJ-0ECHJ, C00 9 C0 uf Panasonic - ECG ECJ-0EB0J0M, C00 0 D,D,D Panasonic - SSG LNJ08G8LRA, LED060, LED GREEN SS TYPE LOW CUR SMD 0 D,D,D6,D7,D8,D9,D0, D,D,D MBR00 F ACHC--T F ACF8-0 H JTAG Micro Commercial Co. MBR00-TP, SOD-, DIODE SCHOTTKY 0V 00MA SOD TDK ACHC--T, FILTR TERM 0MHZ TO 00MHZ SMD TDK ACF8-, FILTER -TERM 60MHZ 00MA SMD Samtec TSW G-D Do not populate H,H9 Samtec TSW-0-07-G-D, Do not populate H9 6 H HEADER_0X Samtec TSW-0-07-G-D 7 H HEADER_7X Samtec TSW-7-07-G-D 8 H,H6,H7 Samtec TST-0-0-G-D 9 H8 IS PORT Samtec TSW--07-G-D 0 H0 CAMERA Samtec TSW-0-07-G-D 6 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

27 Chapter Parts List 0 6 JP,JP,JP,JP,JP,JP6 JP0,JP,JP,JP JP7,JP8,JP9,JP,JP,J P6 6 L,L,L,L,L,L6 Ferrite L7 0uH SIP CONN HEADER VERT POS.00 TIN or GENERIC SIP CONN HEADER VERT POS.00 TIN or GENERIC Steward HZ060B7R-0, R060, FERRITE 00MA 98 OHMS 060 SMD Panasonic - ECG ELL-6SH00M, IND_ELL6, COIL 0UH 00MA CHOKE SMD P,P HEADER_0X M 0-8-RB, HDRX0/MM 6 6 R,R,R,R,R,R6,R7,R 8,R9,R0,R,R,R,R,R,R6,R7,R8,R9, R0,R,R,R,R,R,R6,R7,R8,R9,R0, R,R,R,R,R,R 6,R7,R8,R9,R0,R, R,R,R,R,R6,R 7,R8,R9,R0,R,R, R,R,R7,R8,R9,R6 0,R6,R6,R88 % R R,R6,R70,R7,R7,R7,R7,R7,R76,R77,R78, R79,R80,R8,R9,R96,R9 7,R98,R99,R00,R0,R 0,R06,R08,R,R, R6,R7,R8,R9,R 0,R,R,R,R, R,R6,R7,R8,R 9,R0,R,R6,R6, R6,R67,R69,R70,R 8,R9,R9,R9,R9, R9,R96,R97,R98,R 99,R00,R0,R0,R6, R7,R8,R9 R6,R6,R6,R66,R67,R6 8,R69,R8,R8,R86,R87, R0,R0,R0,R07,R 09,R0,R,R,R, R,R6,R7,R8,R 9,R0,R,R,R, R,R,R6,R7,R 8,R9,R0,R,R, R,R,R,R,R 60,R6,R6,R66,R68, R7,R80,R8,R86,R 87,R88,R89,R90,R0, R0,R0,R06,R07,R 08,R09,R0,R,R, R,R,R Table - : SUP00C00 Parts List Item Quantity Reference Part Description 0_np R00 Do not populate 0 R00 9 R8 M R00 0 R8 k R00 SUP00C00 Evaluation Board User Manual (Rev.) EPSON 7

28 Chapter Parts List 0 R89,R9,R9,R9,R9,R 6,R7,R8,R8,R8 0k R00 R90 0k % R00 R,R,R7 0 R060 R7,R8,R9 70 % R00 R7 0k R00 6 R7 00k Panasonic - ECG EVN-ESX0B, POT 00K OHM MM CARBON TRIM SMD 7 R76 6k R00 8 R77.k % R00 9 R78,R79.k R SH,SH,SH,SH,SH,S H6,SH7,SH8,SH9,SH0,S H,SH,SH,SH,SH,SH6.00 in. Jumper Shunt SW SW_DIPSW 0 SW,SW,SW,SW,SW6,SW7,SW8,SW9,SW0,S W Table - : SUP00C00 Parts List Item Quantity Reference Part Description SW TACT-SPST TPGND,TP.VDD TP_SMT U SDPBGA6 U MP-VMF 6 U,U 8M6 DRAM 7 U MIC700-.8WS 8 U6 LM7Y 9 X MA M 0 0 Y -Pin DIP Sullins Electronics Corp. STC0SYAN JUMPER SHORTING TIN CTS Corp 8-LPST, DIPSW, SWITCH DIP HALF PITCH POS ITT Industries KSC0JLFS, SWITCH TACT SILVR 0GF J-LEAD Keystone 0, TP_06, PC TEST POINT MINIATURE SMT ST Microelectronics MP-VMF6P, IC SRL FLASH MBIT V 6-SOIC Qimonda HYB9S860FE-7, IC SDRAM 8MBit -TSOP Micrel MIC700-.8WS, SOT-, Alternate MIC900-.8WS National Semiconductor LM7YMF/NOPB, SOT-, IC CONV BOOST 0V FET SW SOT- Epson MA M, CRYSTAL MHZ 8PF SMD AMP Do not populate 8 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

29 Chapter 6 Schematic Diagrams Chapter 6 Schematic Diagrams CORE PLL PLL OSC HIO SDVDD PIO PIO IO CM Board default configuration:.00 in. Jumper Shunt SH JP.8VDD CORE -indirect interface Intel 80, 6-bit FPIO[:0], L8 FPIO0,, AB[0:0] AB0 FPIO0 H6 M8 FPIO -EID signals from FPIO interface C C C C C C6 C7 C8 AB AB0 FPIO H7 P8 FPIO AB AB FPIO G R8 FPIO 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF AB G AB FPIO P7 FPIO -C Debug port from AB[:6] AB AB FPIO G R7 FPIO AB AB FPIO G T7 FPIO6 AB6 R97 0_np pab6 F AB FPIO6 N7 FPIO7 -Keybord interface on AB[0:] C9 C0 C C C C C C6 AB7 R98 0_np pab7 AB6 FPIO7 F M7 FPIO8 AB8 R99 0_np pab8 G6 AB7 FPIO8 L7 FPIO9 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF D D AB9 R00 0_np pab9 AB8 FPIO9 G7 K7 FPIO0 AB0 R0 0_np pab0 AB9 FPIO0 F T FPIO AB R0 0_np pab AB0 FPIO F R6 FPIO AB AB FPIO F6 R FPIO AB AB FPIO E P FPIO Place a 0.0uF and a 0.uF cap on each AB AB FPIO E M6 FPIO COREVDD power pin of the SD AB AB FPIO D L6 FPIO6 AB6 AB FPIO6 D R FPIO7 AB7 AB6 FPIO7 E T FPIO8 AB8 D AB7 FPIO8 P FPIO9.00 in. Jumper Shunt.00 in. Jumper Shunt AB9 AB8 FPIO9 D P FPIO0 SH.8VDD SH.8VDD AB0 AB9 FPIO0 JP JP C N FPIO L PLL L PLL AB0 FPIO R FPIO Ferrite Ferrite DB[:0] DB0 FPIO L T FPIO DB K6 DB0 FPIO FPIO[7:0] DB DB K P FPIO0 PLLVDD C7 C8 PLLVDD C0 C DB DB FPIO0 K P6 FPIO nf C9 nf C DB K DB FPIO P FPIO 0.uF 0uF 0.uF 0uF DB DB FPIO K R FPIO DB6 DB FPIO K R FPIO L L DB7 DB6 FPIO J T FPIO Ferrite Ferrite DB8 R0 0 pdb8 DB7 FPIO J M FPIO6 GND GND DB9 R0 0 pdb9 DB8 FPIO6 J P FPIO7 DB0 R0 0 pdb0 DB9 FPIO7 J6 N FPIO8 DB R06 0 pdb DB0 FPIO8 J7 P FPIO9 DB R07 0 pdb DB FPIO9 H K0 pfpio0 R0 0 FPIO0.00 in. Jumper Shunt DB R08 0 pdb DB FPIO0 H T pfpio R 0 FPIO SH.8VDD JP DB H DB FPIO R FPIO L OSC DB DB FPIO H L0 pfpio R 0 FPIO Ferrite DB FPIO N pfpio R 0 FPIO FPIO CS# L P FPIO CS# FPIO, M/R# M T pfpio6 R 0 FPIO6 OSCVDD C C M/R# FPIO6 pfpio7 FPIO7 RD# M N0 R 0 RD# FPIO7 RD/WR# M K9 FPIO8 0.0uF 0.uF RD/WR# FPIO8 FPIO9 BE0# M P0 BE0# FPIO9 FPIO0 L6, BE# N R0 BS# R09 0 pbs# BE# FPIO0 M L9 FPIO Ferrite C BS# FPIO FPIO GND C, BURST# N M9 BURST# FPIO, BDIP# N T0 FPIO Place a 0.0uF and a 0.uF cap on each BDIP# FPIO P P9 FPIO OSCVDD power pin of the SD, TEA# TEA# FPIO P R9 FPIO WAIT# WAIT# FPIO R K8 FPIO6 IRQ IRQ FPIO6 FPIO7,, RESET# R T9 RESET# FPIO7 MEMA[:0] CLKI B SDPBGA6 A9 R % MEMA0.00 in. Jumper Shunt.00 in. Jumper Shunt CLKI MEMA0 BUSCLK J B9 R % MEMA SH6 HIOVDD SH PIOVDD BUSCLK MEMA JP6 JP OSCI A F8 R % MEMA HIO PIO A6 OSCI MEMA C9 R % MEMA OSCO OSCO MEMA G8 R % MEMA.00 in. Jumper Shunt MEMA D9 R6 % MEMA SH7 MEMA CNF0 J0 A0 R7 % MEMA6 JP7 HIOVDD PIOVDD CNF0 MEMA6 CNF K E9 R8 % MEMA7 CNF MEMA7.VDD MEMA8 CNF K6 F R9 % CNF MEMA8 HIOVDD G R0 % MEMA9 HIOVDD_IN C C6 C7 C8 C9 C0 C MEMA9 G R % MEMA0 R % MEMA0 M H0 R % MEMA HIOVDD SOURCE 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF SPICS# R % SPICS# MEMA L G6 R % MEMA SPICLK SPIDIO R6 % SPICLK MEMA L H R7 % MEMBA0.00 in. Jumper Shunt SPIDIO MEMBA0 H R8 % MEMBA SH8 MEMBA J R9 % MEMCS# JP8 C C C C C6 C7 C8 MEMCS# N H R0 % WSIO WSIO MEMRAS# MEMRAS#.VDD R % SCKIO N H6 MEMCAS# PIOVDD 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF N SCKIO MEMCAS# H R % SDO SDO MEMWE# MEMWE# MEMDQ[:0] PIOVDD_IN N6 C0 R % MEMDQ0 MCLKO MCLKO MEMDQ0 A R % MEMDQ PIOVDD SOURCE MEMDQ E0 R % MEMDQ MEMDQ CMDAT0 C G9 R6 % MEMDQ.00 in. Jumper Shunt Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each MEMDQ CMDAT C CMDAT0 MEMDQ C R7 % SH9 HIOVDD power pin of the SD PIOVDD power pin of the SD CMDAT MEMDQ CMDAT C F R8 % MEMDQ JP9 CMDAT MEMDQ MEMDQ6 CMDAT C6 B R9 % CMDAT MEMDQ6.VDD R0 % MEMDQ7 CMDAT D E CMDAT MEMDQ7 PIOVDD CMDAT A8 B R % MEMDQ8 PIOVDD_IN.00 in. Jumper Shunt.00 in. Jumper Shunt CMDAT MEMDQ8 MEMDQ9 CMDAT6 D7 C R % SH0 JP PIOVDD SH JP0 CMVDD CMDAT6 MEMDQ9 CMDAT7 E6 B6 R % MEMDQ0 PIOVDD SOURCE PIO CM CMDAT7 MEMDQ0 MEMDQ B CMFIELD C8 C6 R % CMFIELD MEMDQ B R % MEMDQ.00 in. Jumper Shunt CMHREF F7 D6 CMHREF MEMDQ CMVREF B8 G0 R6 % MEMDQ SH MEMDQ CMCLKIN B7 CMVREF MEMDQ F R7 % JP PIOVDD CMVDD CMCLKIN MEMDQ A7 G R8 % MEMDQ CMCLKOUT CMCLKOUT MEMDQ.VDD D0 R9 % MEMDQ6 MEMDQ6 CMVDD, SCL E8 F9 R0 % MEMDQ7 CMVDD_IN C9 C0 C C C SCL MEMDQ7, SDA D8 B R % MEMDQ8 SDA MEMDQ8 F0 R % MEMDQ9 CMVDD SOURCE 0.uF 0.uF 0.uF 0.uF 0.uF MEMDQ9 D R % MEMDQ0 MEMDQ0 M A R % MEMDQ.00 in. Jumper Shunt PWM PWM MEMDQ M C R % MEMDQ SH PWM PWM MEMDQ A R6 % MEMDQ JP C C C6 C7 C8 MEMDQ D R7 % MEMDQ.VDD TCK MEMDQ8 K B R8 % MEMDQ IOVDD 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF TMS TCK MEMDQ K C R9 % MEMDQ6 IOVDD_IN TDI TMS MEMDQ L6 D R0 % MEMDQ7 TDO TDI MEMDQ6 L E R % MEMDQ8 IOVDD SOURCE R 0_np TDO MEMDQ7 K F R % MEMDQ9 TRST MEMDQ9 F R % MEMDQ0 Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each MEMDQ0 G R % MEMDQ PIOVDD power pin of the SD CMVDD power pin of the SD R6 0 MEMDQ L J R7 % TESTEN MEMDQM0 MEMDQM0 A J R8 % MEMDQM MEMDQM A VCP J R9 % MEMDQM.00 in. Jumper Shunt.00 in. Jumper Shunt VCP MEMDQM J R60 % MEMDQM SH IOVDD SH.VDD MEMDQM JP JP R6 % MEMCLK IO SDVDD MEMCLK A MEMCKE J6 R6 % MEMCKE COREVDD Signal traces must be less than cm. C9 C0 C C C C C Place these resistors as GND GND GND close to U as possible. 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF AB[0:0] pab6 R6 0 R6 0_np pbs# For Indirect pab R6 0 A Host pab0 R66 0 C6 C7 C8 C9 C60 C6 C6 A Interface pab9 R67 0 IOVDD H pab7 R uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF pab8 R69 0 H FPIO[7:0] TMS pfpio R70 0_np C_PEDCLK TDI pfpio7 R7 0_np C_PEDSIO TDO For REG[00Ch] bit 0 = pfpio R7 0_np C_PEDST Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each TCK 0 b, C debug pins on pfpio R7 0_np C_PEDST IOVDD power pin of the SD SDVDD power pin of the SD FPIO pfpio0 R7 0_np C_PEDST0 0 pfpio6 R7 0_np C_PEDCPCO IOVDD SDVDD JTAG pdb0 pdb9 For Direct 8-bit pdb Interface pdb pdb pdb8 R76 0_np C DEBUG PORT Title R77 0_np SD QFP6 R78 0_np R79 0_np Size Document Number Rev <Doc>.0 R80 0_np R8 0_np Tuesday, May 7, 008 Date: Sheet of C A A6 B C C7 D E E F G H H8 H9 J8 J9 K L L M0 N N8 P6 R T T6 B B B6 PLL PLL OSC COREVDD C COREVDD D6 COREVDD E COREVDD E6 COREVDD L COREVDD M6 COREVDD N6 COREVDD T PLLVDD B PLLVDD A OSCVDD B HIOVDD E HIOVDD G HIOVDD J HIOVDD L SDVDD A SDVDD B0 SDVDD D SDVDD E SDVDD F6 SDVDD H PIOVDD T PIOVDD T6 PIOVDD T8 PIOVDD N9 PIOVDD R PIOVDD R6 PIOVDD T IOVDD M CMVDD E7 U Figure 6-: SUP00C00 Schematics ( of ) SUP00C00 Evaluation Board User Manual (Rev.) EPSON 9

30 Chapter 6 Schematic Diagrams.VDD U R8 M OSCO OSCI U.VDD SPICS# 7 CS# VCC MEMA[:0] SPICLK 6 MEMA CLK 6 R8 MEMA NC/A VDD SPIDIO DIN NC 8 C6 C6 k MEMA0 A VDD R8 0 DOUT NC 0.uF 0uF X MEMA9 A0 VDD 7 NC.VDD MEMA8 A9 VDDQ R8 0 HOLD# NC 6 MEMA7 A8 VDDQ 9 NC XIN XOUT 9 MEMA6 A7 VDDQ R86 0 W#/VPP NC D MEMA A6 VDDQ 9 NC NC NC D 0 0 MEMA A MEMBA NC 9 C6 MA M C66 MEMBA MEMA A BA 6 0 MEMBA0 MP-VMF 8pF 8pF MEMBA0 MEMA A BA0 MEMA A MEMDQM MEMA0 A DQMH 9 A0 DQML MEMDQM0 MEMWE# GND GND MEMDQ[:0] 6 MEMWE# MEMDQ0 WE# 7 MEMCAS# MEMCAS# MEMDQ D0 CAS# 8 MEMRAS# MEMRAS# MEMDQ D RAS# 9 MEMCS# R87 0 MEMCS# MEMDQ D CS# 7 HIOVDD MEMDQ D 8 MEMCKE MEMCKE MEMDQ D CKE 7 Y 0 MEMCLK MEMCLK MEMDQ6 D CLK 8 VDD OE MEMDQ7 D6 C67 C R88 % CLKI MEMDQ8 D7 MEMDQ9 D8 NC 0 GND OUT 0.uF 0.0uF MEMDQ0 D9 R89 MEMDQ -Pin DIP D0 7 0k MEMDQ D 8 TTL/CMOS Oscillator MEMDQ D 8 0 MEMDQ D Q MEMDQ D Q 6 D Q IOVDD C Q 6 C This resistor is used to pull down CLKI input when 8M6 DRAM oscillator is not used. If an oscillator is used,.vdd then this resistor can be U removed. MEMA[:0] MEMA 6 MEMA NC/A VDD MEMA0 A VDD SW_DIPSW MEMA9 A0 VDD 7 SW A9 VDDQ MEMA8 MEMA7 A8 VDDQ 9.00 in. Jumper Shunt HIOVDD MEMA6 A7 VDDQ SH6 MEMA A6 VDDQ 9 0.VDD MEMA A MEMBA CNF0 9 MEMA A BA MEMBA0 CNF 6 0 R90 MEMA A BA0 CNF 0k % MEMA A R9 MEMDQM MEMA0 A DQMH 9 0k SW A0 DQML MEMDQM MEMWE# R9 MEMDQ[:0] 6 R9 RESET#,, MEMDQ6 WE# 7 MEMCAS# JP6 0k 0k MEMDQ7 D0 CAS# 8 MEMRAS# C69 MEMDQ8 D RAS# 9 B MEMDQ9 D CS# MEMCS# 7 0.uF B MEMDQ0 D MEMCKE 8 MEMDQ D CKE 7 0 MEMCLK SDRAM I/F MEMDQ D CLK 8 MEMDQ D6 SDRAM I/F MEMDQ D7 - BIT MEMDQ D8 NC 0-6BIT HIOVDD SW TACT-SPST MEMDQ6 D9 MEMDQ7 D0 7 MEMDQ8 D 8 MEMDQ9 D 8 0 MEMDQ0 D Q TP MEMDQ D Q 6 R9 R96 R97 R98 R99 R0.VDD U.8VDD Q R00 D 0_np 0_np 0_np 0_np 0_np 0_np MIC700-.8WS Q 6 0_np IN OUT 8M6 DRAM,, AB[0:0] AB C70 C7 C7 AB C7 Place a 0.0uF and a 0.uF cap on each Place a 0.0uF and a 0.uF cap on each AB0 0uF 0.uF 0.uF 0uF.VDD VDD power pin of the two SDRAM chips..vdd VDDQ power pin of the two SDRAM chips., BE#, BURST#, BDIP#, TEA# C7 C7 C76 C77 C78 C79 C80 C8 C8 C8 C8 C8 C86 C87 A A 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF 0.uF R0 R0 R0 R0 R06 R07 R08 0_np 0_np 0_np SDRAM 8Mb x 6-bit x banks SDRAM 8Mb x 6-bit x banks R9 0k TAB GND C88 C89 C90 C9 C9 C9 C9 C9 C96 C97 C98 C99 C00 C0 Title SDRAM / Flash / Clocks / Reset /.8V Supply 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF 0.0uF CNF CNF CNF6 CNF7 Size Document Number Rev CNF B <Doc>.0 Thursday, May, 008 Date: Sheet of Figure 6-: SUP00C00 Schematics ( of ) 0 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

31 Chapter 6 Schematic Diagrams R00 and R0 are not resistors on PCB. They P are external wires D added to the board. D DB[:0] 6 R09 0 WAIT# HIOVDD BE# R R 0_np RD/WR# H 9 0 R00 0 R 0 RD# IRQ R 0 RD# R0 0 BE# DB BE0#, BE# 6 R 0 DB 6 DB0 RD# R DB DB 9 0 DB DB R6 0 R7 0 DB DB DB R8 0 6 R9 0 DB DB0 6 DB R R 0 DB0 DB9 7 8 DB9 R R 0 DB8 DB8 9 0 R 0 DB7 DB7 DB6 R 0 R6 0 DB DB6 DB R7 0 6 R8 0 DB DB 6 DB R R0 0 DB DB 7 8 DB0 R DB 9 0 DB HEADER_0X BS# AB0 C 6 C AB 7 8 TP.VDD AB 9 0 TP_SMT P.VDD HEADER_0X CS# R 0 R 0_np M/R# R 0 6,, AB[0:0] HEARTBEAT ENUMERATED H 6 R 0_np AB0 AB AB AB9 R6 0_np 7 8 R7 0_np AB8 AB AB6 AB7 R8 0_np 9 0 AB7 6 AB8 R9 0_np AB6 AB9 8 AB0 AB R0 0_np R 0_np AB AB 0 AB AB R 0_np 6 R 0_np AB AB AB AB R 0_np 7 8 R 0_np AB0 AB AB6 AB9 R6 0_np 9 0 R7 0_np AB8 AB7 6 AB8 R8 0_np AB7 AB9 7 8 AB0 AB6 R9 0_np R0 0_np AB 9 0 M/R# M/R#, AB R 0_np 6 R 0_np AB CS# RD/WR# RD/WR# AB R 0_np AB CS# 7 8 R 0 BE0# B AB0 R 0_np BE0# 9 0 IRQ IRQ 6 TEA#, B R0 0 AB 7 8 WAIT# WAIT# AB, BDIP# R , BURST# RESET#,, HEADER_0X HIOVDD_IN HIOVDD.VDD BUSCLK R0 and R0 are not resistors on PCB. They Place these resistors as close as possible are external wires HEADER_7X R6 to H and H headers. added to the board. 0k This resistor is used to pull down BUSCLK input when it is not used. If BUSCLK input is used, then this resistor can be removed. HEARTBEAT ENUMERATED.VDD A D D D TPGND A LED LED.V Power TP_SMT TP Title Host connectors Size Document Number Rev B <Doc>.0 Tuesday, August 9, 008 Date: Sheet of 7 9 K K K A A R7 R8 R9 70 % 70 % 70 % A Figure 6-: SUP00C00 Schematics ( of ) SUP00C00 Evaluation Board User Manual (Rev.) EPSON

32 Chapter 6 Schematic Diagrams FPIO[7:0], FPIO[:0] H6 H FPIO0 FPIO0 FPDAT0 FPIO FPIO6 FPIO FPDAT FPDAT6 FPIO6 FPIO 6 FPIO7 FPIO FPDAT 6 FPDAT7 FPIO7 FPIO 7 8 FPIO FPDAT 7 8 FPIO 0 FPIO FPDAT 9 0 FPIO FPIO FPDAT FPIO6 D FPIO6 FPDAT6 FPIO7 D 6 FPIO7 FPDAT7 6 FPIO8 7 8 FPIO8 FPDAT8 7 8 FPIO9 9 0 FPIO9 FPDAT9 9 0 FPIO0 FPIO0 FPDAT0 FPIO FPIO FPDAT FPIO 6 FPIO FPDAT 6 FPIO 7 8 PIOVDD FPIO FPDAT 7 8 PIOVDD FPIO 9 0 VBACKLIGHT FPIO FPDAT 9 0 VBACKLIGHT FPIO FPIO FPDAT FPIO FPIO7 FPSHIFT FPIO 6 FPIO6 FPDRDY 6 FPIO0 7 8 FPIO FPLINE 7 8 FPIO 9 0 FPIO FPFRAME 9 0 FP LCD Connector FP LCD Connector Place these Place these H7 resistors close to resistors close to H8 connector. H6 connector. FPIO6 POLGMA FPIO R60 0 POLGMA DEXR C 6 WSIO R6 0_np R6 0_np C CPV 7 8 OE 9 0 FPIO9 FPDAT9 FPIO R6 0 DEXR FPIO0 FPDAT0 SCKIO R7 0_np R6 0_np FPIO FPDAT 6 FPIO FPDAT 7 8 FPIO FPDAT 9 0 FPIO7 R6 0 CPV SDO R8 0_np R6 0_np LED_DIM_OUT FPIO FPIO 9 0 FPIO9 R66 0 LED_DIM_OUT PWM R67 0_np H8 FPIO8 6 FPIO9 7 8 FPIO8 R68 0 OE FPIO0 9 0 FPSO FPIO MCLKO R9 0_np R69 0_np MCLKO MCLKO 0 9 FP Extended LCD Connector FPIO8 R70 0_np WSIO WSIO SDO SDO Place these SCKIO SCKIO 6 Adjustable Step Up Power Supply resistors close to, SCL 8 7 B V@ 00mA to V@60mA H7 connector., SDA 0 9 B D TP IOVDD R7 0.VDD F L7 MBR00 F VBACKLIGHT ACHC--T 0uH ACF8- R7 0 A K IS PORT C0 0uF V R7 0k H9 R7 0pF 00k U6 VIN SW PWM PWM 6 PWM IOVDD_IN 7 8 CMVDD_IN PIOVDD_IN 9 0 PIOVDD_IN /SHDN GND R77 A A LM7Y.k % Vout=.x[+(R7+R0)/R9] (V) Title LCD, IS and PWM connectors Size Document Number Rev B <Doc>.0 Thursday, May, 008 Date: Sheet of R76 6k FB PWM/PWR PORT 9 C0 R7.uF 0V 0k C0 Figure 6-: SUP00C00 Schematics ( of ) EPSON SUP00C00 Evaluation Board User Manual (Rev.)

33 Chapter 6 Schematic Diagrams H0 CMVDD D CMDAT0 CMDAT D 6 CMDAT CMDAT 7 8 CMDAT CMDAT R78 R CMDAT6 CMDAT7.k.k CMCLKIN CMVREF CMCLKOUT CMHREF CMVDD 6 7 8, SCL RESET#,, 9 0, SDA CMFIELD C0 uf CAMERA If Kypad i/f is from M/R#, AB CMVDD HIOVDD pins, populate this resistor PIOVDD C06 0.uF R80 0 R8 0k R8 0k R8 0k R8 0_np If Kypad i/f from FPIO pins, populate this resistor Silkscreen with Keypad Matrix Order Place these capacitors close KBR0 C to pin of the header. C SW SW SW SW TACT-SPST SW TACT-SPST SW TACT-SPST D D6 D7 A K A K A K MBR00 MBR00 MBR00 KBR SW6 SW7 SW8 SW TACT-SPST SW TACT-SPST SW TACT-SPST D8 D9 D0 A K A K A K B B,,, M/R# AB[0:0] AB0 AB9 R8 0 R86 0 R87 0 KBR MBR00 MBR00 MBR00 AB6 R88 0 SW9 SW0 SW AB R90 0 SW TACT-SPST SW TACT-SPST SW TACT-SPST AB R89 0 D D D, FPIO[:0] FPIO FPIO6 FPIO0 FPIO FPIO FPIO R9 0_np R9 0_np R9 0_np R9 0_np R9 0_np R96 0_np KBR0 KBR KBR KBC0 KBC KBC KBC0 KBC KBC A K MBR00 A K MBR00 A K MBR00 Place these resistors as close to the A SD as A possible. Title Camera i/f, Keypad Size Document Number Rev B <Doc>.0 Thursday, May, 008 Date: Sheet of Figure 6-: SUP00C00 Schematics ( of ) SUP00C00 Evaluation Board User Manual (Rev.) EPSON

34 Chapter 7 Board Layout Chapter 7 Board Layout Figure 7-: SUP00C00 Board Layout - Top View EPSON SUP00C00 Evaluation Board User Manual (Rev.)

35 Chapter 7 Board Layout Figure 7-: SUP00C00 Board Layout - Bottom View SUP00C00 Evaluation Board User Manual (Rev.) EPSON

36 Chapter 8 References Chapter 8 References 8. Documents Epson Research and Development, Inc., SD Hardware Functional Specification, document number X8A-A-00-xx. 8. Document Sources Epson Research and Development Website: 6 EPSON SUP00C00 Evaluation Board User Manual (Rev.)

37 Chapter 8 References Change Record X8A-G-00-0 Revision. - Issued: September 9, 009 section.8 Keypad Interface - add note The keyboard is non-operational with the buttons SW-SW, mounted as they are on the board... to start of section X8A-G-00-0 Revision.0 - Issued: January 0, 009 Release as Revision.0 section.. CNF[7:] - correct typo in table change R0 to R07 chapter 6 Schematic Diagrams - replace figure 6- X8A-G Revision Issued: June, 008 globally add missing Figures globally add missing resistor numbers chapter Features -in second bullet change 6MB to MB and MB to 6MB respectively chapter Parts List - add parts list data chapter 6 Schematic Diagrams - update all schematic diagrams chapter 7 Board Layout - add figures X8A-G Revision Issued: April, 008 section, changed package from QFP to PBGA section, changed Headers for connection to cameras to Header for connection to cameras section, removed On-board video decoder allowing direct connection of an analog camera section, changed on-board keypad from x to x section.., changed the SDRAM size from 6Mbit to 8Mbit section.7., removed Analog Camera and Video Decoder section section.8, changed x keypad to x keypad and updated keypad diagram section 6, updated schematic diagrams X8A-G Revision Issued: February, 008 initial draft of the user manual minor edits and formatting SUP00C00 Evaluation Board User Manual (Rev.) EPSON 7

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