FM486. PMC daughter card specifications

Transcription

1 PMC daughter card specifications for FM486 Unit / Module Name: PMC daughter card specifications Unit / Module Number: FM486 Document Issue: 1.2 FM486 PMC daughter card specifications 4DSP Inc, 955 S Virginia Street, Suite 214, Reno, NV 89502, USA 4DSP bv, Crown Business Centre, Leidse Schouw 2, 2408 AE Alphen a/d Rijn, Netherlands This document is the property of 4DSP and may not be copied nor communicated to a third party without the written permission of 4DSP. 4DSP 2008 April

2 Revision History Date Revision Version First release Corrected: Part number for the SAMTEC connector Minor corrections 1.2 April

3 Table of contents Table of contents Related Documents Dimensions and connectors placement Power connector Data connector...6 April

4 1 Related Documents IEEE Std : IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC). ANSI/VITA : PCI-X for PMC and Processor PMC. ANSI/VITA : Conduction Cooled PMC. ANSI/VITA : XMC Switched Mezzanine Card Auxiliary Standard. IEEE Std : IEEE Standard for a Common Mezzanine Card (CMC) Family. Xilinx Virtex-5 user guides 2 Dimensions and connectors placement Figure 1 : Daughter card dimensions and PCB side 1 connector placement The power and data connectors are placed on side 1 of the PCB. The components height must not exceed 5mm on side 1 of the PCB. For a PCB thickness of 2mm, the components height must not exceed 3mm on side 2 of the PCB. April

5 3 Power connector The PMC daughter card on is powered via a 7- connector of type BKT (Samtec BKT F-V). Each can carry up to 1.5A. The power connector s assignment is as follows. Pin # Signal Signal Pin # V +3.3V V GND V GND V Table 1: Power connector assignment April

6 4 Data connector The daughter card interfaces to the PMC via a 180- connector (QSH F-D-A). The footprint of the 180- connector looks like: Figure 2: Pinout for the QSH connector The data connector assignment is given in the table below. All signals are shown as single ended signals, but they can be also used as LVDS pairs or for any standard that does not breach the electrical rules of the Xilinx Virtex-5 I/O pads. April

7 Signal Name FPGA FPGA Signal name 1 FP_P0 R6 P7 FP_P1 2 3 FP_N0 T6 P6 FP_N1 4 5 FP_X0 U10 T11 FP_X1 6 7 FP_P2 (2) T8 N5 FP_P3 8 9 FP_N2 (2) U7 P5 FP_N FP_X2 T10 T9 FP_X FP_P4 N8 M6 FP_P FP_N4 N7 M5 FP_N FP_X4 R11 R8 FP_X FP_P6 M7 K7 FP_P FP_N6 L6 K6 FP_N FP_X6 R7 L4 FP_X FP_P8 H7 G6 FP_P FP_N8 J7 G7 FP_N FP_X8 D11 L16 FP_X FP_P10 (2) J6 H5 FP_P FP_N10 (2) J5 G5 FP_N FP_X10 K16 L15 FP_X FP_P12 F5 E6 FP_P FP_N12 F6 E7 FP_N FP_X12 L14 K14 FP_X FP_P14 N10 M10 FP_P FP_N14 N9 L9 FP_N FP_X14 K13 K12 FP_X FP_P16 (2) K8 J14 FP_P17 (1) FP_N16 (2) K9 H13 FP_N17 (1) FP_X16 J15 J12 FP_X FP_P18 (1) H14 K11 FP_P FP_N18 (1) H15 J11 FP_N FP_X18 H12 F14 FP_X19 60 Table 2 : Front Panel IO daughter card assignment Bank A (1) Connected to a global clock on the FPGA. (2) Connected to a regional clock on the FPGA. April

8 Signal Name FPGA FPGA Signal name 61 FP_P20 G11 H10 FP_P FP_N20 G12 H9 FP_N FP_X20 F15 E14 FP_X FP_P22 G8 F13 FP_P FP_N22 H8 G13 FP_N FP_X22 D14 F16 FP_X FP_P24 (2) J10 F10 FP_P FP_N24 (2) J9 G10 FP_N FP_X24 G17 J16 FP_X FP_P26 F9 E12 FP_P FP_N26 F8 E13 FP_N FP_X26 L19 C19 FP_X FP_P28 F11 E9 FP_P FP_N28 E11 E8 FP_N FP_X28 F18 M8 FP_X FP_P30 B13 D12 FP_P FP_N30 C13 C12 FP_N FP_X30 E19 G20 FP_X FP_P32 A13 A15 FP_P FP_N32 B12 A14 FP_N FP_X32 F20 L20 FP_X FP_P34 C14 E17 FP_P35 (2) FP_N34 C15 E16 FP_N35 (2) FP_X34 L21 K21 FP_X FP_P36 (2) H17 H18 FP_N36 (2) V/2.5V/1.8V Vbatt (3) FP_X36 G22 J22 FP_X V/2.5V/1.8V 0.9V V/2.5V/1.8V 3.3V/2.5V/1.8V FP_X38 K22 G23 FP_X Table 3: Front Panel IO daughter card assignment Bank B (1) Connected to a global clock on the FPGA. (2) Connected to a regional clock on the FPGA. (3) Vbatt is connected to both Virtex-5 devices Vbatt. April

9 Signal Name FPGA FPGA Signal name 121 FP_P37 B16 B17 FP_P FP_N37 B15 A16 FP_N FP_X40 H23 K23 FP_X FP_P39 C17 D16 FP_P FP_N39 D17 D15 FP_N FP_X42 E22 E23 FP_X FP_P41 D21 E21 FP_P FP_N41 D22 D20 FP_N FP_X44 F23 D24 FP_X FP_P43 F21 C20 FP_P FP_N43 G21 B20 FP_N FP_X46 E24 F24 FP_X FP_P45 (1) H19 B21 FP_P FP_N45 (1) H20 A21 FP_N FP_X48 A29 B25 FP_X FP_P47 C22 A23 FP_P FP_N47 B22 A24 FP_N FP_X50 C25 C18 FP_X FP_P49 C23 C24 FP_P FP_N49 B23 D25 FP_N FP_X52 D29 A30 FP_X FP_P51 D26 B27 FP_P FP_N51 C27 A26 FP_N FP_X54 B30 C30 FP_X FP_P53 (2) B26 C28 FP_P FP_N53 (2) A25 D27 FP_N FP_X56 D30 A31 FP_X FP_P55 (1) J20 A19 FP_P FP_N55 (1) J21 A20 FP_N FP_X58 B31 D31 FP_X Table 4 : Front Panel IO daughter card assignment Bank C (1) Connected to a global clock on the FPGA. (2) Connected to a regional clock on the FPGA. April