Virtex-6 FPGA ML605 Evaluation Kit FAQ June 24, 2009
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1 Virtex-6 FPGA ML605 Evaluation Kit FAQ June 24, 2009 Getting Started Q: Where can I purchase a kit? A: Once the order entry is open, you can purchase your ML605 kit online at: or contact your local Xilinx Distributor or Representative at: Q: When will I get my kit? A: The lead time will initially be 12 weeks after opening the order entry. It will be reduced to 4 weeks by Q409 General Kit Questions: Q: What is included in the kit? A: The ML605 kit is shipped with: ROHS compliant ML605 Base Board including the XC6VLX240T-1FFG1156 FPGA FPGA Design Software A full-seat of Xilinx ISE Design Suite: Logic Edition Device- Locked to Virtex-6 LX240T FPGA. Targeted Reference Designs o PCI Express Gen2 (x8) o PCI Express Gen 1 (x8) o Base Reference Design o DDR3 Memory Interface o IBERT o Multiboot Getting Started Demonstration Documentation o Hardware Setup Guide o Getting Started Guide o Hardware User Guide o Reference Design User Guide o Board Design Files - Schematics/Gerbers/BOM Cables & Power Supply o 12V Universal Power Supply o Two USB Cables o One Ethernet Cable o DVI To VGA Adapter ML605 Board Questions:
2 Q: What silicon version of the Virtex-6 LX240T FPGA is currently installed on the ML605 boards? Production or ES? A: The current FPGA version is ES Q: What speed grade Virtex-6 LX240T is on the board? A: The speed grade is -1 Q: Can I upgrade to a larger or faster device with the same footprint? A: Yes, you can but to do so voids the Xilinx warranty and support for the board will not be provided Q: What is the maximum size of the on-board DDR-III SO-DIMM? A: Up to 2GB Q: The ML605 board is shipped with a 512 MB SO-DIMM made by Micron, can I use SO- DIMMs from other vendors? A: Yes, you can use any JEDEC compliant SO-DIMMs Q: What are the configuration options for the ML605 board?? A: The following configuration methods are available: SystemACE (CompactFlash) Platform Flash Direct (through the on-board configuration circuit) Q: Can the ML605 be plugged into a Motherboard? A: Yes, this is a PCI Express board with edge connector and designed to be used either in PCIe or stand alone mode. For PCIe Gen 2 operation, the PC motherboard should be Gen 2 compliant Q: Is the ML605 powered by PC motherboard (through on board PCIe slots)? A: No, the PCIe slot provides only 12V/2.2A supply which is insufficient for providing the required power to the board. In some cases the overall board s power consumption may exceed 26W and an external supply with higher current is required. Q: The ML605 is an 8-lane PCIe end-point card. How can use the board in x4 or x1 configuration? A: The below jumper setting shows different configurations: Q: My PC s power supply has smaller power connectors that can mate with the on-board J60 connector. Can I use this connector when using the board in PCIe Mode? A: NO, you should ONLY use the 4-pin ATX connector when board is plugged into a PC motherboard Q: Is PCIe Root supported by the ML605 board?
3 A: Yes, but only through an FCM daughter card Q: Does the Ethernet port on the ML605 support the SGMII interface? A: Yes. This feature is sported by one GTX port. Q: The on-board Marvell PHY is also available in smaller packages. Why Xilinx has used the largest package size? A: The larger package size provides easy probing for debugging purpose. Q: Do I need an IP core in order to control the DVI port? A: No, a DVI controller chip is available on the board Q: Do I need an IP core in order to control the USB ports? A: No, a USB controller chip is available on the board Q: Does the ML650 board have a UART port so I can access the EDK IP cores? A: The board is supported by a USB-to-UART bridge chip which has USB connector on one side and UART interface on the other side. Serial programs such as Hyper Terminal supporting USB UART can have serial access to EDK IP cores. Q: How fast can I operate the SFP? A: Up to 4 GB Q: Is the board shipped with an SFP module? A: No, the plug-in module should be purchase separately. Q: Can I install a low pin count (LPC) FMC card into a high pin count (HPC) FMC socket? A: Yes, the name and location of the active signals on the LPC are as same as the HPC Q: I already have an FMC Vita57 compliant daughter card that was not originally designed to be used with the ML605 board. Can I expect this daughter card to work with the ML605 board? A: Yes, this is the most important feature of the FMC. Your card can be plugged into the ML605 board as well as other boards with the same connector and spec compliance. The card must be capable of supporting 2.5V I/Os. Q: Am I limited to the fixed voltages on the FMC card or other voltages can also be provided? A: The V_adjust feature enables availability of other voltage options (via jumper setting) Q: How can I obtain a copy of the Vita57 specification? A: The specification is available for purchase at Q: How many selectios are available on the FMC connectors? A: HPC (High Pin Count): 160 and LPC (Low Pin Count): 68 Q: How many RocketIOs are available on the FMC connectors? A: HPC: 8 and LPC: 1 Q: Can I modify the power output of the on-chip regulators? A: Yes, the ML605 is populated with a UCD9240 PMBus Controller device which can easily adjust the output voltage of the on-board TI regulators. Additional information is available at
4 Q: The board is shipped with a Device-Locked ISE Software. Can I use the software for other Xilinx devices? A: No, the software provides access to the LX240 Device only Q: What are the board s dimensions? A: 10.5 x 5.0 (26.7 cm x 12.7 cm) Q: Does Xilinx provide all the board s design files? A: Yes, these files are available at product page Q: Can I use and modify the PCB design files for my own design? A: Yes you can but please read the disclaimer posted on the board s user manual Q: What is your return policy for boards and software? A: To return a board or cable purchased through normal distribution channels, contact the authorized distributor who originally sold you the product. For more information please visit the following site: Q: What is the warranty period for Xilinx development boards? A: It is 90 days. For more information please visit the following site: Software Related Questions Q: What is ISE Design Suite Device-Locked? A: This option has all features of the full version but provides access only to the LX240T device Q: How do I register and install my software? A: When you order the Virtex-6 FPGA ML605 Evaluation kit, you will be sent an with download instruction. If you log in with the address that was included in your purchase order, then you will already have an account created for you. If not, then you will need to register a new account. This evaluation kit comes with entitlement to a seat of the ISE Design Suite software and all associated updates for a one-year period, or as specified in your purchase order. Please visit the Xilinx software registration and entitlement site: Q: What software do I need to run these reference designs and where do I get it? A: You need ISE Logic Edition Q: What other software would be helpful? Why? A: While ISE will support all the features of the ML605 board, there are some additional software tools that may be helpful. These are found in the ISE Logic, Embedded, DSP or System Editions. For more information see: ChipScope Pro - an FPGA debug and verification tool. Using the ChipScope Core Generator or Core Inserter, you put ChipScope-specific logic into your design, called a ChipScope core.
5 Then, you can connect to ChipScope cores later using the ChipScope Analyzer software to debug or validate your design. The AccelDSP Synthesis Tool - a product that allows you to transform a MATLAB floating-point design into a hardware module that can be implemented in a Xilinx FPGA. The AccelDSP Synthesis Tool features an easy-to-use Graphical User Interface that controls an integrated environment with other design tools such as MATLAB, Xilinx ISE tools, and other industry-standard HDL simulators and logic synthesizers. System Generator - a DSP design tool from Xilinx that enables the use of The Mathworks model-based design environment Simulink for FPGA design. Designs are captured in the DSP friendly Simulink modeling environment using a Xilinx-specific block set. All of the downstream FPGA implementation steps including synthesis and place-and-route are automatically performed to generate an FPGA programming file. PlanAhead a design and analysis software product used to design large FPGA devices. The core technology includes a hierarchical floorplanning tool that can partition the physical design into smaller, more manageable pieces, thus reducing the time to understand, design, verify, and implement the FGPA. Getting More Information Q: Where do I get more information? A: Please check back to the ML605 product page found
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