July 2004 Connectivity Solutions SCPS087

Transcription

1 Data Manual July 2004 Connectivity Solutions SCPS087

2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2004, Texas Instruments Incorporated

3 Contents Section Title Page 1 Introduction Controller Functional Description PCI7515 Controller Multifunctional Terminals PCI Bus Power Management Power Switch Interface Features Related Documents Trademarks Terms and Definitions Ordering Information Terminal Descriptions Feature/Protocol Descriptions Power Supply Sequencing I/O Characteristics Clamping Voltages Peripheral Component Interconnect (PCI) Interface PCI Bus Master Device Resets PCI Bus Lock (LOCK) Serial EEPROM I 2 C Bus Function 0 (CardBus) Subsystem Identification Function 2 (OHCI 1394) Subsystem Identification Function 5 (Smart Card) Subsystem Identification PC Card Applications PC Card Insertion/Removal and Recognition Low Voltage CardBus Card Detection Card Detection Power Switch Interface Internal Ring Oscillator Integrated Pullup Resistors for PC Card Interface SPKROUT and CAUDPWM Usage LED Socket Activity Indicators CardBus Socket Registers MHz Clock Requirements Serial EEPROM Interface Serial-Bus Interface Implementation iii

4 Section Title Page Accessing Serial-Bus Devices Through Software Serial-Bus Interface Protocol Serial-Bus EEPROM Application Programmable Interrupt Subsystem PC Card Functional and Card Status Change Interrupts Interrupt Masks and Flags Using Parallel IRQ Interrupts Using Parallel PCI Interrupts Using Serialized IRQSER Interrupts SMI Support in the PCI7515 Controller Power Management Overview Power Management (Function 2) Integrated Low-Dropout Voltage Regulator (LDO-VR) CardBus (Function 0) Clock Run Protocol CardBus PC Card Power Management Bit PC Card Power Management Suspend Mode Requirements for Suspend Mode Ring Indicate PCI Power Management CardBus Power Management (Function 0) OHCI 1394 (Function 2) Power Management Smart Card (Function 5) Power Management CardBus Bridge Power Management ACPI Support Master List of PME Context Bits and Global Reset-Only Bits IEEE 1394 Application Information PHY Port Cable Connection Crystal Selection Bus Reset PC Card Controller Programming Model PCI Configuration Register Map (Function 0) Vendor ID Register Device ID Register Function Command Register Status Register Revision ID Register Class Code Register Cache Line Size Register Latency Timer Register iv

5 Section Title Page 4.10 Header Type Register BIST Register CardBus Socket Registers/ExCA Base Address Register Capability Pointer Register Secondary Status Register PCI Bus Number Register CardBus Bus Number Register Subordinate Bus Number Register CardBus Latency Timer Register CardBus Memory Base Registers 0, CardBus Memory Limit Registers 0, CardBus I/O Base Registers 0, CardBus I/O Limit Registers 0, Interrupt Line Register Interrupt Pin Register Bridge Control Register Subsystem Vendor ID Register Subsystem ID Register PC Card 16-Bit I/F Legacy-Mode Base-Address Register System Control Register General Control Register General-Purpose Event Status Register General-Purpose Event Enable Register General-Purpose Input Register General-Purpose Output Register Multifunction Routing Status Register Retry Status Register Card Control Register Device Control Register Diagnostic Register Capability ID Register Next Item Pointer Register Power Management Capabilities Register Power Management Control/Status Register Power Management Control/Status Bridge Support Extensions Register Power-Management Data Register Serial Bus Data Register Serial Bus Index Register Serial Bus Slave Address Register Serial Bus Control/Status Register v

6 Section Title Page 5 ExCA Compatibility Registers (Function 0) ExCA Identification and Revision Register ExCA Interface Status Register ExCA Power Control Register ExCA Interrupt and General Control Register ExCA Card Status-Change Register ExCA Card Status-Change Interrupt Configuration Register ExCA Address Window Enable Register ExCA I/O Window Control Register ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers ExCA I/O Windows 0 and 1 End-Address High-Byte Registers ExCA Memory Windows 0 4 Start-Address Low-Byte Registers ExCA Memory Windows 0 4 Start-Address High-Byte Registers ExCA Memory Windows 0 4 End-Address Low-Byte Registers ExCA Memory Windows 0 4 End-Address High-Byte Registers ExCA Memory Windows 0 4 Offset-Address Low-Byte Registers ExCA Memory Windows 0 4 Offset-Address High-Byte Registers ExCA Card Detect and General Control Register ExCA Global Control Register ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers ExCA Memory Windows 0 4 Page Registers CardBus Socket Registers (Function 0) Socket Event Register Socket Mask Register Socket Present State Register Socket Force Event Register Socket Control Register Socket Power Management Register OHCI Controller Programming Model Vendor ID Register Device ID Register Command Register Status Register Class Code and Revision ID Register Latency Timer and Class Cache Line Size Register Header Type and BIST Register OHCI Base Address Register TI Extension Base Address Register Subsystem Identification Register vi

7 Section Title Page 7.11 Power Management Capabilities Pointer Register Interrupt Line Register Interrupt Pin Register Minimum Grant and Maximum Latency Register OHCI Control Register Capability ID and Next Item Pointer Registers Power Management Capabilities Register Power Management Control and Status Register Power Management Extension Registers PCI PHY Control Register PCI Miscellaneous Configuration Register Link Enhancement Control Register Subsystem Access Register GPIO Control Register OHCI Registers OHCI Version Register GUID ROM Register Asynchronous Transmit Retries Register CSR Data Register CSR Compare Register CSR Control Register Configuration ROM Header Register Bus Identification Register Bus Options Register GUID High Register GUID Low Register Configuration ROM Mapping Register Posted Write Address Low Register Posted Write Address High Register Vendor ID Register Host Controller Control Register Self-ID Buffer Pointer Register Self-ID Count Register Isochronous Receive Channel Mask High Register Isochronous Receive Channel Mask Low Register Interrupt Event Register Interrupt Mask Register Isochronous Transmit Interrupt Event Register Isochronous Transmit Interrupt Mask Register Isochronous Receive Interrupt Event Register Isochronous Receive Interrupt Mask Register Initial Bandwidth Available Register vii

8 Section Title Page 8.28 Initial Channels Available High Register Initial Channels Available Low Register Fairness Control Register Link Control Register Node Identification Register PHY Layer Control Register Isochronous Cycle Timer Register Asynchronous Request Filter High Register Asynchronous Request Filter Low Register Physical Request Filter High Register Physical Request Filter Low Register Physical Upper Bound Register (Optional Register) Asynchronous Context Control Register Asynchronous Context Command Pointer Register Isochronous Transmit Context Control Register Isochronous Transmit Context Command Pointer Register Isochronous Receive Context Control Register Isochronous Receive Context Command Pointer Register Isochronous Receive Context Match Register TI Extension Registers DV and MPEG2 Timestamp Enhancements Isochronous Receive Digital Video Enhancements Isochronous Receive Digital Video Enhancements Register Link Enhancement Register Timestamp Offset Register PHY Register Configuration Base Registers Port Status Register Vendor Identification Register Vendor-Dependent Register Power-Class Programming Smart Card Controller Programming Model Vendor ID Register Device ID Register Command Register Status Register Class Code and Revision ID Register Latency Timer and Class Cache Line Size Register Header Type and BIST Register Smart Card Base Address Register Subsystem Vendor Identification Register Subsystem Identification Register viii

9 Section Title Page Capabilities Pointer Register Interrupt Line Register Interrupt Pin Register Minimum Grant Register Maximum Latency Register Capability ID and Next Item Pointer Registers Power Management Capabilities Register Power Management Control and Status Register Power Management Bridge Support Extension Register Power Management Data Register General Control Register Subsystem Access Register Smart Card Configuration 1 Register Electrical Characteristics Absolute Maximum Ratings Over Operating Temperature Ranges Recommended Operating Conditions Electrical Characteristics Over Recommended Operating Conditions Electrical Characteristics Over Recommended Ranges of Operating Conditions Device Driver Receiver PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature Switching Characteristics for PHY Port Interface Operating, Timing, and Switching Characteristics of XI PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature Smart Card Timing Specifications Over Recommended Operating Conditions Reset Timing Mechanical Information ix

10 List of Illustrations Figure Title Page 2 1 PCI7515 GHK/ZHK-Package Terminal Diagram PCI7515 System Block Diagram State Bidirectional Buffer Serial ROM Application SPKROUT Connection to Speaker Driver Sample LED Circuit Serial-Bus Start/Stop Conditions and Bit Transfers Serial-Bus Protocol Acknowledge Serial-Bus Protocol Byte Write Serial-Bus Protocol Byte Read EEPROM Interface Doubleword Data Collection IRQ Implementation System Diagram Implementing CardBus Device Class Power Management Signal Diagram of Suspend Function RI_OUT Functional Diagram Block Diagram of a Status/Enable Cell TP Cable Connections Typical Compliant DC Isolated Outer Shield Termination Non-DC Isolated Outer Shield Termination Load Capacitance for the PCI7515 PHY Recommended Crystal and Capacitor Layout ExCA Register Access Through I/O ExCA Register Access Through Memory Accessing CardBus Socket Registers Through PCI Memory Test Load Diagram Cold Reset Sequence Warm Reset Sequence Contact Deactivation Sequence Reset Timing Diagram x

11 List of Tables Table Title Page 1 1 Terms and Definitions Signal s by GHK Terminal Number CardBus PC Card Signal s Sorted Alphabetically Bit PC Card Signal s Sorted Alphabetically Power Supply Terminals PC Card Power Switch Terminals PCI System Terminals PCI Address and Data Terminals PCI Interface Control Terminals Multifunction and Miscellaneous Terminals Bit PC Card Address and Data Terminals Bit PC Card Interface Control Terminals CardBus PC Card Interface System Terminals CardBus PC Card Address and Data Terminals CardBus PC Card Interface Control Terminals IEEE 1394 Physical Layer Terminals Smart Card Terminals PCI Bus Support PC Card Card Detect and Voltage Sense Connections TPS2228 Control Logic xvpp/vcore TPS2228 Control Logic xvcc TPS2226 Control Logic xvpp TPS2226 Control Logic xvcc CardBus Socket Registers PCI7515 Registers Used to Program Serial-Bus Devices EEPROM Loading Map Interrupt Mask and Flag Registers PC Card Interrupt Events and Description Interrupt Pin Register Cross Reference SMI Control Requirements for Internal/External 1.5-V Core Power Supply Power-Management Registers Function 2 Power-Management Registers Function 5 Power-Management Registers Bit Field Access Tag Descriptions Function 0 PCI Configuration Register Map Command Register Description xi

12 Table Title Page 4 4 Status Register Description Secondary Status Register Description Interrupt Pin Register Cross Reference Bridge Control Register Description System Control Register Description General Control Register Description General-Purpose Event Status Register Description General-Purpose Event Enable Register Description General-Purpose Input Register Description General-Purpose Output Register Description Multifunction Routing Status Register Description Retry Status Register Description Card Control Register Description Device Control Register Description Diagnostic Register Description Power Management Capabilities Register Description Power Management Control/Status Register Description Power Management Control/Status Bridge Support Extensions Register Description Serial Bus Data Register Description Serial Bus Index Register Description Serial Bus Slave Address Register Description Serial Bus Control/Status Register Description ExCA Registers and Offsets ExCA Identification and Revision Register Description ExCA Interface Status Register Description ExCA Power Control Register Description 82365SL Support ExCA Power Control Register Description 82365SL-DF Support ExCA Interrupt and General Control Register Description ExCA Card Status-Change Register Description ExCA Card Status-Change Interrupt Configuration Register Description ExCA Address Window Enable Register Description ExCA I/O Window Control Register Description ExCA Memory Windows 0 4 Start-Address High-Byte Registers Description ExCA Memory Windows 0 4 End-Address High-Byte Registers Description ExCA Memory Windows 0 4 Offset-Address High-Byte Registers Description ExCA Card Detect and General Control Register Description ExCA Global Control Register Description CardBus Socket Registers Socket Event Register Description xii

13 Table Title Page 6 3 Socket Mask Register Description Socket Present State Register Description Socket Force Event Register Description Socket Control Register Description Socket Power Management Register Description Function 2 Configuration Register Map Command Register Description Status Register Description Class Code and Revision ID Register Description Latency Timer and Class Cache Line Size Register Description Header Type and BIST Register Description OHCI Base Address Register Description TI Base Address Register Description Subsystem Identification Register Description Interrupt Line Register Description PCI Interrupt Pin Register Read-Only INTPIN Per Function Minimum Grant and Maximum Latency Register Description OHCI Control Register Description Capability ID and Next Item Pointer Registers Description Power Management Capabilities Register Description Power Management Control and Status Register Description Power Management Extension Registers Description PCI PHY Control Register Description PCI Miscellaneous Configuration Register Description Link Enhancement Control Register Description Subsystem Access Register Description General-Purpose Input/Output Control Register Description OHCI Register Map OHCI Version Register Description GUID ROM Register Description Asynchronous Transmit Retries Register Description CSR Control Register Description Configuration ROM Header Register Description Bus Options Register Description Configuration ROM Mapping Register Description Posted Write Address Low Register Description Posted Write Address High Register Description Host Controller Control Register Description Self-ID Count Register Description Isochronous Receive Channel Mask High Register Description Isochronous Receive Channel Mask Low Register Description Interrupt Event Register Description Interrupt Mask Register Description xiii

14 Table Title Page 8 17 Isochronous Transmit Interrupt Event Register Description Isochronous Receive Interrupt Event Register Description Initial Bandwidth Available Register Description Initial Channels Available High Register Description Initial Channels Available Low Register Description Fairness Control Register Description Link Control Register Description Node Identification Register Description PHY Control Register Description Isochronous Cycle Timer Register Description Asynchronous Request Filter High Register Description Asynchronous Request Filter Low Register Description Physical Request Filter High Register Description Physical Request Filter Low Register Description Asynchronous Context Control Register Description Asynchronous Context Command Pointer Register Description Isochronous Transmit Context Control Register Description Isochronous Receive Context Control Register Description Isochronous Receive Context Match Register Description TI Extension Register Map Isochronous Receive Digital Video Enhancements Register Description Link Enhancement Register Description Timestamp Offset Register Description Base Register Configuration Base Register Field Descriptions Page 0 (Port Status) Register Configuration Page 0 (Port Status) Register Field Descriptions Page 1 (Vendor ID) Register Configuration Page 1 (Vendor ID) Register Field Descriptions Page 7 (Vendor-Dependent) Register Configuration Page 7 (Vendor-Dependent) Register Field Descriptions Power Class Descriptions Function 5 Configuration Register Map Command Register Description Status Register Description Class Code and Revision ID Register Description Latency Timer and Class Cache Line Size Register Description Header Type and BIST Register Description Smart Card Base Address Register Description PCI Interrupt Pin Register Minimum Grant Register Description Maximum Latency Register Description xiv

15 Table Title Page Capability ID and Next Item Pointer Registers Description Power Management Capabilities Register Description Power Management Control and Status Register Description General Control Register Subsystem Access Register Description Smart Card Configuration 1 Register Description xv

16 xvi

17 1 Introduction The Texas Instruments PCI7515 controller is an integrated single-socket PC Card controller, IEEE 1394 open HCI host controller and PHY, and Smart Card controller. This high-performance integrated solution provides the latest in PC Card, IEEE 1394, and Smart Card technology. 1.1 Controller Functional Description PCI7515 Controller The PCI7515 controller is a three-function PCI controller compliant with PCI Local Bus Specification, Revision 2.3. Function 0 provides an independent PC Card socket controllers compliant with the PC Card Standard (Release 8.1). The PCI7515 controller provides features that make it the best choice for bridging between the PCI bus and PC Cards, and supports 16-bit, CardBus, or USB custom card interface PC Cards, powered at 5 V or 3.3 V, as required. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI7515 controller is register compatible with the Intel 82365SL-DF ExCA controller. The PCI7515 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI7515 controller can be programmed to accept posted writes to improve bus utilization. Function 2 of the PCI7515 controller is compatible with IEEE Std 1394a-2000 and the latest 1394 Open Host Controller Interface Specification. The chip provides the IEEE1394 link and 1-port PHY function and is compatible with data rates of 100, 200, and 400 Mbits per second. Deep FIFOs are provided to buffer 1394 data and accommodate large host bus latencies. The PCI7515 controller provides physical write posting and a highly tuned physical data path for SBP-2 performance. Function 5 of the PCI7515 controller is a PCI-based Smart Card controller used for communication with Smart Cards inserted in PC Card adapters or the dedicated Smart Card socket. Utilizing Smart Card technology from Gemplus, this function provides compatibility with many different types of Smart Cards Multifunctional Terminals Various implementation-specific functions and general-purpose inputs and outputs are provided through eight multifunction terminals. These terminals present a system with options in PCI LOCK, serial and parallel interrupts, PC Card activity indicator LEDs, and other platform-specific signals. PCI complaint general-purpose events may be programmed and controlled through the multifunction terminals, and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs PCI Bus Power Management The PCI7515 controller is compliant with the latest PCI Bus Power Management Specification, and provides several low-power modes, which enable the host power system to further reduce power consumption Power Switch Interface The PCI7515 controller also has a three-pin serial interface compatible with the Texas Instruments TPS2228 (default), TPS2226, TPS2224, TPS2223A, and TPS2220 power switches. All five power switches provide power to the CardBus socket on the PCI7515 controller. The power to the dedicated Smart Card socket is controlled through a separate power control pin that can be used to control an external 5-V power switch or it may be configured to source power through BVPP of a dual socket PCMCIA power switch. 1 1

18 1.2 Features The PCI7515 controller supports the following features: PC Card Standard 8.1 compliant PCI Bus Power Management Interface Specification 1.1 compliant Advanced Configuration and Power Interface (ACPI) Specification 2.0 compliant PCI Local Bus Specification Revision 2.3 compliant PC 98/99 and PC2001 compliant Windows Logo Program 2.0 compliant PCI Bus Interface Specification for PCI-to-CardBus Bridges 1.5-V core logic and 3.3-V I/O cells with internal voltage regulator to generate 1.5-V core V CC Universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Supports PC Card or CardBus with hot insertion and removal Supports 132-MBps burst transfers to maximize data throughput on both the PCI bus and the CardBus Supports serialized IRQ with PCI interrupts Programmable multifunction terminals Many interrupt modes supported Serial ROM interface for loading subsystem ID and subsystem vendor ID ExCA-compatible registers are mapped in memory or I/O space Intel 82365SL-DF register compatible Supports ring indicate, SUSPEND, and PCI CLKRUN protocols and PCI bus Lock (LOCK) Provides VGA/palette memory and I/O, and subtractive decoding options, LED activity terminals Fully interoperable with FireWire and i.link implementations of IEEE Std 1394 Compliant with Intel Mobile Power Guideline 2000 Fully compliant with provisions of IEEE Std for a high-performance serial bus and IEEE Std 1394a-2000 Fully compliant with 1394 Open Host Controller Interface Specification 1.1 Full IEEE Std 1394a-2000 support includes: connection debounce, arbitrated short reset, multispeed concatenation, arbitration acceleration, fly-by concatenation, and port disable/suspend/resume Power-down features to conserve energy in battery-powered applications include: automatic device power down during suspend, PCI power management for link-layer, and inactive ports powered down, ultralow-power sleep mode A IEEE Std 1394a-2000 fully compliant cable port at 100M bits/s, 200M bits/s, and 400M bits/s Cable port monitors line conditions for active connection to remote node Cable power presence monitoring Separate cable bias (TPBIAS) for the port Physical write posting of up to three outstanding transactions PCI burst transfers and deep FIFOs to tolerate large host latency 1 2

19 External cycle timer control for customized synchronization Extended resume signaling for compatibility with legacy DV components PHY-Link logic performs system initialization and arbitration functions PHY-Link encode and decode functions included for data-strobe bit level encoding PHY-Link incoming data resynchronized to local clock Low-cost MHz crystal provides transmit and receive data at 100M bits/s, 200M bits/s, and 400M bits/s Node power class information signaling for system power management Register bits give software control of contender bit, power class bits, link active control bit, and IEEE Std 1394a-2000 features Isochronous receive dual-buffer mode Out-of-order pipelining for asynchronous transmit requests Register access fail interrupt when the PHY SCLK is not active PCI power-management D0, D1, D2, and D3 power states Initial bandwidth available and initial channels available registers PME support per 1394 Open Host Controller Interface Specification Advanced submicron, low-power CMOS technology 1.3 Related Documents Advanced Configuration and Power Interface (ACPI) Specification (Revision 2.0) 1394 Open Host Controller Interface Specification (Release 1.1) IEEE Standard for a High Performance Serial Bus (IEEE Std ) IEEE Standard for a High Performance Serial Bus Amendment 1 (IEEE Std 1394a-2000) PC Card Standard (Release 8.1) PCI Bus Power Management Interface Specification (Revision 1.1) Serial Bus Protocol 2 (SBP-2) Serialized IRQ Support for PCI Systems PCI Mobile Design Guide PCI Bus Power Management Interface Specification for PCI to CardBus Bridges PCI14xx Implementation Guide for D3 Wake-Up PCI to PCMCIA CardBus Bridge Register Description Texas Instruments TPS2224 and TPS2226 product data sheet, SLVS317 Texas Instruments TPS2223A product data sheet, SLVS428 Texas Instruments TPS2228 product data sheet, SLVS419 PCI Local Bus Specification (Revision 2.3) PCMCIA Proposal (262) ISO Standards for Identification Cards ISO/IEC

20 1.4 Trademarks Intel is a trademark of Intel Corporation. TI and MicroStar BGA are trademarks of Texas Instruments. FireWire is a trademark of Apple Computer, Inc. i.link is a trademark of Sony Corporation of America. Other trademarks are the property of their respective owners. 1.5 Terms and Definitions Terms and definitions used in this document are given in Table 1 1. Table 1 1. Terms and Definitions TERM DEFINITIONS AT AT (advanced technology, as in PC AT) attachment interface CIS Card information structure. Tuple list defined by the PC Card standard to communicate card information to the host computer CSR Control and status register ISO/IEC 7816 The Smart Card standard PCMCIA Personal Computer Memory Card International Association. Standards body that governs the PC Card standards RSVD Reserved for future use Smart Card The name applied to ID cards containing integrated circuits, as defined by ISO/IEC TI Smart Card driver 1.6 Ordering Information A qualified software component provided by Texas Instruments that loads when an UltraMedia-based Smart Card adapter is inserted into a PC Card slot. This driver is logically attached to a CIS provided by the PCI7515 when the adapter and media are both inserted. ORDERING NUMBER NAME VOLTAGE PACKAGE PCI7515 Single Socket CardBus Controller with Integrated 1394a-2000 OHCI One-Port PHY/Link-Layer Controller with Dedicated Smart Card Socket 3.3-V, 5-V tolerant I/Os 257-ball PBGA (GHK or ZHK) 1 4

21 2 Terminal Descriptions The PCI7515 controller is available in the 257-terminal MicroStar BGA package (GHK) or the 257-terminal lead-free (Pb, atomic number 82) MicroStar BGA package (ZHK). Figure 2 1 is a pin diagram of the PCI7515 package. W V NC NC AD16 TRDY SERR AD15 VCCP AD11 C/BE0 AD4 PC2 (TEST3) TPB0N TPA0N NC NC NC NC NC NC NC NC IRDY STOP C/BE1 AD12 AD10 AD7 AD3 PC1 (TEST2) TPB0P TPA0P NC NC NC NC NC U PC0 NC NC NC NC C/BE2 DEVSEL PAR AD13 AD9 AD6 AD2 AGND AGND AVDD NC NC (TEST1) VSPLL VDPLL _33 T AD18 AD17 NC NC R0 R1 R AD22 AD21 AD19 FRAME PERR AD14 AD8 AD5 AD0 CPS TPBIAS0 AGND VSPLL XO XI P VCCP C/BE3 AD23 AD20 VCC GND VCC GND VCC AD1 TEST0 AVDD AVDD VDPLL_ 15 PHY_ TEST_ MA CNA A_CAD0 //A_D3 N AD26 AD25 AD24 IDSEL GND NC A_CCD1 //A_CD1 A_CAD2 //A_D11 A_CAD1 //A_D4 A_CAD4 //A_D12 M AD31 AD30 AD29 AD27 AD28 GND A_CAD3 //A_D5 A_CAD6 //A_D13 A_CAD5 //A_D6 A_RSVD //A_D14 L PCLK GNT REQ RI_OUT //PME VCC VCC A_CAD9 //A_A10 A_CC/BE0 //A_CE1 A_CAD8 //A_D15 A_CAD7 //A_D7 K VR_PORT VR_EN PRST GRST GND GND A_CAD12 //A_A11 A_CAD11 //A_OE A_CAD10 //A_CE2 VR_PORT J MFUNC4 MFUNC5 MFUNC6 SUSPEND VCC VCC A_CAD14 //A_A9 A_CAD15 A_CAD13 //A_IOWR //A_IORD VCCA H MFUNC3 MFUNC2 SPKROUT MFUNC1 GND A_CPAR //A_A13 A_CBLOCK //A_A19 A_RSVD //A_A18 A_CC/BE1 //A_A8 A_CAD16 //A_A17 G MFUNC0 SCL SDA SC_PWR _CTRL SC_VCC _5V GND A_CTRDY //A_A22 A_CGNT //A_WE A_CSTOP //A_A20 A_CPERR //A_A14 F CLK_48 SC_OC SC_CD SC_RST A_CAD29 VCC GND NC VCC GND VCC GND VCC //A_D1 A_CAD17 //A_A24 A_CIRDY //A_A15 A_CCLK //A_A16 A_CDEVSEL //A_A21 E SC_DATA SC_CLK SC_FCB NC SC_ GPIO3 NC NC NC A_USB_EN A_CAD28 //A_D8 A_CINT// A_READY (IREQ) A_CC/BE3 //A_REG A_CAD21 //A_A5 A_CAD18 //A_A7 A_CC/BE2 //A_A12 A_CFRAME //A_A23 D SC_RFU NC NC NC NC A_CAD19 //A_A25 C B A NC NC NC NC SC_ SC_ A_CAD31 A_CAD27 A_CSERR A_CAD25 A_CREQ A_CRST GPIO2 GPIO6 NC NC LATCH //A_D10 //A_D0 //A_WAIT //A_A1 //A_INPACK //A_RESET NC NC NC NC NC NC A_CAUDIO SC_ SC_ A_RSVD A_CCD2 A_CAD26 A_CAD23 A_CAD22 A_CVS2 NC NC NC DATA //A_BVD2 GPIO0 GPIO4 //A_D2 //A_CD2 //A_A0 //A_A3 //A_A4 //A_VS2 (SPKR) NC NC NC NC A_CCLKRUN A_CSTSCHG SC SC_ A_CAD30 A_CVS1 A_CAD24 A_CAD20 NC NC NC CLOCK //A_WP //A_BVD1 VCCA GPIO1 GPIO5 //A_D9 (IOIS16) (STSCHG/RI) //A_VS1 //A_A2 //A_A6 NC NC NC NC Figure 2 1. PCI7515 GHK/ZHK-Package Terminal Diagram 2 1

22 Table 2 1 lists the terminal assignments arranged in terminal-number order, with corresponding signal names for both CardBus and 16-bit PC Cards for the PCI7515 GHK package. Table 2 2 and Table 2 3 list the terminal assignments arranged in alphanumerical order by signal name, with corresponding terminal numbers for the GHK package; Table 2 2 is for CardBus signal names and Table 2 3 is for 16-bit PC Card signal names. Terminal E5 on the GHK package is an identification ball used for device orientation. Table 2 1. Signal s by GHK Terminal Number TERMINAL SIGNAL NAME TERMINAL SIGNAL NAME NUMBER CardBus PC Card 16-Bit PC Card NUMBER CardBus PC Card 16-Bit PC Card A02 NC NC C03 NC NC A03 NC NC C04 NC NC A04 SC_GPIO1 SC_GPIO1 C05 SC_GPIO2 SC_GPIO2 A05 SC_GPIO5 SC_GPIO5 C06 SC_GPIO6 SC_GPIO6 A06 NC NC C07 NC NC A07 NC NC C08 NC NC A08 NC NC C09 LATCH LATCH A09 CLOCK CLOCK C10 A_CAD31 A_D10 A10 A_CAD30 A_D9 C11 A_CAD27 A_D0 A11 A_CCLKRUN A_WP(IOIS16) C12 A_CSERR A_WAIT A12 A_CSTSCHG A_BVD1(STSCHG/RI) C13 A_CAD25 A_A1 A13 A_CVS1 A_VS1 C14 A_CREQ A_INPACK A14 A_CAD24 A_A2 C15 A_CRST A_RESET A15 VCCA VCCA C16 NC NC A16 A_CAD20 A_A6 C17 NC NC A17 NC NC C18 NC NC A18 NC NC C19 NC NC B01 NC NC D01 SC_RFU SC_RFU B02 NC NC D02 NC NC B03 NC NC D03 NC NC B04 SC_GPIO0 SC_GPIO0 D17 NC NC B05 SC_GPIO4 SC_GPIO4 D18 NC NC B06 NC NC D19 A_CAD19 A_A25 B07 NC NC E01 SC_DATA SC_DATA B08 NC NC E02 SC_CLK SC_CLK B09 DATA DATA E03 SC_FCB SC_FCB B10 A_RSVD A_D2 E06 SC_GPIO3 SC_GPIO3 B11 A_CCD2 A_CD2 E07 NC NC B12 A_CAUDIO A_BVD2(SPKR) E08 NC NC B13 A_CAD26 A_A0 E09 NC NC B14 A_CAD23 A_A3 E10 A_USB_EN A_USB_EN B15 A_CAD22 A_A4 E11 A_CAD28 A_D8 B16 A_CVS2 A_VS2 E12 A_CINT A_READY(IREQ) B17 NC NC E13 A_CC/BE3 A_REG B18 NC NC E14 A_CAD21 A_A5 B19 NC NC E17 A_CAD18 A_A7 C01 NC NC E18 A_CC/BE2 A_A12 C02 NC NC E19 A_CFRAME A_A23 2 2