December 2004 Connectivity Solutions SCPS071E

Transcription

1 Data Manual December 2004 onnectivity Solutions SPS071E

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3 ontents Section Title Page 1 Introduction Description Features Related Documents Trademarks Document onventions Ordering Information PI1510 Data Manual Document History Terminal Descriptions PI1510 Terminal Assignments Terminal Descriptions Feature/Protocol Descriptions Power Supply Sequencing I/O haracteristics lamping Voltages Peripheral omponent Interconnect (PI) Interface PI GRST Signal PI Bus Lock (LOK) Loading Subsystem Identification P ard Applications P ard Insertion/Removal and Recognition Parallel Power-Switch Interface (TPS2211A) Zoomed Video Support Standardized Zoomed-Video Register Model Zoomed-Video ard Insertion and onfiguration Procedure Internal Ring Oscillator Integrated Pullup Resistors SPKROUT and AUDPWM Usage LED Socket Activity Indicators ardbus Socket Registers Serial-Bus Interface Serial-Bus Interface Implementation Serial-Bus Interface Protocol Serial-Bus EEPROM Application Accessing Serial-Bus Devices Through Software iii

4 Section Title Page 3.7 Programmable Interrupt Subsystem P ard Functional and ard Status hange Interrupts Interrupt Masks and Flags Using Parallel IRQ Interrupts Using Parallel PI Interrupts Using Serialized IRQSER Interrupts SMI Support in the PI1510 ontroller Power Management Overview Integrated Low-Dropout Voltage Regulator (LDO-VR) lock Run Protocol ardbus P ard Power Management Bit P ard Power Management Suspend Mode Requirements for Suspend Mode Ring Indicate PI Power Management ardbus Bridge Power Management API Support Master List of PME ontext Bits and Global Reset-Only Bits P ard ontroller Programming Model PI onfiguration Registers Vendor ID Register Device ID Register ommand Register Status Register Revision ID Register PI lass ode Register ache Line Size Register Latency Timer Register Header Type Register BIST Register ardbus Socket/ExA Base-Address Register apability Pointer Register Secondary Status Register PI Bus Number Register ardbus Bus Number Register Subordinate Bus Number Register ardbus Latency Timer Register Memory Base Registers 0, Memory Limit Registers 0, I/O Base Registers 0, iv

5 Section Title Page 4.22 I/O Limit Registers 0, Interrupt Line Register Interrupt Pin Register Bridge ontrol Register Subsystem Vendor ID Register Subsystem ID Register P ard 16-Bit I/F Legacy-Mode Base Address Register System ontrol Register Multifunction Routing Register Retry Status Register ard ontrol Register Device ontrol Register Diagnostic Register apability ID Register Next-Item Pointer Register Power-Management apabilities Register Power-Management ontrol/status Register Power-Management ontrol/status Register Bridge Support Extensions Power-Management Data Register General-Purpose Event Status Register General-Purpose Event Enable Register General-Purpose Input Register General-Purpose Output Register Serial-Bus Data Register Serial-Bus Index Register Serial-Bus Slave Address Register Serial-Bus ontrol and Status Register ExA ompatibility Registers ExA Identification and Revision Register ExA Interface Status Register ExA Power ontrol Register ExA Interrupt and General ontrol Register ExA ard Status-hange Register ExA ard Status-hange Interrupt onfiguration Register ExA Address Window Enable Register ExA I/O Window ontrol Register ExA I/O Windows 0 and 1 Start-Address Low-Byte Registers ExA I/O Windows 0 and 1 Start-Address High-Byte Registers ExA I/O Windows 0 and 1 End-Address Low-Byte Registers ExA I/O Windows 0 and 1 End-Address High-Byte Registers ExA Memory Windows 0 4 Start-Address Low-Byte Registers v

6 Section Title Page 5.14 ExA Memory Windows 0 4 Start-Address High-Byte Registers ExA Memory Windows 0 4 End-Address Low-Byte Registers ExA Memory Windows 0 4 End-Address High-Byte Registers ExA Memory Windows 0 4 Offset-Address Low-Byte Registers ExA Memory Windows 0 4 Offset-Address High-Byte Registers ExA ard Detect and General ontrol Register ExA Global ontrol Register ExA I/O Windows 0 and 1 Offset-Address Low-Byte Registers ExA I/O Windows 0 and 1 Offset-Address High-Byte Registers ExA Memory Windows 0 4 Page Registers ardbus Socket Registers Socket Event Register Socket Mask Register Socket Present-State Register Socket Force Event Register Socket ontrol Register Socket Power-Management Register Electrical haracteristics Absolute Maximum Ratings Over Operating Temperature Ranges Recommended Operating onditions Electrical haracteristics Over Recommended Operating onditions PI lock/reset Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature PI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature Mechanical Information vi

7 List of Illustrations Figure Title Page 2 1 PI1510 GGU-Package Terminal Diagram PI1510 GVF-Package Terminal Diagram PI1510 PGE-Package Terminal Diagram PI1510 Simplified Block Diagram State Bidirectional Buffer TPS2211A Typical Application Zoomed Video Implementation Using the PI1510 ontroller Zoomed Video Switching Application Sample Application of SPKROUT and AUDPWM Two Sample LED ircuits Serial EEPROM Application Serial-Bus Start/Stop onditions and Bit Transfers Serial-Bus Protocol Acknowledge Serial-Bus Protocol Byte Write Serial-Bus Protocol Byte Read EEPROM Interface Doubleword Data ollection IRQ Implementation Signal Diagram of Suspend Function RI_OUT Functional Diagram Block Diagram of a Status/Enable ell ExA Register Access Through I/O ExA Register Access Through Memory Accessing ardbus Socket Registers Through PI Memory vii

8 List of Tables Table Title Page 2 1 Signal Names Sorted by PGE Terminal Number Signal Names Sorted by GGU Terminal Number Signal Names Sorted by GVF Terminal Number ardbus P ard Signal Names Sorted Alphabetically to Device Terminals Bit P ard Signal Names Sorted Alphabetically to Device Terminals Power Supply Terminals P ard Power Switch Terminals PI System Terminals PI Address and Data Terminals PI Interface ontrol Terminals Multifunction and Miscellaneous Terminals Bit P ard Address and Data Terminals Bit P ard Interface ontrol Terminals ardbus P ard Interface System Terminals ardbus P ard Address and Data Terminals ardbus P ard Interface ontrol Terminals P ard ard-detect and Voltage-Sense onnections Zoomed-Video ard Interrogation Integrated Pullup Resistors ardbus Socket Registers Register- and Bit-Loading Map PI1510 Registers Used to Program Serial-Bus Devices Interrupt Mask and Flag Registers P ard Interrupt Events and Description SMI ontrol Requirements for Internal/External 2.5-V ore Power Supply Power-Management Registers PI onfiguration Registers Bit Field Access Tag Descriptions ommand Register Description Status Register Description Secondary Status Register Description Bridge ontrol Register Description System ontrol Register Description Multifunction Routing Register Description Retry Status Register Description viii

9 Table Title Page 4 10 ard ontrol Register Description Device ontrol Register Description Diagnostic Register Description Power-Management apabilities Register Description Power-Management ontrol/status Register Description Power-Management ontrol/status Register Bridge Support Extensions Description General-Purpose Event Status Register Description General-Purpose Event Enable Register Description General-Purpose Input Register Description General-Purpose Output Register Description Serial-Bus Data Register Description Serial-Bus Index Register Description Serial-Bus Slave Address Register Description Serial-Bus ontrol and Status Register Description ExA Registers and Offsets ExA Identification and Revision Register Description ExA Interface Status Register Description ExA Power ontrol Register Description 82365SL Support ExA Power ontrol Register Description 82365SL-DF Support ExA Interrupt and General ontrol Register Description ExA ard Status-hange Register Description ExA ard Status-hange Interrupt onfiguration Register Description ExA Address Window Enable Register Description ExA I/O Window ontrol Register Description ExA Memory Windows 0 4 Start-Address High-Byte Registers Description ExA Memory Windows 0 4 End-Address High-Byte Registers Description ExA Memory Windows 0 4 Offset-Address High-Byte Registers Description ExA ard Detect and General ontrol Register Description ExA Global ontrol Register Description ardbus Socket Registers Socket Event Register Description Socket Mask Register Description Socket Present-State Register Description Socket Force Event Register Description Socket ontrol Register Description Socket Power-Management Register Description ix

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11 1 Introduction 1.1 Description The Texas Instruments PI1510 device, a 144-terminal or a 209-terminal single-slot ardbus controller designed to meet the PI Bus Power Management Interface Specification for PI to ardbus Bridges, is an ultralow-power high-performance PI-to-ardBus controller that supports a single P card socket compliant with the P ard Standard (rev. 7.2). The controller provides features that make it the best choice for bridging between PI and P ards in both notebook and desktop computers. The P ard Standard retains the 16-bit P ard specification defined in the PI Local Bus Specification and defines the 32-bit P ard, ardbus, capable of full 32-bit data transfers at 33 MHz. The controller supports both 16-bit and ardbus P ards, powered at 5 V or 3.3 V, as required. The controller is compliant with the PI Local Bus Specification, and its PI interface can act as either a PI master device or a PI slave device. The PI bus mastering is initiated during ardbus P ard bridging transactions. The controller is also compliant with PI Bus Power Management Interface Specification (rev. 1.1). All card signals are internally buffered to allow hot insertion and removal without external buffering. The controller is register-compatible with the Intel 82365SL-DF and 82365SL ExA controllers. The controller internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The controller can also be programmed to accept fast posted writes to improve system-bus utilization. Multiple system-interrupt signaling options are provided, including parallel PI, parallel ISA, serialized ISA, and serialized PI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PI1510 controller, such as a socket activity light-emitting diode (LED) outputs, are discussed in detail throughout this document. An advanced complementary metal-oxide semiconductor (MOS) process achieves low system power consumption while operating at PI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. 1.2 Features The controller supports the following features: A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGA ball-grid array (GGU/ZGU) package, or a 209-terminal PBGA (GVF/ZVF) package 2.5-V core logic and 3.3-V I/O with universal PI interfaces compatible with 3.3-V and 5-V PI signaling environments Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5-V power supply Mix-and-match 5-V/3.3-V 16-bit P ards and 3.3-V ardbus ards A single P ard or ardbus slot with hot insertion and removal Parallel interface to TI TPS2211A single-slot P ard power switch Burst transfers to maximize data throughput with ardbus ards Interrupt configurations: parallel PI, serialized PI, parallel ISA, and serialized ISA Serial EEPROM interface for loading subsystem ID, subsystem vendor ID, and other configuration registers Pipelined architecture for greater than 130-Mbps throughput from ardbus-to-pi and from PI-to- ardbus 1 1

12 Up to five general-purpose I/Os Programmable output select for LKRUN Five PI memory windows and two I/O windows available for the 16-bit interface Two I/O windows and two memory windows available to the ardbus socket Exchangeable-card-architecture- (ExA-) compatible registers are mapped in memory and I/O space Intel 82365SL-DF and 82365SL register compatible Ring indicate, SUSPEND, PI LKRUN, and ardbus LKRUN Socket activity LED terminal PI bus lock (LOK) Internal ring oscillator 1.3 Related Documents Advanced onfiguration and Power Interface (API) Specification (revision 1.1) PI Bus Power Management Interface Specification (revision 1.1) PI Bus Power Management Interface Specification for PI to ardbus Bridges (revision 0.6) PI to PMIA ardbus Bridge Register Description (Yenta) (revision 2.1) PI Local Bus Specification (revision 2.2) PI Mobile Design Guide (revision 1.0) P ard Standard (revision 7.2) Serialized IRQ Support for PI Systems (revision 6) 1.4 Trademarks Intel is a trademark of Intel orporation. MicroStar BGA is a trademark of Texas Instruments. Other trademarks are the property of their respective owners. 1.5 Document onventions Throughout this data manual, several conventions are used to convey information. These conventions are listed below: 1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field. 2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field. 3. All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format. 4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b. 5. RSVD indicates that the referenced item is reserved. 6. In Sections 4 through 6, the configuration space for the controller is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries: r read-only access 1 2

13 ru read-only access with updates by the controller internal hardware rw read and write access rcu read access with the option to clear an asserted bit with a write-back of 1b including updates by the controller internal hardware. 1.6 Ordering Information ORDERING NUMBER NAME VOLTAGE PAKAGE PI1510 P ard controller 3.3 V, 5-V tolerant I/Os 144-terminal LQFP 144-ball PBGA (GGU or ZGU) 209-ball PBGA (GVF or ZVF) 1.7 PI1510 Data Manual Document History DATE PAGE NUMBER REVISION 01/ Modified terminal number of AD30 from 143 to 142 for PGE package 01/ Added new subsection to describe GRST during power up 01/ Modified byte-read diagram (Figure 3 12) to better reflect a read transaction to the EEPROM 01/ Modified the description of the power management capabilities register. This register is not a static read-only register. 08/ Added lead-free (Pb, atomic number 82) MicroStar BGA package (ZGU) to ordering information 08/ Added description for ZGU package 08/ Added ZGU mechanical drawing 10/ Added GVF package to features 10/ Added GVF package to ordering information 10/ Added GVF terminal descriptions, Table / Added GVF mechanical drawing. 07/2004 hapters 1, 2, 8 Added RGVF, RZVF, and ZVF packages and pinout. 12/2004 hapters 1, 2, 8 Removed RGVF and RZVF packages and pinout. Added Section 1.5, Document onventions 1 3

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15 2 Terminal Descriptions The PI1510 controller is available in five packages, a 144-terminal quad flatpack (PGE), two 144-terminal MicroStar BGA packages (GGU/ZGU), and two 209-terminal PBGA packages (GVF/ZVF). The GGU and ZGU packages are mechanically and electrically identical, but the ZGU is a lead-free (Pb, atomic number 82) design. Throughout the remainder of this manual, only the GGU package designator is used for either the GGU or ZGU package. The terminal layout for the GGU package is shown in Figure 2 1. The GVF and ZVF packages are mechanically and electrically identical, but the ZVF is a lead-free (Pb, atomic number 82) design. Throughout the remainder of this manual, only the GVF package designator is used for either the GVF or ZVF package. The terminal layout for the GVF package is shown in Figure 2 2. The terminal layout with signal names for the PGE package is shown in Figure 2 3. GGU PAKAGE (TOP VIEW) ÎÎ ÎÎ ÎÎ T T M T 10 M M M T M M ÎÎ Î ÎÎ P M P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Î A B D E F G H J K L M N P T M PI Interface P ard Interface TPS Power Switch MFUN Pins ÎÎ V Ground (GND) Miscellaneous Figure 2 1. PI1510 GGU-Package Terminal Diagram 2 1

16 2 2 P GVF PAKAGE (TOP VIEW) P Î Î Î Î ÎÎ ÎÎ ÎÎ Î M T PI Interface P P ard Interface TPS Power Switch MFUN Pins V Ground (GND) Miscellaneous Î M N K L H J F G D B A E No onnection N P R W T U V M N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N T T T T M M M M M M P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P P Figure 2 2. PI1510 GVF-Package Terminal Diagram

17 2.1 PI1510 Terminal Assignments Figure 2 3 and Table 2 1 show the terminal assignments for the PGE package. Table 2 2 and Table 2 3 list the terminal assignments for the GGU and GVF packages, respectively. The signal names for the P ard slot are given in a ardbus // 16-bit signal format. All tables are arranged in order by increasing terminal designator, which is numeric for the PGE package and alphanumeric for the other packages. Table 2 4 and Table 2 5 list the ardbus and 16-bit signal names, respectively, in alphanumerical order with the corresponding terminal numbers for each package. PGE PAKAGE (TOP VIEW) VB IRDY//A15 FRAME//A23 GND /BE2//A12 AD17//A24 AD18//A7 AD19//A25 VS2//VS2 AD20//A6 RST//RESET AD21//A5 AD22//A4 REQ//INPAK AD23//A3 /BE3//REG VR_EN V AD24//A2 AD25//A1 AD26//A0 VS1//VS1 INT//READY(IREQ) GND SERR//WAIT AUDIO//BVD2(SPKR) STSHG//BVD1(STSHG/RI) LKRUN//WP(IOIS16) V D2//D2 AD27//D0 AD28//D8 AD29//D1 AD30//D9 RSVD//D2 AD31//D VPPD1 VPPD0 V MFUN6 MFUN5 MFUN4 GRST SUSPEND MFUN3 MFUN2 VR_PORT SPKROUT GND MFUN1 MFUN0 RI_OUT/PME AD0 AD1 V AD2 AD3 AD4 AD5 AD6 AD7 /BE0 AD8 AD9 AD10 AD11 AD12 AD13 GND AD14 AD15 /BE REQ GNT AD31 AD30 AD29 AD28 AD27 GND AD26 AD25 AD24 V /BE3 IDSEL AD23 AD22 AD21 AD20 PRST PLK GND AD19 AD18 AD17 AD16 /BE2 FRAME IRDY TRDY DEVSEL STOP V PERR SERR PAR VP TRDY//A22 LK//A16 DEVSEL//A21 GNT//WE V STOP//A20 PERR//A14 BLOK//A19 PAR//A13 RSVD//A18 /BE1//A8 AD16//A17 AD14//A9 AD15//IOWR AD13//IORD GND AD12//A11 AD11//OE AD10//E2 AD9//A10 /BE0//E1 AD8//D15 AD7//D7 LK_48_RSVD RSVD//D14 AD5//D6 AD6//D13 AD3//D5 GND AD4//D12 AD1//D4 AD2//D11 AD0//D3 D1//D1 VD1 VD Figure 2 3. PI1510 PGE-Package Terminal Diagram 2 3

18 Table 2 1. Signal Names Sorted by PGE Terminal Number SIGNAL NAME SIGNAL NAME TERMINAL ARDBUS 16-BIT TERMINAL ARDBUS 1 REQ REQ 43 AD11 AD11 2 GNT GNT 44 AD10 AD10 3 AD31 AD31 45 AD9 AD9 4 AD30 AD30 46 AD8 AD8 5 AD29 AD29 47 /BE0 /BE0 6 AD28 AD28 48 AD7 AD7 7 AD27 AD27 49 AD6 AD6 8 GND GND 50 AD5 AD5 9 AD26 AD26 51 AD4 AD4 10 AD25 AD25 52 AD3 AD3 11 AD24 AD24 53 AD2 AD2 16-BIT 12 V V 54 V V 13 /BE3 /BE3 55 AD1 AD1 14 IDSEL IDSEL 56 AD0 AD0 15 AD23 AD23 57 RI_OUT/PME RI_OUT/PME 16 AD22 AD22 58 MFUN0 MFUN0 17 AD21 AD21 59 MFUN1 MFUN1 18 AD20 AD20 60 GND GND 19 PRST PRST 61 SPKROUT SPKROUT 20 PLK PLK 62 VR_PORT VR_PORT 21 GND GND 63 MFUN2 MFUN2 22 AD19 AD19 64 MFUN3 MFUN3 23 AD18 AD18 65 SUSPEND SUSPEND 24 AD17 AD17 66 GRST GRST 25 AD16 AD16 67 MFUN4 MFUN4 26 /BE2 /BE2 68 MFUN5 MFUN5 27 FRAME FRAME 69 MFUN6 MFUN6 28 IRDY IRDY 70 V V 29 TRDY TRDY 71 VPPD0 VPPD0 30 DEVSEL DEVSEL 72 VPPD1 VPPD1 31 STOP STOP 73 VD0 VD0 32 V V 74 VD1 VD1 33 PERR PERR 75 D1 D1 34 SERR SERR 76 AD0 D3 35 PAR PAR 77 AD2 D11 36 VP VP 78 AD1 D4 37 /BE1 /BE1 79 AD4 D12 38 AD15 AD15 80 GND GND 39 AD14 AD14 81 AD3 D5 40 GND GND 82 AD6 D13 41 AD13 AD13 83 AD5 D6 42 AD12 AD12 84 RSVD D14 2 4

19 TERMINAL Table 2 1. Signal Names Sorted by PGE Terminal Number (ontinued) ARDBUS SIGNAL NAME 16-BIT TERMINAL ARDBUS SIGNAL NAME 85 LK_48_RSVD LK_48_RSVD 115 AD18 A7 86 AD7 D7 116 AD19 A25 87 AD8 D VS2 VS2 88 /BE0 E1 118 AD20 A6 89 AD9 A RST RESET 90 AD10 E2 120 AD21 A5 91 AD11 OE 121 AD22 A4 92 AD12 A REQ INPAK 93 GND GND 123 AD23 A3 94 AD13 IORD 124 /BE3 REG 95 AD15 IOWR 125 VR_EN VR_EN 96 AD14 A9 126 V V 97 AD16 A AD24 A2 98 /BE1 A8 128 AD25 A1 99 RSVD A AD26 A0 100 PAR A VS1 VS1 101 BLOK A INT READY(IREQ) 102 PERR A GND GND 103 STOP A SERR WAIT 104 V V 134 AUDIO BVD2(SPKR) 16-BIT 105 GNT WE 135 STSHG BVD1(STSHG/RI) 106 DEVSEL A LKRUN WP(IOIS16) 107 LK A V V 108 TRDY A D2 D2 109 VB VB 139 AD27 D0 110 IRDY A AD28 D8 111 FRAME A AD29 D1 112 GND GND 142 AD30 D9 113 /BE2 A RSVD D2 114 AD17 A AD31 D10 Terminal 85 is an N on the PI1510 to allow for terminal compatibility with the next generation of devices. 2 5

20 TERMINAL ARDBUS Table 2 2. Signal Names Sorted by GGU Terminal Number SIGNAL NAME 16-BIT TERMINAL ARDBUS SIGNAL NAME A01 /BE3 /BE3 D05 V V A02 GND GND D06 AUDIO BVD2(SPKR) A03 RSVD D2 D07 AD25 A1 A04 AD27 D0 D08 RST RESET A05 LKRUN WP(IOIS16) D09 /BE2 A12 A06 INT READY(IREQ) D10 AD23 A3 A07 V V D11 DEVSEL A21 A08 /BE3 REG D12 PERR A14 A09 VS2 VS2 D13 GNT WE A10 FRAME A23 E01 V V A11 GND GND E02 AD25 AD25 A12 AD18 A7 E03 AD31 AD31 A13 BLOK A19 E04 AD29 AD29 B01 AD27 AD27 E10 STOP A20 B02 VS1 VS1 E11 /BE1 A8 B03 AD31 D10 E12 PAR A13 B04 AD30 D9 E13 RSVD A18 B05 D2 D2 F01 AD22 AD22 B06 SERR WAIT F02 IDSEL IDSEL B07 AD24 A2 F03 AD24 AD24 B08 REQ INPAK F04 AD26 AD26 B09 AD19 A25 F10 AD16 A17 B10 AD17 A24 F11 AD14 A9 B11 VB VB F12 AD13 IORD B12 AD22 A4 F13 GND GND B13 LK A16 G01 PLK PLK 01 GNT GNT G02 AD20 AD20 02 REQ REQ G03 PRST PRST 03 AD23 AD23 G04 AD21 AD21 04 AD29 D1 G10 AD11 OE 05 AD28 D8 G11 AD9 A10 06 STSHG BVD1(STSHG/RI) G12 AD12 A11 07 AD26 A0 G13 AD10 E2 08 AD21 A5 H01 AD17 AD17 09 AD20 A6 H02 AD19 AD19 10 IRDY A15 H03 AD18 AD18 11 AD15 IOWR H04 GND GND 16-BIT 12 TRDY A22 H10 LK_48_RSVD LK_48_RSVD 13 V V H11 AD8 D15 D01 GND GND H12 AD7 D7 D02 AD28 AD28 H13 /BE0 E1 D03 AD30 AD30 J01 FRAME FRAME D04 VR_EN VR_EN J02 /BE2 /BE2 Terminal H10 is not bonded out in the packaged parts in order to have pin compatibility with future devices. 2 6

21 TERMINAL Table 2 2. Signal Names Sorted by GGU Terminal Number (ontinued) ARDBUS SIGNAL NAME 16-BIT TERMINAL ARDBUS SIGNAL NAME J03 TRDY TRDY L11 GRST GRST J04 AD16 AD16 L12 VD1 VD1 J10 AD5 D6 L13 D1 D1 J11 AD4 D12 M01 V V J12 RSVD D14 M02 AD9 AD9 J13 AD3 D5 M03 /BE1 /BE1 K01 IRDY IRDY M04 AD15 AD15 K02 DEVSEL DEVSEL M05 AD10 AD10 K03 PERR PERR M06 AD5 AD5 K04 AD4 AD4 M07 AD1 AD1 K05 AD13 AD13 M08 RI_OUT/PME RI_OUT/PME K06 /BE0 /BE0 M09 SPKROUT SPKROUT K07 MFUN0 MFUN0 M10 MFUN4 MFUN4 K08 GND GND M11 VPPD1 VPPD1 K09 VPPD0 VPPD0 M12 AD2 D11 K10 MFUN3 MFUN3 M13 GND GND K11 AD0 D3 N01 PAR PAR K12 AD1 D4 N02 GND GND K13 AD6 D13 N03 AD12 AD12 L01 STOP STOP N04 AD8 AD8 L02 SERR SERR N05 AD7 AD7 L03 VP VP N06 AD3 AD3 L04 AD11 AD11 N07 V V L05 AD14 AD14 N08 AD0 AD0 L06 AD6 AD6 N09 MFUN1 MFUN1 L07 AD2 AD2 N10 SUSPEND SUSPEND L08 VR_PORT VR_PORT N11 V V L09 MFUN2 MFUN2 N12 MFUN5 MFUN5 L10 MFUN6 MFUN6 N13 VD0 VD0 16-BIT 2 7

22 Table 2 3. Signal Names Sorted by GVF Terminal Number SIGNAL NAME SIGNAL NAME TERMINAL ARDBUS 16-BIT TERMINAL ARDBUS A04 VPPD0 VPPD0 E07 N N A05 V V E08 AD31 D10 A06 N N E09 AD28 D8 A07 GND GND E10 SERR WAIT A08 V V E11 AD25 A1 A09 STSHG BVD1(STSHG/RI) E12 AD21 A5 A10 GND GND E13 AD18 A7 A11 VB VB E14 TRDY A22 A12 AD23 A3 E17 STOP A20 A13 V V E18 BLOK A19 16-BIT A14 AD19 A25 E19 V V A15 GND GND F01 MFUN5 MFUN5 A16 DEVSEL A21 F02 MFUN3 MFUN3 B05 VD1 VD1 F03 MFUN2 MFUN2 B06 N N F05 MFUN0 MFUN0 B07 N N F06 N N B08 AD29 D1 F07 N N B09 LKRUN WP(IOIS16) F08 RSVD D2 B10 VS1 VS1 F09 AD27 D0 B11 /BE3 REG F10 AUDIO BVD2(SPKR) B12 REQ INPAK F11 AD26 A0 B13 RST RESET F12 VS2 VS2 B14 AD17 A24 F13 IRDY A15 B15 FRAME A23 F14 PAR A13 05 VPPD1 VPPD1 F15 PERR A14 06 N N F17 RSVD A18 07 N N F18 AD16 A17 08 AD30 D9 F19 AD14 A9 09 D2 D2 G01 V V 10 INT READY(IREQ) G02 VR_PORT VR_PORT 11 AD24 A2 G03 SUSPEND SUSPEND 12 AD22 A4 G05 MFUN4 MFUN4 13 AD20 A6 G06 MFUN1 MFUN1 14 /BE2 A12 G14 VB VB 15 LK A16 G15 /BE1 A8 D01 N N G17 AD15 IOWR D19 GNT WE G18 AD13 IORD E01 GND GND G19 GND GND E02 SPKROUT SPKROUT H01 PLK PLK E03 N N H02 GRST GRST E05 N N H03 PRST PRST E06 VD0 VD0 H05 VR_EN VR_EN Terminal F06 is not bonded out in the packaged parts in order to have pin compatibility with future devices. 2 8

23 Table 2 3. Signal Names Sorted by GVF Terminal Number (ontinued) TERMINAL ARDBUS SIGNAL NAME 16-BIT TERMINAL ARDBUS SIGNAL NAME H06 MFUN6 MFUN6 M17 N N H14 AD11 OE M18 N N H15 AD12 A11 M19 N N H17 AD10 E2 N01 GND GND H18 AD9 A10 N02 AD19 AD19 H19 V V N03 AD18 AD18 J01 GNT GNT N05 FRAME FRAME J02 REQ REQ N06 AD17 AD17 J03 RI_OUT/PME RI_OUT/PME N14 N N J05 AD31 AD31 N15 N N J06 AD30 AD30 N17 N N J14 AD8 D15 N18 N N J15 /BE0 E1 N19 N N J17 AD7 D7 P01 AD16 AD16 J18 RSVD D14 P02 /BE2 /BE2 J19 AD5 D6 P03 IRDY IRDY K01 GND GND P05 STOP STOP K02 AD29 AD29 P06 TRDY TRDY K03 AD28 AD28 P07 AD14 AD14 K05 AD27 AD27 P08 AD9 AD9 K06 AD26 AD26 P09 N N K14 AD6 D13 P10 N N K15 AD3 D5 P11 N N K17 AD4 D12 P12 N N K18 AD1 D4 P13 N N K19 GND GND P14 N N L01 VP VP P15 N N L02 AD25 AD25 P17 N N L03 AD24 AD24 P18 N N L05 IDSEL IDSEL P19 GND GND L06 /BE3 /BE3 R01 V V L14 AD2 D11 R02 DEVSEL DEVSEL L15 AD0 D3 R03 PERR PERR L17 D1 D1 R06 AD15 AD15 L18 VR_PORT VR_PORT R07 AD10 AD10 L19 V V R08 AD6 AD6 M01 V V R09 AD0 AD0 M02 AD23 AD23 R10 N N M03 AD22 AD22 R11 N N M05 AD20 AD20 R12 N N M06 AD21 AD21 R13 N N M14 N N R14 N N M15 N N R17 N N 16-BIT 2 9

24 Table 2 3. Signal Names Sorted by GVF Terminal Number (ontinued) TERMINAL ARDBUS SIGNAL NAME 16-BIT TERMINAL ARDBUS SIGNAL NAME R18 N N V10 N N R19 N N V11 N N T01 SERR SERR V12 N N T19 N N V13 N N U05 /BE1 /BE1 V14 N N U06 AD12 AD12 V15 N N U07 AD8 AD8 W04 PAR PAR U08 AD5 AD5 W05 VP VP U09 AD1 AD1 W06 GND GND U10 N N W07 AD7 AD7 U11 N N W08 V V U12 N N W09 AD3 AD3 U13 N N W10 N N U14 N N W11 N N U15 N N W12 N N V05 AD13 AD13 W13 N N V06 AD11 AD11 W14 N N V07 /BE0 /BE0 W15 N N V08 AD4 AD4 W16 N N V09 AD2 AD2 16-BIT 2 10

25 Table 2 4. ardbus P ard Signal Names Sorted Alphabetically to Device Terminals TERMINAL TERMINAL SIGNAL NAME PGE GGU GVF SIGNAL NAME PGE GGU GVF AD0 56 N08 R09 AD11 91 G10 H14 AD1 55 M07 U09 AD12 92 G12 H15 AD2 53 L07 V09 AD13 94 F12 G18 AD3 52 N06 W09 AD14 96 F11 F19 AD4 51 K04 V08 AD G17 AD5 50 M06 U08 AD16 97 F10 F18 AD6 49 L06 R08 AD B10 B14 AD7 48 N05 W07 AD A12 E13 AD8 46 N04 U07 AD B09 A14 AD9 45 M02 P08 AD AD10 44 M05 R07 AD E12 AD11 43 L04 V06 AD B12 12 AD12 42 N03 U06 AD D10 A12 AD13 41 K05 V05 AD B07 11 AD14 39 L05 P07 AD D07 E11 AD15 38 M04 R06 AD F11 AD16 25 J04 P01 AD A04 F09 AD17 24 H01 N06 AD E09 AD18 23 H03 N03 AD B08 AD19 22 H02 N02 AD B04 08 AD20 18 G02 M05 AD B03 E08 AD21 17 G04 M06 AUDIO 134 D06 F10 AD22 16 F01 M03 /BE0 47 K06 V07 AD M02 /BE1 37 M03 U05 AD24 11 F03 L03 /BE2 26 J02 P02 AD25 10 E02 L02 /BE3 13 A01 L06 AD26 9 F04 K06 BLOK 101 A13 E18 AD27 7 B01 K05 /BE0 88 H13 J15 AD28 6 D02 K03 /BE1 98 E11 G15 AD29 5 E04 K02 /BE2 113 D09 14 AD30 4 D03 J06 /BE3 124 A08 B11 AD31 3 E03 J05 D1 75 L13 L17 AD0 76 K11 L15 D2 138 B05 09 AD1 78 K12 K18 LK 107 B13 15 AD2 77 M12 L14 LKRUN 136 A05 B09 AD3 81 J13 K15 DEVSEL 106 D11 A16 AD4 79 J11 K17 FRAME 111 A10 B15 AD5 83 J10 J19 GNT 105 D13 D19 AD6 82 K13 K14 INT 131 A06 10 AD7 86 H12 J17 IRDY F13 AD8 87 H11 J14 LK_48_RSVD 85 H10 AD9 89 G11 H18 PAR 100 E12 F14 AD10 90 G13 H17 PERR 102 D12 F

26 Table 2 4. ardbus P ard Signal Names Sorted Alphabetically to Device Terminals (ontinued) TERMINAL TERMINAL SIGNAL NAME PGE GGU GVF SIGNAL NAME PGE GGU GVF REQ 122 B08 B12 MFUN4 67 M10 G05 RST 119 D08 B13 MFUN5 68 N12 F01 RSVD 84 A03 F08 MFUN6 69 L10 H06 RSVD 99 E13 F17 PAR 35 N01 W04 RSVD 143 J12 J18 PLK 20 G01 H01 SERR 133 B06 E10 PERR 33 K03 R03 STOP 103 E10 E17 PRST 19 G03 H03 STSHG A09 REQ 1 02 J02 TRDY E14 RI_OUT/PME 57 M08 J03 VS1 130 B02 B10 SERR 34 L02 T01 VS2 117 A09 F12 SPKROUT 61 M09 E02 DEVSEL 30 K02 R02 STOP 31 L01 P05 FRAME 27 J01 N05 SUSPEND 65 N10 G03 GNT 2 01 J01 TRDY 29 J03 P06 GRST 66 L11 H02 VD0 73 N13 E06 IDSEL 14 F02 L05 VD1 74 L12 B05 IRDY 28 K01 P03 VPPD0 71 K09 A04 MFUN0 58 K07 F05 VPPD1 72 M11 05 MFUN1 59 N09 G06 VR_EN 125 D04 H05 MFUN2 63 L09 F03 VR_PORT 62 L08 G02, L18 MFUN3 64 K10 F

27 Table Bit P ard Signal Names Sorted Alphabetically to Device Terminals TERMINAL TERMINAL SIGNAL NAME PGE GGU GVF SIGNAL NAME PGE GGU GVF AD0 56 N08 R09 A11 92 G12 H15 AD1 55 M07 U09 A D09 14 AD2 53 L07 V09 A E12 F14 AD3 52 N06 W09 A D12 F15 AD4 51 K04 V08 A F13 AD5 50 M06 U08 A B13 15 AD6 49 L06 R08 A17 97 F10 F18 AD7 48 N05 W07 A18 99 E13 F17 AD8 46 N04 U07 A A13 E18 AD9 45 M02 P08 A E10 E17 AD10 44 M05 R07 A D11 A16 AD11 43 L04 V06 A E14 AD12 42 N03 U06 A A10 B15 AD13 41 K05 V05 A B10 B14 AD14 39 L05 P07 A B09 A14 AD15 38 M04 R06 BVD1(STSHG/RI) A09 AD16 25 J04 P01 BVD2(SPKR) 134 D06 F10 AD17 24 H01 N06 /BE0 47 K06 V07 AD18 23 H03 N03 /BE1 37 M03 U05 AD19 22 H02 N02 /BE2 26 J02 P02 AD20 18 G02 M05 /BE3 13 A01 L06 AD21 17 G04 M06 D1 75 L13 L17 AD22 16 F01 M03 D2 138 B05 09 AD M02 E1 88 H13 J15 AD24 11 F03 L03 E2 90 G13 H17 AD25 10 E02 L02 LK_48_RSVD 85 H10 AD26 9 F04 K06 DEVSEL 30 K02 R02 AD27 7 B01 K05 D0 139 A04 F09 AD28 6 D02 K03 D B08 AD29 5 E04 K02 D2 143 A03 F08 AD30 4 D03 J06 D3 76 K11 L15 AD31 3 E03 J05 D4 78 K12 K18 A F11 D5 81 J13 K15 A1 128 D07 E11 D6 83 J10 J19 A2 127 B07 11 D7 86 H12 J17 A3 123 D10 A12 D E09 A4 121 B12 12 D9 142 B04 08 A E12 D B03 E08 A D11 77 M12 L14 A7 115 A12 E13 D12 79 J11 K17 A8 98 E11 G15 D13 82 K13 K14 A9 96 F11 F19 D14 84 J12 J18 A10 89 G11 H18 D15 87 H11 J

28 Table Bit P ard Signal Names Sorted Alphabetically to Device Terminals (ontinued) TERMINAL TERMINAL SIGNAL NAME PGE GGU GVF SIGNAL NAME PGE GGU GVF FRAME 27 J01 N05 REG 124 A08 B11 GNT 2 01 J01 REQ 1 02 J02 GRST 66 L11 H02 RESET 119 D08 B13 IDSEL 14 F02 L05 RI_OUT/PME 57 M08 J03 INPAK 122 B08 B12 SERR 34 L02 T01 IORD 94 F12 G18 SPKROUT 61 M09 E02 IOWR G17 STOP 31 L01 P05 IRDY 28 K01 P03 SUSPEND 65 N10 G03 MFUN0 58 K07 F05 TRDY 29 J03 P06 MFUN1 59 N09 G06 VD0 73 N13 E06 MFUN2 63 L09 F03 VD1 74 L12 B05 MFUN3 64 K10 F02 VPPD0 71 K09 A04 MFUN4 67 M10 G05 VPPD1 72 M11 05 MFUN5 68 N12 F01 VR_EN 125 D04 H05 MFUN6 69 L10 H06 VR_PORT 62 L08 G02, L18 OE 91 G10 H14 VS1 130 B02 B10 PAR 35 N01 W04 VS2 117 A09 F12 PLK 20 G01 H01 WAIT 133 B06 E10 PERR 33 K03 R03 WE 105 D13 D19 PRST 19 G03 H03 WP(IOIS16) 136 A05 B09 READY(IREQ) 131 A

29 2.2 Terminal Descriptions The terminals are grouped in tables by functionality, such as PI system function, power-supply function, etc. The terminal numbers are also listed for convenient reference. Table 2 6. Power Supply Terminals TERMINAL NUMBER I/O DESRIPTION NAME PGE GGU GVF GND V 8, 21, 40, 60, 80, 93, 112, , 32, 54, 70, 104, 126, 137 A02, A11, D01, F13, H04, K08, M13, N02 A07, 13, D05, E01, M01, N07, N11 A07, A10, A15, E01, G19, K01, K19, N01, P19, W06 A05, A08, A13, E19, G01, H19, L19, M01, R01, W08 Device ground terminals Power supply terminals for I/O and internal voltage regulator VB 109 B11 A11, G14 lamp voltage for P ard interface. Matches card signaling environment, 5 V or 3.3 V VP 36 L03 L01, W05 lamp voltage for PI and miscellaneous I/O, 5 V or 3.3 V VR_EN 125 D04 H05 I Internal voltage regulator enable. Active-low VR_PORT 62 L08 G02, L18 Internal voltage regulator input/output. When VR_EN is low, the regulator is enabled and this terminal is an output. An external bypass capacitor is required on this terminal. When VR_EN is high, the regulator is disabled and this terminal is an input for an external 2.5-V core power source. NAME VD0 VD1 VPPD0 VPPD1 Table 2 7. P ard Power Switch Terminals TERMINAL NUMBER I/O DESRIPTION PGE GGU GVF N13 L12 K09 M11 E06 B05 A04 05 O O Logic controls to the TPS2211A P ard power interface switch to control AV Logic controls to the TPS2211A P ard power interface switch to control AVPP 2 15

30 NAME TERMINAL Table 2 8. PI System Terminals NUMBER I/O DESRIPTION PGE GGU GVF GRST 66 L11 H02 I PLK 20 G01 H01 I PRST 19 G03 H03 I Global reset. When the global reset is asserted, the GRST signal causes the controller to place all output buffers in a high-impedance state and reset all internal registers. When GRST is asserted, the device is completely in its default state. For systems that require wake-up from D3, GRST normally is asserted only during initial boot. PRST must be asserted following initial boot so that PME context is retained during the transition from D3 to D0. When the SUSPEND mode is enabled, the device is protected from GRST, and the internal registers are preserved. All outputs are placed in a high-impedance state. PI bus clock. PLK provides timing for all transactions on the PI bus. All PI signals are sampled at the rising edge of PLK. PI bus reset. When the PI bus reset is asserted, PRST causes the controller to place all output buffers in a high-impedance state and reset internal registers. When PRST is asserted, the device can generate the PME signal only if it is enabled. After PRST is deasserted, the controller is in a default state. When the SUSPEND mode is enabled, the device is protected from PRST, and the internal registers are preserved. All outputs are placed in a high-impedance state. 2 16

31 NAME AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 /BE3 /BE2 /BE1 /BE0 TERMINAL Table 2 9. PI Address and Data Terminals NUMBER I/O DESRIPTION PGE GGU GVF 3 E03 J05 4 D03 J06 5 E04 K02 6 D02 K03 7 B01 K05 9 F04 K06 10 E02 L02 11 F03 L M02 16 F01 M03 17 G04 M06 18 G02 M05 22 H02 N02 23 H03 N03 24 H01 N06 25 J04 P01 38 M04 R06 39 L05 P07 41 K05 V05 42 N03 U06 43 L04 V06 44 M05 R04 45 M02 P08 46 N04 U07 48 N05 W07 49 L06 R08 50 M06 U08 51 K04 V08 52 N06 W09 53 L07 V09 55 M07 U09 56 N08 R A01 J02 M03 K06 L06 P02 U05 V07 I/O I/O PAR 35 N01 W04 I/O PI address/data bus. These signals make up the multiplexed PI address and data bus on the primary interface. During the address phase of a primary-bus PI cycle, AD31 AD0 contain a 32-bit address or other destination information. During the data phase, AD31 AD0 contain data. PI-bus commands and byte enables. These signals are multiplexed on the same PI terminals. During the address phase of a primary-bus PI cycle, /BE3 /BE0 define the bus command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable determines which byte paths of the full 32-bit data bus carry meaningful data. /BE0 applies to byte 0 (AD7 AD0), /BE1 applies to byte 1 (AD15 AD8), /BE2 applies to byte 2 (AD23 AD16), and /BE3 applies to byte 3 (AD31 AD24). PI-bus parity. In all PI-bus read and write cycles, the controller calculates even parity across the AD31 AD0 and /BE3 /BE0 buses. As an initiator during PI cycles, the controller outputs this parity indicator with a one-plk delay. As a target during PI cycles, the controller compares its calculated parity to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR). 2 17

32 NAME TERMINAL Table PI Interface ontrol Terminals NUMBER I/O DESRIPTION PGE GGU GVF DEVSEL 30 K02 R02 I/O FRAME 27 J01 N05 I/O GNT 2 01 J01 I IDSEL 14 F02 L05 I IRDY 28 K01 P03 I/O PERR 33 K03 R03 I/O REQ 1 02 J02 O SERR 34 L02 T01 O STOP 31 L01 P05 I/O TRDY 29 J03 P06 I/O PI device select. The controller asserts DEVSEL to claim a PI cycle as the target device. As a PI initiator on the bus, the controller monitors DEVSEL until a target responds. If no target responds before timeout occurs, then the controller terminates the cycle with an initiator abort. PI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME is deasserted, the PI bus transaction is in the final data phase. PI bus grant. GNT is driven by the PI bus arbiter to grant the controller access to the PI bus after the current data transaction has completed. GNT may or may not follow a PI bus request, depending on the PI bus parking algorithm. Initialization device select. IDSEL selects the controller during configuration space accesses. IDSEL can be connected to one of the upper 24 PI address lines on the PI bus. PI initiator ready. IRDY indicates the ability of the PI bus initiator to complete the current data phase of the transaction. A data phase is completed on a rising edge of PLK where both IRDY and TRDY are asserted. Until IRDY and TRDY are both sampled asserted, wait states are inserted. PI parity error indicator. PERR is driven by a PI device to indicate that calculated parity does not match PAR when PERR is enabled through bit 6 of the command register (PI offset 04h, see Section 4.4). PI bus request. REQ is asserted by the controller to request access to the PI bus as an initiator. PI system error. SERR is an output that is pulsed from the controller when enabled through bit 8 of the command register (PI offset 04h, see Section 4.4) indicating a system error has occurred. The controller need not be the target of the PI cycle to assert this signal. When SERR is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a ardbus interface. PI cycle stop signal. STOP is driven by a PI target to request the initiator to stop the current PI bus transaction. STOP is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. PI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of the transaction. A data phase is completed on a rising edge of PLK when both IRDY and TRDY are asserted. Until both IRDY and TRDY are asserted, wait states are inserted. 2 18