Distributed Operation Layer Integrated SW Design Flow for Mapping Streaming Applications to MPSoC

Transcription

1 Distributed Operation Layer Integrated SW Design Flow for Mapping Streaming Applications to MPSoC Iuliana Bacivarov, Wolfgang Haid, Kai Huang, and Lothar Thiele ETH Zürich

2 MPSoCs are Hard to program ( system specification) to implement ( system synthesis) to optimize ( design space exploration) to analyze ( performance analysis) In each phase, there is (unavoidable) essential complexity (avoidable) accidental complexity Map2Mpsoc, June 2009 Distributed Operation Layer 2

3 Essential Complexity Complexity that is inherent to the problem System specification Scalable applications and architectures System synthesis Automated synthesis is hard Design space exploration NP-hard problem Performance analysis Parallel, distributed, heterogeneous systems Complex interactions on shared resources Map2Mpsoc, June 2009 Distributed Operation Layer 3

4 Accidental Complexity Consequence of the way we choose to solve a problem System specification Difficult if based on board-support package System synthesis Difficult to automate, if not based on a fixed (formal) specification Design space exploration Difficult if based on ad-hoc decisions Performance analysis Difficult if done using only a simulation platform Map2Mpsoc, June 2009 Distributed Operation Layer 4

5 Approach Reduce accidental complexity by raising the level of abstraction and automation System specification Abstract model of computation and high-level API System synthesis Automated (software) synthesis on different MPSoC Design space exploration Automated exploration instead of trial-and-error Performance analysis System-level (formal) analysis instead of simulation Map2Mpsoc, June 2009 Distributed Operation Layer 5

6 Outline of this Talk Introduction Distributed Operation Layer (DOL) design flow Specification Synthesis Design space exploration Performance analysis Some experimental results Conclusions Map2Mpsoc, June 2009 Distributed Operation Layer 6

7 DOL Programming Environment Goal Automatically generate an optimal mapping of a parallel application onto MPSoC Challenges Scalable specification Automated synthesis Design space exploration System-level performance analysis Map2Mpsoc, June 2009 Distributed Operation Layer 7

8 System Specification Goal Express the data and functional parallelism in an application Specify the mapping of the application onto the target architecture Challenges Scalability Platform-independence Map2Mpsoc, June 2009 Distributed Operation Layer 8

9 DOL Programming Model Model of computation: Kahn process network Coordination language: XML with performance annotations Functionality of processes: C/C++ with specific programming DOL API Scalability: iterators for large, multi-tile descriptions Map2Mpsoc, June 2009 Distributed Operation Layer 9

10 DOL Abstract Platform Modeling tile_0.magic DDM tile_0.ddm tile_0.arm magicv ARM9 RDM tile_0.rdm MAGIC BUS tile_0.magicbus ARM BUS tile_0.armbus tile_0.dma DMA AHB 1 tile_0.ahb1 Elements DXM tile_0.dxm Structure: processors, peripherals, memories, buses, etc. Interconnects: explicit read and write communication paths Performance data: e.g. latency and bandwidth of HW communication channels Specification: XML, including the iterators capability Map2Mpsoc, June 2009 Distributed Operation Layer 10

11 DOL Mapping Specification Mapping: Binding Processes to processors SW channels to R/W paths Scheduling Constraints Mapping representation in the DOL GUI Strategy Manual Automatic Map2Mpsoc, June 2009 Distributed Operation Layer 11

12 System Synthesis Goal Close the gap between system-level specification and implementation Challenges Achieve desired performance Handle deadlocks, starvation, and data races Preserve KPN semantics Map2Mpsoc, June 2009 Distributed Operation Layer 12

13 DOL Synthesis Strategy Source-to-source code generators from DOL KPN application to implementation Automatic generation of the glue code : processes and channels implementation, bootstrapping, and scheduling Synthesis Functional synthesis SystemC untimed, native execution Software synthesis Platforms: MPARM (U. Bologna Predator Project), Atmel DIOPSIS (Atmel Rome Shapes Project), Cell BE Map2Mpsoc, June 2009 Distributed Operation Layer 13

14 DOL Functional Synthesis Automatic synthesis of DOL KPN in functional SystemC KPN application T1 T2 T3 Synthesis DOL processes and FIFOs: SystemC threads and channels SystemC main file: bootstrapping and scheduling Features Execution: native, un-timed Debugging: standard tools, i.e. gdb Performance data extraction: monitor DOL READ, WRITE, FIRE Map2Mpsoc, June 2009 Distributed Operation Layer 14

15 DOL Software Synthesis MPARM: identical ARM7 tiles connected by AMBA bus Atmel Diopsis 940: tile:arm9+dsp connected by an AMBA bus; several tiles connected via NoC Cell BE: PowerPC and 8 DSP-like SPEs connected via ring bus SPU SPU SPU SPU SPU SPU SPU SPU LS LS LS LS LS LS LS LS SPE MFC MFC MFC MFC MFC MFC MFC MFC Element interconnect bus (EIB) L2 Cache L1 Cache PPU PPE MIC Main storage Memory Legend: LS: Local Store MFC: Memory Flow Controller MIC: Memory Interface Controller PPE: Power Processor Element PPU: Power Processor Unit SPE: Synergistic Processor Elements SPU: Synergistic Processor Unit Map2Mpsoc, June 2009 Distributed Operation Layer 15

16 Design Space Exploration Goal Find the Pareto-optimal mappings of an application onto a given architecture Challenges Exhaustive search of the design space not feasible Instruction-accurate simulation too slow for design space exploration Map2Mpsoc, June 2009 Distributed Operation Layer 16

17 Mapping Optimization Framework Modular framework: optimization and performance analysis plug-ins Evolutionary algorithm: SPEA2 (Strength Pareto Evolutionary Algorithm) Performance analysis: MPA (Modular Performance Analysis) analytic model Control & GUI: EXPO Interface: PISA Map2Mpsoc, June 2009 Distributed Operation Layer 17

18 Performance Analysis Goal Feedback for developer Verification of single designs Decision basis for design space exploration Challenges Accuracy Speed Map2Mpsoc, June 2009 Distributed Operation Layer 18

19 DOL Performance Analysis Goal: design of real-time systems (for multi-media, signal processing) Method: Modular Performance Analysis (MPA) Challenge: integration of MPA in DOL Generate an MPA model from a high-level specification Calibrate the MPA model with accurate data Map2Mpsoc, June 2009 Distributed Operation Layer 19

20 Performance Analysis using MPA Design: abstract event streams traversing a network of abstract processing units dynamics aspects: scheduling Output: worst-case bounds on system properties Modular Performance Analysis (Large) MPSoC extensions: complex activation schemes, timing correlations, blocking semantics, cyclic dependencies Map2Mpsoc, June 2009 Distributed Operation Layer 20

21 MPA Model Generation Annotated DOL spec MPA model Matlab script for MPA toolbox Automated MPA model generation in 2 steps Framework-independent model (XML format) Framework-specific model and Matlab script Challenges Relation: DOL spec and MPA model Sequential evaluation of parallel MPA model Accurate parameters Map2Mpsoc, June 2009 Distributed Operation Layer 21

22 MPA Model Calibration Goal: collect accurate performance data from simulation Problem: too slow during design space exploration Strategy: collect parameters beforehand, by using calibration mappings XML specification binary generation TCL script generation backannotation trace generator log file analysis Map2Mpsoc, June 2009 Distributed Operation Layer 22

23 A Few Experimental Results MJPEG application executing on the MPARM MPSoC (optimal) mapping Map2Mpsoc, June 2009 Distributed Operation Layer 23

24 Design Space Exploration PISA and EXPO environment (SPEA2 evolutionary algorithm) 2 objectives: End-to-end delay (upper bound in MPA) Cost (additive model) Population: 60 individuals Nb. generations: 50 Pareto front: 12 solutions Search time: ~2 hours Map2Mpsoc, June 2009 Distributed Operation Layer 24

25 Performance Analysis Mapping of the MJPEG application onto a 3-tile MPARM system Map2Mpsoc, June 2009 Distributed Operation Layer 25

26 Some Performance Figures Model calibration: time-expensive (usual for all flows) cannot be included in the design space exploration loop Model generation and performance analysis in MPA: sec. reasonable for design space exploration Map2Mpsoc, June 2009 Distributed Operation Layer 26

27 Some Performance Figures Bounds derived by MPA w.r.t. actual (average-case behavior) observed during system simulation Differences: avg.10-20% typical for compositional performance analysis [Perathoner et al. 2007] Some MPA operators do not produce tight bounds Simulation cannot provide the actual worst/best-case behavior (lack of exhaustive test patterns) Map2Mpsoc, June 2009 Distributed Operation Layer 27

28 Some Performance Figures The DOL framework is mainly implemented in Java (available at Code size of different parts of the design flow: Map2Mpsoc, June 2009 Distributed Operation Layer 28

29 Conclusions Accidental complexity can be considerably reduced compared to brute-force methods Using a fixed MoC (KPN) vs. BSP approaches Automated performance analysis vs. manual analysis Automated design space exploration vs. ad-hoc techniques Complete SW design flow (specification, synthesis, design space exploration, performance analysis) DOL is available: Map2Mpsoc, June 2009 Distributed Operation Layer 29

30 Distribution of the DOL Design Flow Distribution elements available for download* DOL basic package Design space exploration environment Modular performance analysis generation DOL graphical front-end DOL benchmarks *all these packages include a complete documentation Map2Mpsoc, June 2009 Distributed Operation Layer 30

31 Thank You! Questions?