Part 2: Principles for a System-Level Design Methodology

Transcription

1 Part 2: Principles for a System-Level Design Methodology Separation of Concerns: Function versus Architecture Platform-based Design 1

2 Design Effort vs. System Design Value Function Level of Abstraction HW/SW Architecture RTL - SW Design Entry Level Design Entry Level Design Entry Level Conceptual Design Entry Level Gap Design Entry Level Design Entry Level RTL/Gate platform Today Tomorrow Mask - ASM Effort/Value 2

3 Design Effort vs. System Design Value Function Level of Abstraction HW/SW Architecture RTL - SW Design Entry Level Hand-off platform Hand-off platform Hand-off platform Hand-off platform Hand-off platform Today Tomorrow Mask - ASM Effort/Value 3

4 System-Level Design Science Design Methodology: Top Down Aspect: Orthogonalization of Concerns: Separate Implementation from Conceptual Aspects Separate computation from communication Formalization: precise unambiguous semantics Abstraction: capture the desired system details (do not over-specify) Decomposition: partitioning the system behavior into simpler behaviors Successive Refinements: refine the abstraction level down to the implementation by filling in details and passing constraints Bottom Up Aspect: 4 IP Re-use (even at the algorithmic and functional level) Components of architecture from pre-existing library

5 Separate Behavior from Micro-architecture System Behavior Functional Specification of System. No notion of hardware or software! Implementation Architecture Hardware and Software Optimized Computer Front End 1 Transport Decode 2 Rate 12 Rate 5 Mem 13 User/Sys Control 3 Synch Control 4 Video Decode 6 Sensor Frame 7 Video Output 8 External I/O MPEG Peripheral Processor Bus DSP Processor DSP RAM Control Processor Rate 9 Audio Decode/ Output 10 Audio Decode System RAM 5 Mem 11

6 Models of Computation: And There are More... Continuous time (ODEs) Spatial/temporal (PDEs) Discrete time Rendezvous Synchronous/Reactive Dataflow... Each of these provides a formal framework for reasoning about certain aspects of embedded systems. Tower of Babel, Bruegel,

7 Formalization Model of a design with precise unambiguous semantics: Implicit or explicit relations: inputs, outputs and (possibly) state variables Properties Cost functions Constraints Formalization of Design + Environment = closed system of equations and inequalities over some algebra. 7

8 Validating Designs By construction property is inherent. By verification property is provable. By simulation check behavior for all inputs. By intuition property is true. I just know it is. By assertion property is true. Wanna make something of it? By intimidation Don t even try to doubt whether it is true It is generally better to be higher in this list 8

9 Notion of Time 9

10 System Specifications 10

11 Two Basic Questions Question I - IP Authoring 11 IP Block Authoring Embedded System Requirements IP Block Definition Executable System Level Block Level Specification Iterative Refinement Block Implementation Implementation Level Verification Synthesis / Place & Route etc. How to design a system block? Starting from the system level With a consistent test-bench Getting from the abstract, untimed system model to the clocked HW or SW implementation model Example Rake Receiver Which are the optimal algorithms? How does it work fixed point? How is it best implemented? Does the implementation work as specified in the system level

12 Two Basic Questions Question II IP Integration 12 How to integrate system blocks? Starting from the system level With a consistent test-bench Getting from the abstract, un-timed system model to the clocked HW or SW implementation model Communication between blocks Addressing Platform Based design Example 3G Cell phone Which are the optimal algorithms? Do they work together functionally? Is the architecture sufficient? Does the implementation integration work? Embedded System Requirements Platform Function Performance Analysis and Platform Configuration Communication Refinement Communication Integration Hardware Assembly System Integration Platform Architecture Software Assembly Implementation Level Verification Synthesis / Place & Route etc. IP Block System Integration

13 Historical Perspective: Ptolemy E. Lee Project at UC Berkeley Multiple models of computation DSP beginnings: Static Dataflow Many other models: FSM, Discrete Event Mixed model verification

14 A bit of history: the POLIS project 1988: The problem: Climate Control Info System Engine Control Exhaust Control Active Suspensions The target architecture: Transmission ABS compute air flow air flow throttle position engine speed air temperature air pressure compute injection time look-up table engine temperature injection time drive actuators PWM signals 68HC11 ROM Intfc. 14

15 The Essence of the Polis/Felix/VCC Approach 1988: Traditional System Design VCC Separation and Mapping System Behavior System Implementation System Architecture System Performance System Behavior System Architecture 1 2 Mapping Behavior on Architecture Refine 3 Data Sheets on paper 4 Implementation of System Executable Data Sheets 15

16 Example of System Behavior Mem 13 Rate 12 User/Sys Control 3 Sensor Satellite Dish Synch Control 4 remote Front End 1 Transport Decode 2 Rate 5 Video Decode 6 Frame 7 Video Output 8 Cable Rate 9 Audio Decode/ Output 10 monitor Mem 11 speakers

17 IP-Based Design of the System Behavior System Integration Communication Protocol Designed in Felix Testbench Designed in BONeS Rate 12 Mem 13 User/Sys Control 3 Sensor User Interface Written in C Satellite Dish Synch Control 4 remote Front End 1 Transport Decode 2 Rate 5 Video Decode 6 Frame 7 Video Output 8 Cable Rate 9 Audio Decode/ Output 10 monitor Baseband Processing Designed in SPW Mem 11 speakers Transport Decode Written in C Decoding Algorithms Designed in SPW

18 Challenges and Trends Cost ($M) Design Costs Validation Physical Prototype Verification Architecture 0.35µm 0.25µm 0.18µm 0.13µm 90nm 9,000 8,500 8,000 7,500 7,000 6,500 6,000 Design Starts -27% Estimated Engineering Months Increased SW Effort Cell-Based ASICs becoming prohibitively expensive for all but $1,000,000 highest Process Geometry Mask Costs $1,500,000 Mask Costs volume applications Shift to $500,000 Re-use Strategy at all levels $0 Higher Level 250 of 180 Abstractions Software!!! Technology (nm) 18

19 The Quest for the Next Level of Abstraction Transistor Model Capacity Load Gate Level Model Capacity Load SDF Wire Load IP Block Performance Inter IP Communication Performance Models IP Blocks abstract abstract abstract RTL cluster RTL Clusters SW Models cluster abstract cluster s 1980s 1990s 2000+

20 IP-Based Design of the Implementation Which Bus? PI? AMBA? Dedicated Bus for DSP? Which DSP Processor? C50? Can DSP be done on Microcontroller? Can I Buy an MPEG2 Processor? Which One? External I/O MPEG Peripheral Processor Bus DSP Processor DSP RAM Control Processor Which Microcontroller? ARM? HC11? Audio Decode Do I need a dedicated Audio Decoder? Can decode be done on Microcontroller? System RAM How fast will my User Interface Software run? How Much can I fit on my Microcontroller?

21 Architectural Choices Flexibility Prog Mem µp Prog Mem µp Prog Mem µp Sate llite Processor MAC Unit Addr Gen General Purpose µp Dedicated Logic Satellite Satellite Processor Processor Hardware Reconfigurable Processor Software Programmable DSP Direct Mapped Hardware 1/Efficiency (power, speed) 21

22 Map Between Behavior from Architecture Transport Decode Implemented as Software Task Running on Microcontroller Rate 12 Mem 13 User/Sys Control 3 Sensor Communication Over Bus External I/O DSP Processor Front End 1 Transport Decode 2 Rate 5 Rate 9 Synch Control 4 Video Decode 6 Audio Decode/ Output 10 Frame 7 Video Output 8 MPEG Peripheral Audio Decode Processor Bus DSP RAM Control Processor System RAM Mem 11 Audio Decode Behavior Implemented on Dedicated Hardware

23 Classic A/D, HW/SW tradeoff Digital expanding De-correlate (spread spectrum) De-modulate LO e.g. Analog vs. Digital tradeoff Suppose digital limit is pushed System Chip DSP A/D Custom DSP DS 1-bit1 Modulator Dec. Filter Gen DSP 1-bit Modulator Gen DSP 1-bit Modulator RF Front End Can trade custom analog for hardware, even for software Power, area critical criteria, or easy functional modification

24 Example: Voice Mail Pager Modulation Scheme Choice (e.g. BPSK) Q f P I? e.g. De-correlate (spread spectrum) Analog vs. Digital tradeoff De-modulate? Gen DSP Design considerations cross design layers Trade-offs require systematic methodology and constraint-based hierarchical approach for clear justification