SoC Design for the New Millennium Daniel D. Gajski

Transcription

1 SoC Design for the New Millennium Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine

2 Outline System gap Design flow Model algebra System environment Vision Conclusion Copyright 2003 Daniel D. Gajski 2

3 Past, Present and Future Design Flow Capture & Simulate Describe & Synthesize Specify, Explore & Refine Specs Specs Executable Spec Functionality System Gap Algorithms SW? Algorithms SW? Algorithms Architecture Communications Network Algorithms Connectivity Protocols Design Describe Design SW/HW Design Performance Simulate Logic Simulate Logic Logic Timing Physical Physical Physical Manufacturing Manufacturing Manufacturing 1960 s 1980 s 2000 s Copyright 2003 Daniel D. Gajski 3

4 Missing Semantics: Simulation Dominated Design Flow Simulatable but not synthesizable/verifiable case X is when X1 => Finite State Machine when X2 => Table Lookup Controller Memory (VHDL, Verilog, C, SystemC, ) Copyright 2003 Daniel D. Gajski 4

5 Principles of Design Methodology Well defined specification Complete Just another model Well defined system models Several possible models Well defined semantics Formal representation Design synthesis Design decisions => transformations Automatic model generation Model verification Formally defined transformations Provable equivalence System Specification model SER Intermediate models Cycle accurate implementation model Copyright 2003 Daniel D. Gajski 5

6 Modeling as Algebra Algebra = < {objects}, {operations} > Set of all possible expressions [ex: a * (b + c)] Model Algebra = < {objects}, {compositions} > Set of all possible models [ex: ] Model Transformation t is a change in objects or composition Model refinement is an ordered set of transformations Methodology is a sequence of models and corresponding refinements Copyright 2003 Daniel D. Gajski 6

7 Model Definition Model Algebra = < {objects}, {composition rules} > Objects Behaviors (representing tasks / computations / functions) Channels (representing communication between behaviors) Composition rules Sequential, parallel, pipelined, FSM Behavior composition creates hierarchy Behavior composition also creates execution order Relations Relations define a specific model [a*((b+c)*(b-c))] Relations define the model structure (composition and connectivity) Relations? {objects} x {compositions} Copyright 2003 Daniel D. Gajski 7

8 Model Transformations (Rearrange and Replace) Rearrange object composition To distribute computation over components Replace objects Import library components Add / Remove synchronization To correctly transform a sequential composition to parallel and vice-versa Decompose abstract data structures To implement data transaction over a bus Other transformations B2 B1 a*(b+c) = a*b + a*c Distributivity of multiplication over addition analogous to B3 = B1 B2 PE1 B3 Distribution of behaviors (tasks) over components PE2 Copyright 2003 Daniel D. Gajski 8

9 Model Refinement Definition Ordered set of transformations < t m,, t 2, t 1 > is a refinement model B = t m ( ( t 2 ( t 1 ( model A ) ) ) ) Derives a more detailed model from an abstract one Specific sequence for each model refinement Not all sequences are relevant Automatic model generation Each transformation can be automated Each refined model can be automatically generated Equivalence verification Each transformation maintains functional equivalence Refinement is thus correct by construction Copyright 2003 Daniel D. Gajski 9

10 Refinement based Methodology Refinement based system level methodology Methodology := < {models}, {refinements} > Each transformation is uniquely defined Each transformation can be automatic No need for designer modeling No need for modeling languages Designers only make design decisions Copyright 2003 Daniel D. Gajski 10

11 System Synthesis through Refinement Set of models Each design decisions => one model transformation Select components / connections/ IPs Map behaviors / channels Schedule behaviors/channels Add new objects ( IF, IC, Arbiters, ) Synchronize to preserve equivalence Design is a sequence of decisions Refinement is a sequence of model transformations Synthesis = design + refinement Challenge: define the design and refinement sequences Copyright 2003 Daniel D. Gajski 11

12 System Verification through Refinement Set of models Transformations preserve equivalence Same partial order of tasks Same input/output data for each task Same partial order of data transactions Equivalent replacements All refined models will be equivalent to input model Still need to verify First model Correctness of replacements Designer Decisions Library of objects Model A Refinement Tool t1 t2 tm Model B Copyright 2003 Daniel D. Gajski 12

13 Y Chart Behavior (Function) System RTL/CA Logic Transistor Structure (Design) MoC MoC MoC Physical (Layout) MoC Copyright 2003 Daniel D. Gajski 13

14 RTL Functional Model Finite State Machine with Data (FSMD) Combined model for control and computation FSMD = FSM + DFG Implementation: controller plus datapath Op1 Op2 Op1 Op2 Op3 S1 S2 Op4 Op1 Op2 S3 Op5 Op6 Op3 FSMD model (SFSMD model) Copyright 2003 Daniel D. Gajski 14

15 RTL Structural Model Multi-pipelined data path Hardwired or programmable controller RISC or NISC style Control inputs Data memory D Q D Q Cotrol signals IR Register Selector RF Cache Bus 1 Next- Sate Logic or Address generator D Q State register or PC Output logic or Program memory SR ALU / Latch Bus 2 Bus 3 Controller Signal status Register Datapath Control outputs Datapath outputs Copyright 2003 Daniel D. Gajski 15

16 RTL Synthesis Variable binding Rescheduling Allocation Operation Binding Bus Binding FSM Synthesis RTL Control inputs Data memory D Q D Control signals IR Register Selector RF Memory Op1 Op2 Op1 Op2 Op3 S1 S3 S2 Op1 Op5 Op2 Op3 Op4 Op6 Controller Nextstate logic or Address generator Q D State Q register or PC Output logic or Program memory SR Signal status ALU / Latch Register Bus 1 Bus 2 Bus 3 Datapath FSMD model Control outputs Datapath outputs RTL/NISC structural model Copyright 2003 Daniel D. Gajski 16

17 System Functional Model Program State Machine States described by procedures in a programming language Example: SpecC! (SystemC subset?!) Proc Proc PSM model Proc Proc Proc Copyright 2003 Daniel D. Gajski 17

18 System Structural Model Arbitrary components (Proc., IP, Memory) Arbitrary connectivity (buses, protocols) System architecture Memory µprocessor IP Comp. Interface Interface Bus Interface Interface Memory Custom HW Copyright 2003 Daniel D. Gajski 18

19 System Synthesis Variable Binding Behavior Binding Channel Binding Allocation IF Synthesis Profiling Refinement System System architecture Memory µprocessor IP Comp. Proc Proc Interface Interface Proc Proc Proc Interface Interface Bus PSM model Custom HW Memory Copyright 2003 Daniel D. Gajski 19

20 System Synthesis (continued) RTL MoC Control RAM Pipeline IF FSM State IP Netlist PC IR FSMD1 FSMD2 FSMD3 FMDS4 FSMD5 Control State Datapath Mem RF IF FSM State Memory ALU HCFSMD model RTL/IS Implementation + results Copyright 2003 Daniel D. Gajski 20

21 System Level Models Models based on time granularity of computation and communication A system level design methodology is a path from model A to F Communication Cycletimed D F Approximatetimed C E A. System specification model B. Component model C. Bus-arbitration model D. Bus-functional model E. Cycle-accurate computation model F. Implementation model Cycletimed Untimed A B Untimed Approximatetimed Computation Source: Lukai Cai, D. Gajski. Transaction level modeling: An overview, ISSS 2003 Copyright 2003 Daniel D. Gajski 21

22 A: Specification Model Objects - Computation -Behaviors - Communication -Variables B2B3 B2 v2 = v1 + b*b; B1 v1 = a*a; v1 B3 v3= v1- b*b; Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions v2 v3 -TI, TOC Communication Cycletimed D F B4 v4 = v2 + v3; c = sequ(v4); - Synchronization -Notify/Wait Approximatetimed C E Cycletimed Untimed A B Untimed Approximatetimed Computation Copyright 2003 Daniel D. Gajski 22

23 B: Component-Assembly Model Objects - Computation - Proc - IPs - Memories - Communication -Variable channels PE1 B1 PE2 v1 = a*a; cv12 B2 v2 = v1 + b*b; cv11 cv2 PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC Communication Cycletimed D F A B1 v1 = a*a; v1 - Synchronization -Notify/Wait B2B3 Approximatetimed C E B2 v2 = v1 + b*b; B3 v3= v1- b*b; v2 v3 Cycletimed Untimed A B Untimed Approximatetimed Computation B4 v4 = v2 + v3; c = sequ(v4); Copyright 2003 Daniel D. Gajski 23

24 C: Bus-Arbitration Model Objects - Computation - Proc - IPs (Arbiters) - Memories - Communication - Abstract bus channels PE1 B1 PE2 v1 = a*a; B2 v2 = v1 + b*b; PE4 (Arbiter) 3 cv12 cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC Communication Cycletimed D F PE1 B1 v1 = a*a; cv11 - Synchronization -Notify/Wait Approximatetimed C E cv12 B PE3 B3 v3= v1- b*b; PE2 v3 Cycletimed Untimed A B Untimed Approximatetimed Computation B2 v2 = v1 + b*b; cv2 B4 v4 = v2 + v3; c = sequ(v4); Copyright 2003 Daniel D. Gajski 24

25 D: Bus-Functional Model Objects - Computation - Proc - IPs (Arbiters) - Memories - Communication - Protocol bus channels PE1 B1 PE2 v1 = a*a; B2 v2 = v1 + b*b; PE4 (Arbiter) 3 address[15:0] address[15:0] data[31:0] data[31:0] 1 ready 2 ack ready ack 1: master interface 2: slave interface 3: arbitor interface IProtocolSlav e PE3 B3 v3= v1- b*b; v3 B4 v4 = v2 + v3; c = sequ(v4); Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC Communication Cycletimed D F PE1 PE4 (Arbiter) C PE3 - Synchronization -Notify/Wait Approximatetimed C E B1 v1 = a*a; 3 cv12 B3 v3= v1- b*b; Cycletimed Untimed A B Untimed Approximatetimed Computation PE2 B2 v2 = v1 + b*b; cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface v3 B4 v4 = v2 + v3; c = sequ(v4); Copyright 2003 Daniel D. Gajski 25

26 E: Cycle-Accurate Computation Model Objects - Computation Communication Approximatetimed Cycletimed - Proc - IPs (Arbiters) - Memories - Wrappers - Communication - Abstract bus channels D C F E PE1 MOV r1, 10 MUL r1, r1, r1... PE2 MLA... r1, r2, r2, r PE4 S0 S1 S2 S3 4 3 cv12 cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface 4. Wrapper PE1 B1 v1 = a*a; 4 PE3 PE4 (Arbiter) 3 cv12 S0 S1 S2 S3 S4 PE3 C B3 v3= v1- b*b; Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization -Notify/Wait Cycletimed Untimed A B Untimed Approximatetimed Computation PE2 B2 v2 = v1 + b*b; cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface v3 B4 v4 = v2 + v3; c = sequ(v4); Copyright 2003 Daniel D. Gajski 26

27 address[15:0] address[15:0] data[31:0] data[31:0] ready ack ready ack e F: Implementation Model Objects - Computation - Proc - IPs (Arbiters) - Memories - Communication -Buses (wires) interrupt PE4 req S0 S1 S2 S3 PE1 MOV r1, 10 MUL r1, r1, r1... interrupt interrupt req PE3 S0 S1 S2 S3 S4 PE2 MLA... r1, r2, r2, r1... MCNTR MADDR MDATA Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Transitions -TI, TOC - Synchronization Communication -Notify/Wait Approximatetimed Cycletimed D C F E PE1 B1 D v1 = a*a; PE4 (Arbiter) 3 PE3 B3 v3= v1- b*b; PE1 E B1 v1 = a*a; PE4 (Arbiter) 3 cv12 PE3 S0 S1 Cycletimed Untimed A B Untimed Approximatetimed Computation PE2 B2 v2 = v1 + b*b; 1 2 1: master interface 2: slave interface 3: arbitor interface IProtocolSlav v3 B4 v4 = v2 + v3; c = sequ(v4); PE2 B2 v2 = v1 + b*b; cv2 1 2 cv11 1. Master interface 2. Slave interface 3. Arbiter interface 4. Wrapper 4 S2 S3 S4 Copyright 2003 Daniel D. Gajski 27

28 Refinement User Interface (RUI) Algorithm selection System structure SoC Environment Capture Validation User Interface (VUI) Compile Spec. optimization Profiling weights Profiling Profiling data Specification model Simulate Verify Allocation Beh. partitioning Scheduling / RTOS Comp. / IP attributes Comp. / IP models Arch. synthesis Design decisions Estimation Estimation results Arch. refinement Architecture model Test Simulate Verify Protocol selection Channel partitioning Arbitration Protocol attributes Protocol models Comm. synthesis Design decisions Comm. refinement Estimation Communication model Estimation results Test Simulate Verify Cycle scheduling Protocol scheduling SW/HW synthesis RTL/RTOS attributes RTL/RTOS models Impl. synthesis Design decisions Estimation Estimation results CA refinement CA model Test Simulate Verify Lang. Translators Copyright 2003 Daniel D. Gajski 28

29 Vocoder Results Experiment on GSM Vocoder design (10K lines of code) Normalized Time Simulation Speed Spec Arch Comm Impl Number of Lines Code Size Spec Arch Comm Impl Spec Arch Arch Comm Comm Impl Total Refinement Effort Modified lines 3, ,146 10,355 Manual 3~4 mons. 1~2 mons. 5~6 mons Automated User / Refine 15 mins / <1 min 5 mins/ <0.5 min 30 mins / <2 mins 9~12 mons 50 mins / <4 mins Conclusion Productivity gain >2,000X for industrial strength designs Compare 9-12 months (manual refinement) vs minutes (user decisions + automatic refinement) Enables extensive design exploration (60/day) Copyright 2003 Daniel D. Gajski 29

30 Simulation Speed & Code size JPEG Results Simulation Speed Code Size Normalized Time Number of Lines Spec Arch Comm Impl Spec Arch Comm Impl Refinement Effort Refinement Effort Modified lines Manual Automated User / Refine SpecfiArch 751 1~2 mons. 5 mins / <0.5 min ArchfiComm 492 ~1 mons. 3 mins/ <0.5 min CommfiImpl 1,278 3~4 mons 20 mins / <1 mins Total 2,521 5~7 mons 28 mins <2mins Compare 5-7months (manual refinement) vs. 28 minutes (user decisions) + 2 minutes (automatic refinement) Copyright 2003 Daniel D. Gajski 30

31 Conclusion New design flow paradigm based on SER methodology Semantics before syntax (language does not matter) Model algebra before semantics System verification, synthesis, modeling simplified SW = HW = computation is the inevitable truth SoC environment gives 1000X productivity gain Challenge: Define models, refinements, methodology Copyright 2003 Daniel D. Gajski 31