INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

Transcription

1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 17 Title: - Objectives and Operation Summary: secondary memory; ; Address translation (hierarchy tables and inverted tables). 2010/2011 Nuno.Roma@ist.utl.pt

2 Architectures for Embedded Computing : Objectives and Operation Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 32 Previous Class In the previous class... Primary Memory: Technologies; DRAM memories operation; Memory planes; Primary memory access optimization. Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 32

3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 32 Summary Today: : secondary memory; ; Address translation: Hierarchy tables; Inverted tables. Bibliography: Computer Architecture: a Quantitative Approach, Sections C.4-C.5 and Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 32

4 Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 32 Memory Hierarchy µp Cache Memory Hard Disk Registers Each level includes a subset of the data that is stored in the next higher level. Price per Megabyte: Cache: 3 e DRAM: 0.6 e Disk: e Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 32

5 Control Bus c Address Bus µp Memory m Data Bus n Memory Managment Unit (MMU): Responsible for the translation between virtual addresses and physical addresses. Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 32 Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 32

6 Increase of the memory space from the program point of view: Automatic overlaying mechanism; Only the memory that is really needed is instantiated; Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 32 Increase of the memory space from the program point of view: Automatic overlaying mechanism; Only the memory that is really needed is instantiated; Memory protection between the programs; Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 32

7 Increase of the memory space from the program point of view: Automatic overlaying mechanism; Only the memory that is really needed is instantiated; Memory protection between the programs; Memory sharing mechanism between programs; Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 32 Increase of the memory space from the program point of view: Automatic overlaying mechanism; Only the memory that is really needed is instantiated; Memory protection between the programs; Memory sharing mechanism between programs; Program relocation within memory: The same program can be executed in any memory position; Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 32

8 Increase of the memory space from the program point of view: Automatic overlaying mechanism; Only the memory that is really needed is instantiated; Memory protection between the programs; Memory sharing mechanism between programs; Program relocation within memory: The same program can be executed in any memory position; Decrease of programs start-up time: It is not necessary any change to the program compilation, independently of the memory position where the program will stay resident. Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 32 Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 32

9 Segmented Memory Each process uses a set of segments (code, data, stack) with variable dimension. The Segment table keeps, for each segment, information about: Starting address, at physical memory, or indication that such segment is currently not in memory; Dimension; Protection; Each memory reference requires: Segment index, within this table; Offset, within this segment (logic address) 2 words!!! Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 32 Paged Memory Memory is divided in fixed-sized blocks, denoted as pages. Each process uses a given set of pages. The page table keeps, for each page used by the process, information about: Physical page index; Protection. Each entry in this table is usually denoted as Page Table Entry (PTE). The virtual address contains: Virtual page index Offset Each memory reference only requires one address: 1 word!!! Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 32

10 Paged Memory Example: Pages with 4k(= 2 12 ) bytes, Physical memory with 256M(= 2 28 ) bytes, Virtual memory with 32G(= 2 35 ) bytes. Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 32 Paged Memory Example: Pages with 4k(= 2 12 ) bytes, Physical memory with 256M(= 2 28 ) bytes, Virtual memory with 32G(= 2 35 ) bytes. Hence... the physical memory is composed of 64k(= 2 16 ) (10000h) pages and the virtual memory has 8M(= 2 23 ) (800000h) pages. 7FFFFFh 7FFFFEh. FFFFh FFFFh FFFEh. FFFEh. 0h 0h Physical Address Virtual Address Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 32

11 Comparison Between Segmented and Paged Memory Paged Words per reference 1 2 Segmented Visible to the programmer no may be Block substitution easy problematic Memory use efficiency internal fragmentation external fragmentation Efficient disk traffic yes not always Table dimension big small There are hybrid schemes, where the segments are paginated. Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 32 Objective: fast and functional Segmented: logic address = {segment index, offset} segment base = segments table [segment index] physical address = segment base + offset Several checks to the range and access rights are done in parallel. Paged: virtual address = {virtual page index offset} physical page index = page table [virtual page index] physical address = physical page index offset Access rights are done in parallel. Fault: The result of a query to the segments table / page table indicates that such segment / page currently is not in primary memory. Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 32

12 Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 32 : Paged Memory Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 32

13 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Just as cache accommodates a subset of primary memory positions, the primary memory accommodates a subset of virtual memory positions. Block? Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 32 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Just as cache accommodates a subset of primary memory positions, the primary memory accommodates a subset of virtual memory positions. Block = page Dimension? Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 32

14 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Just as cache accommodates a subset of primary memory positions, the primary memory accommodates a subset of virtual memory positions. Block = page Dimension: Usually large, to increase the efficiency when acceding the disk (also reduces the dimension of translation tables). However, the bigger it is, the greatest is the potential memory waste (on average, 50% of the page dimension). Typical values are 4k and 8k bytes. Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 32 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Just as cache accommodates a subset of primary memory positions, the primary memory accommodates a subset of virtual memory positions. Block = page Dimension: Usually large, to increase the efficiency when acceding the disk (also reduces the dimension of translation tables). However, the bigger it is, the greatest is the potential memory waste (on average, 50% of the page dimension). Typical values are 4k and 8k bytes. Where can a given block be placed in memory (i.e., set-associativity)? Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 32

15 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Just as cache accommodates a subset of primary memory positions, the primary memory accommodates a subset of virtual memory positions. Block = page Dimension: Usually large, to increase the efficiency when acceding the disk (also reduces the dimension of translation tables). However, the bigger it is, the greatest is the potential memory waste (on average, 50% of the page dimension). Typical values are 4k and 8k bytes. Where can a given block be placed in memory (i.e., set-associativity): In any place of the memory (full associativity). Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 32 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Substitution policy? Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 32

16 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Substitution policy: LRU Software managed (OS) - allows more sophistication. Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 32 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Substitution policy: LRU Software managed (OS) - allows more sophistication. Write policy? Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 32

17 Cache - Primary Mem. vs Primary Mem. - Secondary Mem. Substitution policy: LRU Software managed (OS) - allows more sophistication. Write policy: Write-back: the disk access penalty is to high... Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 32 Mean Access Time Mean access time: t access = t h + p m t p t h < 150 clock cycles. t p can be as high as 10,000,000 clock cycles! Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 32

18 Mean Access Time Mean access time: t access = t h + p m t p t h < 150 clock cycles. t p can be as high as 10,000,000 clock cycles! Why does this work? Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 32 Mean Access Time Mean access time: t access = t h + p m t p t h < 150 clock cycles. t p can be as high as 10,000,000 clock cycles! Why does this work? Because p m may be as low as %! t access = = 160 Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 32

19 Mean Access Time Mean access time: t access = t h + p m t p t h < 150 clock cycles. t p can be as high as 10,000,000 clock cycles! Why does this work? Because p m may be as low as %! t access = = 160 Capacity misses: Few! The context corresponding to the set of programs under execution is usually smaller than the memory dimension (otherwise... thrashing). Conflict misses: Few! Full associative allocation policy. Compulsory misses: Usually, the most prevalent. Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 32 Pages Table Dimension One common problem in paging systems is the dimension of the page table that is required to translate the addresses. Must be allocated in a contiguous region at physical memory. Example: Virtual space with 2 32 bytes, Pages with 4k(= 2 12 ) bytes, Descriptor with D = 4 bytes: Table with 2 20 entries (4M bytes). Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 32

20 Hierarchical Page Tables One common solution to this problem is to implement the translation with a hierarchy of translation tables. Virtual address is seen as: Level 1 index Level 2 index Level n index Offset Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 32 Hierarchical Page Tables Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 32

21 Hierarchical Page Tables How much space is required to store the tables? Example: 2 levels, virtual address with 2 32 bytes and pages with 4k(= 2 12 ) bytes Level 1 index Level 2 index Offset Directory has 1024 entries. Each level 2 table has 1024 entries. The total is 1M entries, corresponding to 4M bytes, just as before! Only the directory must be always in memory: the higher level tables may be at disk! Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 32 Hierarchical Page Tables How much space is required to store the tables? Example: 2 levels, virtual address with 2 32 bytes and pages with 4k(= 2 12 ) bytes Level 1 index Level 2 index Offset Directory has 1024 entries. Each level 2 table has 1024 entries. The total is 1M entries, corresponding to 4M bytes, just as before! Only the directory must be always in memory: the higher level tables may be at disk! Usually, it is adopted: Page tables with the same dimension as the tables; Only the pages under use have to be in primary memory; Only the required pages are instantiated. Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 32

22 Hierarchical Page Tables How much space is required to store the tables? Example: 2 levels, virtual address with 2 32 bytes and pages with 4k(= 2 12 ) bytes Level 1 index Level 2 index Offset Directory has 1024 entries. Each level 2 table has 1024 entries. The total is 1M entries, corresponding to 4M bytes, just as before! Only the directory must be always in memory: the higher level tables may be at disk! Usually, it is adopted: Page tables with the same dimension as the tables; Only the pages under use have to be in primary memory; Only the required pages are instantiated. What happens if it is not possible to divide in equal-sized levels? Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 32 Hierarchical Page Tables How much space is required to store the tables? Example: 2 levels, virtual address with 2 32 bytes and pages with 4k(= 2 12 ) bytes Level 1 index Level 2 index Offset Directory has 1024 entries. Each level 2 table has 1024 entries. The total is 1M entries, corresponding to 4M bytes, just as before! Only the directory must be always in memory: the higher level tables may be at disk! Usually, it is adopted: Page tables with the same dimension as the tables; Only the pages under use have to be in primary memory; Only the required pages are instantiated. What happens if it is not possible to divide in equal-sized levels? No Problem! Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 32

23 Inverted Tables Address translation based in hash tables: A given hash function H(x) is applied to the virtual address to find out a particular queue of descriptors composed by pairs virtual page - physical page, whose corresponding virtual addresses lead to the same value of the hash function H(x) collisions. The required physical address may (or may not) be present in that queue of descriptors. Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 32 Inverted Tables The inverted table translation system is implemented by using two tables: Entries Table: for each value of the hash function indicates the starting address of the corresponding queue. Collision Table: contains a list of physical pages whose corresponding virtual address give rise to the same value of the hash function H(x). Each entry has information about: Virtual page number; Protection; Pointer to the next entry. The entry that contains the virtual page number corresponding to the virtual address under translation corresponds to the index of the desired physical page. Dimension of the tables is determined by the number of physical pages and does not depend of the virtual space size. Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 32

24 Inverted Tables Address translation based on inverted tables: Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 32 Inverted Tables Example: Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 32

25 Inverted Tables Tables dimension: Collision table has as many entries as the number of installed physical pages: Each entry has the following dimension: (V log 2 P ) + (F log 2 P )+protection bits Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 32 Inverted Tables Tables dimension: Collision table has as many entries as the number of installed physical pages: Each entry has the following dimension: (V log 2 P ) + (F log 2 P )+protection bits Entries table is dimensioned to achieve a certain performance level: N: rows in the entries table; M: rows in the collision table (= physical pages) Load factor: α = M N Mean number of searched elements: S = 1 + α 2 Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 32

26 Inverted Tables Hash function: should assure an uniform distribution of virtual pages in the several queues Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 32 Inverted Tables Hash function: should assure an uniform distribution of virtual pages in the several queues Possible solution: Use the least significant bits of the virtual page index. Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 32

27 Inverted Tables Hash function: should assure an uniform distribution of virtual pages in the several queues Possible solution: Use the least significant bits of the virtual page index. Example: Virtual memory with 1T (=2 40 ) bytes, physical memory with 512M (=2 29 ) bytes and pages with 8k (=2 13 ) bytes. It is required that, on average, only 2 descriptors are analyzed. Which bits should be used by the hash function? Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 32 Inverted Tables Hash function: should assure an uniform distribution of virtual pages in the several queues Possible solution: Use the least significant bits of the virtual page index. Example: Virtual memory with 1T (=2 40 ) bytes, physical memory with 512M (=2 29 ) bytes and pages with 8k (=2 13 ) bytes. It is required that, on average, only 2 descriptors are analyzed. Which bits should be used by the hash function? M = # physical pages = = S = 1 + α 2 with α = M N, it comes: 2 = N N = 215 Among the 40 bits of the virtual address, the 13 least significant bits are used as the offset within the page. The following 15 bits are used by the hash function: bits 13 to 27. Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 32

28 Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 32 Virtual memory: Very large addressing spaces; Translation Lookaside Buffer (TLB); Virtual caches; Parallel access to the cache and TLB. Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 32