INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing
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1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 04 Title: Summary: ; ; Compilers Role; MIPS Logic Architecture. 2010/2011 Nuno.Roma@ist.utl.pt
2 Architectures for Embedded Computing Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 35 Previous Class In the previous class... Processor Logic Architecture: Logic Architecture Architectures Classification Assembly Addressing Modes Operands Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 35
3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 35 Summary Today: : Compilers Role MIPS Logic Architecture Bibliography: Computer Architecture: a Quantitative Approach, Appendix B Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 35
4 Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 35 Type ALU Transfer Control System Floating point String Examples integer arithmetic and logic operations: addition, subtraction, multiplication, division, and, or, shift load, store, move branches, jumps, procedure call and return operating system calls; virtual memory management addition, subtraction, multiplication, division, comparison string processing: copy, comparison, search Graphics pixel and vertex operations; compression/decompression operations Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 35
5 80x86 Instruction Statistics Rank Instruction % Total Executed 1 load 22% 2 conditional branch 20% 3 compare 16% 4 store 12% 5 add 8% 6 and 6% 7 sub 5% 8 move reg-reg 4% 9 call 1% 10 return 1% Total: 96% Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 35 Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 35
6 Represent a significant part of the executed instructions; Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 35 Represent a significant part of the executed instructions; Absolute jumps vs relative branches; Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 35
7 Represent a significant part of the executed instructions; Absolute jumps vs relative branches; Number of bits used for the address field; Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 35 Represent a significant part of the executed instructions; Absolute jumps vs relative branches; Number of bits used for the address field; Tested conditions: Flags; Generic register; Comparison is included in the jump/branch instruction. Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 35
8 Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 35 Assembly Machine Language ADD R1,R2,# Fields: Opcode: operation code - unique for each Assembly instruction; Operands: specification of the operands; Addressing Mode: specify how the information included in the operands field should be interpreted. Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 35
9 Addressing Modes: Mode Example Interpretation Register Add R4,R3 Regs[R4] Regs[R4]+Regs[R3] Immediate Add R4,#3 Regs[R4] Regs[R4]+3 Displacement Add R4,100(R1) Regs[R4] Regs[R4]+Mem[100+Regs[R1]] Reg Indirect Add R4,(R1) Regs[R4] Regs[R4]+Mem[Regs[R1]] Indexed Add R4,(R1+R2) Regs[R4] Regs[R4]+Mem[Regs[R1]+Regs[R2]] Direct Add R4,(1001) Regs[R4] Regs[R4]+Mem[1001] Mem Indirect Add Regs[R4] Regs[R4]+Mem[Mem[Regs[R3]]] Autoincrement Add R1,(R2)+ Regs[R1] Regs[R1]+Mem[Regs[R2]] Regs[R2] Regs[R2]+d Autodecrement Add R1,-(R2) Regs[R2] Regs[R2]-d Regs[R1] Regs[R1]+Mem[Regs[R2]] Scaled Add R1,10(R2)[R3] Regs[R1] Regs[R1]+ Mem[10+Regs[R2]+Regs[R3]*d] Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 35 Variable format (CISC): the executable binary is more compact, since each instruction only uses the space that is strictly required. Opcode Mode 1 Operand 1 Mode n Operand n Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 35
10 Variable format (CISC): the executable binary is more compact, since each instruction only uses the space that is strictly required. Opcode Mode 1 Operand 1 Mode n Operand n Fixed format (RISC): Much simpler instruction decoding process. Opcode Operand 1 Operand 2 Operand 3 Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 35 Variable format (CISC): the executable binary is more compact, since each instruction only uses the space that is strictly required. Opcode Mode 1 Operand 1 Mode n Operand n Fixed format (RISC): Much simpler instruction decoding process. Opcode Operand 1 Operand 2 Operand 3 Code compression in RISCs: Two possible instruction formats: 16 and 32 bits. Binary executable in compressed format and decompressed by hardware when the instruction is fetched from memory. Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 35
11 Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 35 MIPS processor is a good example of the RISC paradigm: Load-store architecture; General-purpose registers with 64 bits: 32 integer registers (Rn); 32 floating-point registers (Fn); Two addressing modes: immediate and displacement; Integer operations (8, 16, 32 e 64 bits) and floating-point operations (IEEE 754); Fixed-length encoding (although it allows some variations to achieve a more compact binary executable). Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 35
12 MIPS Encoding Formats 32-bits instructions with 3 possible formats: Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 35 MIPS Addressing Modes Immediate: specification of the constants DADD R2,R1,#100 ; R2 R1+100 Displacement: local variables LD R2,64(R1) ; R2 Mem[64+R1] Indirect Register: addressing using a pointer LD R2,0(R1) ; R2 Mem[R1] Direct or Absolute: access to static variables LD R2,48(R0) ; R2 Mem[48] Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 35
13 MIPS : Load-Store Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 35 MIPS : ALU Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 35
14 MIPS Conditional branches: there isn t any flags!!! BEQZ R1,target ; if(r1=0) then PC target BNEQZ R1,target ; if(r1 0) then PC target Routine calls: does not use the stack!!! JAL routine ; Regs[31] PC+4, PC routine Return from a routine? Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 35 MIPS Conditional branches: there isn t any flags!!! BEQZ R1,target ; if(r1=0) then PC target BNEQZ R1,target ; if(r1 0) then PC target Routine calls: does not use the stack!!! JAL routine ; Regs[31] PC+4, PC routine Return from a routine? JR R31 Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 35
15 MIPS Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 35 MIPS Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 35
16 MIPS Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 35 Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 35
17 to MIPS processor Operations; Conditions; Routine calls; Data: Scalars; Vectors; Matrices; Structures. Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 35 : Operations Precision of the operations: short a,b,c;. a=b+c; LH R1,2(R12) ; b LH R2,4(R12) ; c HADD R3,R1,R2 SH R3,0(R12) ; a Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 35
18 : Operations Precision of the operations: short a,b,c;. a=b+c; long a,b,c;. a=b+c; LH R1,2(R12) ; b LW R1,4(R12) ; b LH R2,4(R12) ; c LW R2,8(R12) ; c HADD R3,R1,R2 ADD R3,R1,R2 SH R3,0(R12) ; a SW R3,0(R12) ; a Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 35 : Control if then else for while repeat until switch There is one condition that is evaluated and, as result of such evaluation, one specific block of code is executed. Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 35
19 : Control short k,n; LH R1,0(R12) ; k. LH R2,2(R12) ; n if( k < n) HSUB R3,R1,R2 Block A BLT R3,BlockA else BlockB: Block B. J BlockA:. EndIF: EndIF Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 35 : Scalars short i,j; D. char c; C c double f; B j 1 A j 0 9 i 1 8 i 0 7 f 7 6 f 6 5 f 5 4 f 4 3 f 3 2 f 2 1 f 1 0 f 0 Base Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 35
20 : Vectors char a[50]; 4. 3 a[3] 2 a[2] 1 a[1] 0 a[0] Base Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 35 : Vectors char a[50]; 4. 3 a[3] 2 a[2] 1 a[1] 0 a[0] Base short a[50]; 5. 4 a[2] 0 3 a[1] 1 2 a[1] 0 1 a[0] 1 0 a[0] 0 Base Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 35
21 : Matrices char b[2,3]; 6. 5 b[1,2] 4 b[1,1] b[0,0] b[0,1] b[0,2] 3 b[1,0] b[1,0] b[1,1] b[1,2] 2 b[0,2] 1 b[0,1] 0 b[0,0] Base Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 35 : Matrices short b[2,3]; A. 9 b[1,1] 1 8 b[1,1] 0 b[0,0] b[0,1] b[0,2] 7 b[1,0] 1 b[1,0] b[1,1] b[1,2] 6 b[1,0] 0 5 b[0,2] 1 4 b[0,2] 0 3 b[0,1] 1 2 b[0,1] 0 1 b[0,0] 1 0 b[0,0] 0 Base Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 35
22 : Access to Data To access element a[i] of a given vector a[n], with 0 i < n, the memory address is computed by: address = base + dim type i Prof. Nuno Roma ACE 2010/11 - DEI-IST 33 / 35 : Access to Data To access element a[i] of a given vector a[n], with 0 i < n, the memory address is computed by: address = base + dim type i To access element a[i,j] of a given matrix a[n,m], with 0 i < n and 0 j < m, the memory address is computed by: address = base + dim type (i m+j) Prof. Nuno Roma ACE 2010/11 - DEI-IST 33 / 35
23 Prof. Nuno Roma ACE 2010/11 - DEI-IST 34 / 35 Pipeline processing: Analysis of the instruction execution Implementation Performance analysis Pipeline Hazards: Structural Data Control Prof. Nuno Roma ACE 2010/11 - DEI-IST 35 / 35
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