An Efficient DesignofRadix-8 Sum-Modified BoothRe-Coder for Fused Add-Multiply Operator

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1 An Efficient DesignofRadix-8 Sum-Modified BoothRe-Coder for Fused Add-Multiply Operator 1 M.LAKSHMIDEEPTHI,M.TECH,VLSI, 2 K. BALA S RI NI V A S A INSTITUTE OF TECHNOLOGY AND SCINCES A N DHR A PRAD ESH Mailid:aru n 14 m u g m a il. co m Under the guidance of K.BALA M.TECH Abstract- Thisproposedmethodispurelybasedonmodifiedr ecoding techniques for booth recoding in DSPapplication. The proposed method implements a newly designed recoding technique for modified booth recoding. This technique to implement the direct recoding of the multi plie rinits Sum Modi fiedbooth(s- MB)form.TheproposedS-MB algorithm is structured, simple and can beeasily modi fied inorder to apply either in signed or unsignednumbers,which compriseof odd or even number of bits. Thus Fused Add- Multiply operator is optimized to increase the performance of complex arithmetic operation. It is optimized with three different recodingschemess-mb1,s-mb2,s MB3. Thesum to modi fied techni que isi mplementedbyradix- 8R ec o rd e r.the proposedtechnique yields considerable reductions in terms of critical delay, hardware complexity and power consumptionofthefamunit. KEY WORDS: Digital Processing, Fast Fourier Transform I.INTRODUCTION Digital signal processing(dsp) are widely used in the modern consumer electronics. Typical DSP applications carry out alarge number of arithmetic operation sas the irimple mentation is based on computationally intensive kernels, such as FastFourierTransform(FFT),DiscreteCosineTransf orm(dct),finiteimpulseresponse(fir) filters and signals convolution. The performance of the DSP is measuredin terms oftheamount of hardwareand resourcesrequired(i,e.,spaceorarea);thespeedofthee xecution,whichdependsonboththethroughputandcl ock rate ;and the amount of the power dissipationor the totalenergy required to perform agiven task. The performance of the DSPapplicationcanbeaffectedbyalargenumberofari thmeticoperation which re quireslargearchitecture. Recent research activit ies in the field of arithmetic optimization have shown that the design of arithmetic Co mponent scombiningoperationswhichsharedata,canleadtosig nificantperformanceimprovements.basedon the observation that an addition can often be sub sequent to a multiplication (e.g.,in s ymmetric FIRfilters),the Multiply -Accumulator (MAC) and Multiply-Add (MAD) units were introduced for efficient implementations of DSP algorithms compared to the conventional ones. Several architectures have been proposed to optimize the performance of the MAC operation interm so fare a occupation,critical path delay or power consumption.mac component sincre a seethe flexibility of DSPdatapath s ynthesis as alarge set of arithmetic operations can be efficiently mapped onto them. Exceptthe MAC/MAD operations, many DSP applications are based on Add-Multiply(AM)operations. Thestraightforwarddesignof the AM unit, by first allocating an adder and then driving its output to the input of a multiplier, increases significantly both are a and criticalpathdelayofthecircuit. The proposed system optimize the design of AM operators, by introducing fusion techniques which is based on the direct recoding of the sum of two numbersinitsmodifiedbooth(mb)form.thedirectre coding of the sum of two numbers initsmbformleadstoamoreefficient implementation ofthefusedadd-multiply (FAM) unit comparedtotheconventionalone.thesum-modified Booth(S-MB)recoding techniquesareefficiently usedto implement the direct recoding of the sum of two numbers in its MB form. The proposed technique yields considerable reductions intermsofcrit icaldelay,hard wareco mplexityandpow erconsumptionofthefamunit. IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 1

2 A. Blockdiagramofproposedsystem- II.PROPOSEDSYSTEM Figure1.Blockdiagram FAMdesignwithsum-modifiedbooth(S- MB)recoding technique reduce the number of partial productsand increasing speed of calculation.the FAM techniquewhichdecreasesthe crit ical path delay and reduces area and power consumption. The proposed S-MB algorithm isstructured,simple and can bee a inorder to be appliedeitherinsigned(in2 scomp lementrepresentat ion)orunsignednumbers,whichco mpriseofoddorev en number of bits. The carry select a ddercomes in the category of conditional sum adder. Conditional sum adderwork son some condition. Sum and carry are calculated by assuminginput carryas 1and0 prior the input carry comes. Whenactual carryinputarrives,theactualcalculatedvaluesofsuma ndcarryareselectedusingamult iplexer.theconventi onal carry select adder consistsofnbitadderforthelowerhalfofthebitsi.e.leastsignificant bits(lsb s)andforthe upper half i.e.most significant bits (MSB s) twon-bit adders. In MSB adder s one adder assumes carry input as one for performing addition and another assumes carry input as zero. The carry out calculated from the laststage i.e.least significant bit stage s used to select the actual calculated values of output carry and sum. The selection is done by using a multiplexer. This technique of dividing adder in two stages increases the are autilization but addition operation fastens. The basic block diagram for carry select adderisshowninfigure2.carry Select Adders(CSLA) is one of the fastest adder s use dinmany data-processing process or stoperform fast arithmetic functions. The carry select adder partitions the adder into several groups,each of which performs two additions in parallel. B. ConceptDescription- AnoptimizeddesignoftheAMoperatorisbasedo nthefusionoftheadderandthembencodingunitintoa singledatapathblock(fig.1)b ydirectrecodingofthes umy=a+btoitsmbrepresentation. The fused Add- Multiply (FAM) component containsonly oneadderattheend(finaladderoftheparallelmu lt iplier ).Asaresult, significant area savings are observedandthecriticalpathdelayoftherecodingproc essisreduced.famdesignisa new technique for direct recoding of two numbers in the MB representation of the irsum. C. S-MBRecoder- Figure2.BlockDiagramofCSA Twocopiesofripplecarryadderactascarryevaluationblockperselectstage.One copy evaluates thecarry chain assuming the block carry-inis zero, while the other assumes it to Thesumtomodifiedboothrecoderisembeddedwi thadderand encoder block. It is structured with half be one. Once the carry signals are finally adders andfull adders where the adder and computed,thecorrectsumandcarry-out signals will encoding is done insingle structure.this fused be simp ly selected by a set of multiplexers. The4- block reduce sthearea of the FAMdesign. This S- bitadder blockis RCA. Carry Select Adders MBR ecoderblock is implemented by S-MBR actsasacompro misebetweenasmallareabutlongerdel ecoder technique. ayripplecarryadder and alargearea with shorter delay CarryLook-aheadAdder. D. CSATree- IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 2

3 S-MB1Recoding Scheme E. CLA Adder S-MB2Recoding Scheme Acarry-look-ahead adder (CLA) is a type of adder used in digital logic.acarry-look-ahead S-MB3Recoding Scheme adder improves speed by reducing the amount of time required to determine carry bits. The carrylook-a TheseS-MB1,S-MB2,S-MB3 head adder calculates one or RecodingTechniquesareimplemented byradix- morecarrybitsbeforethesum,whichreducesthewaitti metocalculatetheresultofthelargervaluebits.most otherarithmet icoperations,e.g.mult iplicationanddiv 8ecodingTechniques. G. Radix-8BoothEncoding isionareimplementedusing severaladd /subtract steps. Thus, improving the speed of addition will improve the speed of all other arithmetic operations. Accordingly,reducingthe carry propagation delay of adders is ofgreatimportance.differentlog icdesignapproaches have been employed to overcome the carry propagation problem. Onewidelyusedapproach employs theprinciple ofcarry-look-ahead solvesthisproblemb ycalculat ingthecarrys ignalsina dvance,basedontheinputsignals.thistypeofaddercir cuit iscalledascarry-look-aheadadder(claadder). Itisbasedonthefactthatacarrysignalwillbegeneratedint wocases: whenbothbitsaiandbiare1,or whenoneof thetwobitsis1andthecarryin(carryofthepreviousstage)is1. Booth algorithm (MB) is ap revalent form used in multiplication and it is a powerful algorithm for signed number multiplication. Ittreatsboththepositive andnegative number uniformly. Itsmain advantageisthatit reducesbyhalfthenumberofpartialproductsinmult ipl ication comparing toan yotherradix- 4representation. Radix-8booth encoder performstheprocessesofencodingthemult iplicandba sedonthemultiplierbits.radix-8 Booth recoding isthesamealgorith masthatofradix- 4.Rad ix8takequartetsofbitsinsteadoftriplets.thenu mberofpartialproductcanbereduceston/3b ymeansof Radix8boothencodingwherenisthenumberofmult ip lierb its.eachquartetiscodedasasigneddigitusingtab le1. Figure3.BlockD iagramofcla Y i M u Radi x- Par tial Y Y Y M 0 i i i ult M Mx Mx Mx F. S-MBRecodingTechniques Bothth econventiona land signed Has and FAs isusedtodesignthethreenewalternativeschemesofth es-mb recoding technique by radix- 8Boothencoding.Eachofthethreeschemescanbeeasi ly applied in either signed(2 s complementrepresentation)orunsignednumberswhi chconsistofoddorevennumberofbits.considerthatbo thinputsaandbarein2 scomp lementformandconsist of2kbitsincaseofevenor2k+1bitsincaseof oddbitwidth.targetingtotransformthesumofaandb(y=a +B)inits M B representation.the three S-MB recoding schemes are: IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 3

4 Mx Mx Mx Mx Mx Mx Mx Mx Mx Mx Mx Mx0 F H. PartialProductGenerator Table1:Radix-8 BoothEncoding Aproductformedb ymultiplyingthemultiplicandbyo nedigitofthemultiplierwhenthemultiplierhasmore than onedigit. Partial products are used as intermediate steps in calculating larger products.partial product generatorisdesignedtoproducetheproductbymultiplyin gthemultiplicandmby0,1,-1,2,-2,-3,-4,3,4.for productgenerator,multiplybyzeromeansthemultiplica ndismultipliedby 0.Multiplyby 1 meanstheproduct stillremainsthesameasthemultiplicandvalue.multiplyb y -1 meansthattheproductisthetwo scomplement formofthenumber.multiplyby 2 istoshiftleftonebitth etwo scomplementofthemultiplicandvalueand multiplyb y 2 meansjustshiftleftthemultiplicandbyon eplace..multiplyby -4 istoshiftlefttwobitthetwo s complementofthemultiplicandvalueandmultiply by 2 meansjustshiftleftthemultiplicandbytwoplace. Figure5..OutputOfS-MB1Odd III.EXPERIMENT ANDRESULT Figure4.OutputOfS-MB1Even Figure6.Outputof S-MB2Even IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 4

5 Figure7.Outputof S-MB2Odd Figure8.OutputofS-MB3Even Figure9.OutputofS-MB3Odd Figure10.ComparisonofDelaywithDi fferents-mbtechnique IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 5

6 IV.CO NCL USI O N TheFusedAdd-Multiply peratoris optimized to increasetheperformanceofcomplexarithmeticoperatio n.itis optimized withthreedifferentrecodingschemess- MB1,S-MB2,S-MB3.Thisproposed systemimplement the modified booth reconding techniquesinradix- 8toachievethepowerconsumption.Theproposedtechni queyieldsconsiderablereductionsintermsofcriticaldela y,hardwarecomplexit yandpowerconsumptionofthefa Munit. REFERENCES [1] An Optimized Modified Booth Recoderfor EfficientDesignoftheAdd-Multiply Operator Kostas Tsoumanis, Student Member, IEEE, SotirisXydis,ConstantinosEfstathiou,NikosMoschop oulos, andkiamalpekmestziaieeetransactionsoncircuitsan dsystems i:regular papers,vol.61,no.4,april2014 [2] Amaricai,M.Vladutiu,andO.Boncalo, Designissuesandi mplementation forfloating-pointdivideaddfused, IEEETrans.CircuitsSyst. II Exp.Briefs,vol.57,no.4,pp ,Apr [3] E.E.SwartzlanderandH.H.M.Saleh, FFTimplementa tion withfusedfloating-point operations, IEEETrans.Comput.,vol.61,no.2, pp ,Feb [4] J.J.F.Cavanagh,DigitalComputerArithmetic.NewYork:M c Graw-Hill,1984. [5] S.Nikolaidis, E.Karaolis, ande.d.kyriakis- Bitzaros, Estimation ofsignaltransition activity infirfiltersimplemented byamac architecture, IEEETrans.Comput.-Aided Des.Integr.CircuitsSyst.,vol.19,no.1,pp ,Jan [6] O.Kwon,K.Nowka,andE.E.Swartzlander, A16- bitby16-bitmac designusingfast5:3compressor cells, J.VLSISignalProcess. Syst.,vol.31,no.2,pp.77 89,Jun [7] L.-H.Chen,O.T.-C.Chen,T.-Y.Wang, andy.- C.Ma, Amultiplication-accumulationcomputation unitwithoptimized compressors and minimized switching activities, inproc.ieeeint,symp.circuitsandsyst.,k obe,japan,2005,vol.6, pp [8]Y.-H.SeoandD.-W.Kim, AnewVLSIarchitecture ofparallel multiplier accumulatorbasedonradix-2 modified Boothalgorithm, IEEETrans.VeryLargeScaleIntegr.(VLSI)Syst.,vol.18,no.2,pp ,Feb [9] A.PeymandoustandG.deMicheli, Usingsymbolicalgebra inalgorithmic leveldspsynthesis, inproc.designautomation Conf.,Las Vegas,NV,2001,pp Lakshmi deepthi studying M.tech K. BALA ASSOCIATE PROFESSOR. SRINIVASA INSTITUTE OF TECHNOLOGY AND SCIENCE. IJCSIET-ISSUE5-VOLUME3-SERIES1 Page 6