Section 19. Inter-Integrated Circuit (I 2 C )

Transcription

1 Section 19. Inter-Integrated Circuit (I 2 C ) HIGHLIGHTS This section of the manual contains the following major topics: 19.1 Overview I 2 C-Bus Characteristics Control and Status Registers Enabling I 2 C Operation Communicating as a Master in a Single-Master Environment Communicating as a Master in a Multi-Master Environment Communicating as a Slave Connection Considerations for I 2 C-Bus Module Operation During PWRSV Instruction Peripheral Module Disable (PMD) Registers Effects of a Reset Register Maps Design Tips Related pplication Notes Revision History Inter-Integrated Circuit (I 2 C ) 2008 Microchip Technology Inc. DS70195B-page 19-1

2 dspic33f Family Reference Manual 19.1 OVERVIEW The Inter-Integrated Circuit (I 2 C) module is a serial interface useful for communicating with the other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, /D converters, etc. The I 2 C module can operate in any of the following I 2 C systems: s a slave device s a master device in a single-master system (slave may also be active) s a master/slave device in a multi-master system (bus collision detection and arbitration available) The I 2 C module contains independent I 2 C master logic and I 2 C slave logic, each generating interrupts based on their events. In multi-master systems, the software is simply partitioned into master controller and slave controller. When the I 2 C master logic is active, the slave logic also remains active, detecting the state of the bus and potentially receiving messages from itself in a single-master system or from other masters in a multi-master system. No messages are lost during multi-master bus arbitration. In a multi-master system, bus collision conflicts with other masters in the system are detected, and the module provides a method to terminate and then restart the message. The I 2 C module contains a Baud Rate Generator. The I 2 C Baud Rate Generator does not consume other timer resources in the device. Key features of the I 2 C module include the following: Independent master and slave logic Multi-master support which prevents message losses in arbitration Detects 7-bit and 10-bit device addresses with configurable address masking in Slave mode Detects general call addresses as defined in the I 2 C protocol Bus Repeater mode, allowing the module to accept all messages as a slave regardless of the address utomatic SCLx clock stretching provides delays for the processor to respond to a slave data request Supports 100 khz and 400 khz bus specifications Supports the Intelligent Platform Management Interface (IPMI) standard Figure 19-1 illustrates the I 2 C module block diagram. DS70195B-page Microchip Technology Inc.

3 Inter-Integrated Circuit (I 2 C ) Figure 19-1: I 2 C Block Diagram Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSB SDx Match Detect ddress Match Write I2CxMSK Write Read I2CxDD Read Start and Stop Bit Detect Write Start and Stop Bit Generation I2CxSTT Collision Detect cknowledge Generation Control Logic I2CxCON Read Write Read Clock Stretching Write 19 Shift Clock I2CxTRN Reload Control LSB Read Write Circuit (I 2 C ) Inter-Integrated BRG Down Counter I2CxBRG TCY/2 Read 2008 Microchip Technology Inc. DS70195B-page 19-3

4 dspic33f Family Reference Manual 19.2 I 2 C-BUS CHRCTERISTICS The I 2 C-bus is a two-wire serial interface. Figure 19-2 shows a schematic of an I 2 C connection between a dspic33f device and a 24LC256 I 2 C serial EEPROM, which is a typical example for any I 2 C interface. The interface uses a comprehensive protocol to ensure reliable transmission and reception of data. When communicating, one device acts as the master and it initiates transfer on the bus and generates the clock signals to permit that transfer, while the other device(s) acts as the slave responding to the transfer. The clock line, SCLx, is output from the master and input to the slave, although occasionally the slave drives the SCLx line. The data line, SDx, may be output and input from both the master and slave. Because the SDx and SCLx lines are bidirectional, the output stages of the devices driving the SDx and SCLx lines must have an open drain in order to perform the wired ND function of the bus. External pull-up resistors are used to ensure a high level when no device is pulling the line down. In the I 2 C interface protocol, each device has an address. When a master wishes to initiate a data transfer, it first transmits the address of the device that it wants to talk to. ll devices listen to see if this is their address. Within this address, bit 0 specifies whether the master wants to read from or write to the slave device. The master and slave are always in opposite modes (transmitter/receiver) of operation during a data transfer. That is, they can be thought of as operating in either of the following two relations: Master-Transmitter and Slave-Receiver Slave-Transmitter and Master-Receiver In either cases, the master originates the SCLx clock signal. Figure 19-2: Typical I 2 C Interconnection Block Diagram VDD VDD dspic33f SCLX SDX 4.7 kω 24LC256 (typical) SCL SD DS70195B-page Microchip Technology Inc.

5 Inter-Integrated Circuit (I 2 C ) Bus Protocol The following I 2 C-bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the SCLx clock line is high. Changes in the data line while the SCLx clock line is high will be interpreted as a Start or Stop condition. ccordingly, the bus conditions shown in Figure 19-3 have been defined. Figure 19-3: I 2 C -Bus Protocol States (I) (S) (D) (Q) () or (N) (P) (I) SCLx SDx NCK CK Start Condition Data or ddress Valid Data llowed to Change CK/NCK Valid Stop Condition STRT DT TRNSFER (S) fter a bus Idle state, a high-to-low transition of the SDx line while the clock (SCLx) is high determines a Start condition. ll data transfers must be preceded by a Start condition STOP DT TRNSFER (P) low-to-high transition of the SDx line while the clock (SCLx) is high determines a Stop condition. ll data transfers must end with a Stop condition REPETED STRT (R) fter a wait state, a high-to-low transition of the SDx line while the clock (SCLx) is high determines a Repeated Start condition. Repeated Starts allow a master to change bus direction or addressed slave device without relinquishing control of the bus DT VLID (D) The state of the SDx line represents valid data when, after a Start condition, the SDx line is stable for the duration of the high period of the clock signal. There is one bit of data per SCLx clock CKNOWLEDGE () OR NOT CKNOWLEDGE (N) ll data byte transmissions must be cknowledged (CK) or Not cknowledged (NCK) by the receiver. The receiver will pull the SDx line low for an CK or release the SDx line for a NCK. The cknowledge is a 1-bit period using one SCLx clock. Circuit (I 2 C ) Inter-Integrated WIT/DT INVLID (Q) The data on the line must be changed during the low period of the clock signal. Devices may also stretch the clock low time by asserting a low on the SCLx line, causing a wait on the bus BUS IDLE (I) Both data and clock lines remain high at those times after a Stop condition and before a Start condition Microchip Technology Inc. DS70195B-page 19-5

6 dspic33f Family Reference Manual Message Protocol typical I 2 C message is shown in Figure In this example, the message will read a specified byte from a 24LC256 I 2 C serial EEPROM. The dspic33f device will act as the master and the 24LC256 device will act as the slave. Figure 19-4 indicates the data as driven by the master device and the data as driven by the slave device, taking into account that the combined SDx line is a wired ND of the master and slave data. The master device controls and sequences the protocol. The slave device will only drive the bus at specifically determined times. Figure 19-4: Typical I 2 C Message: Read of Serial EEPROM (Random ddress Mode) Bus ctivity Idle Start ddress Byte R/W CK EEPROM ddress High Byte CK EEPROM ddress Low Byte CK Restart ddress Byte R/W CK Data Byte NCK Stop Idle Master SDx Output S X R N P Slave SDx Output STRT MESSGE Each message is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between the Start and Stop conditions is determined by the master device. s defined by the system protocol, the bytes of the message may have special meaning, such as device address byte or data byte DDRESS SLVE In Figure 19-4, the first byte is the device address byte, which must be the first part of any I 2 C message. It contains a device address and a R/W status bit. Refer to ppendix : I2C Overview in the dspic30f Family Reference Manual (DS70074) for additional information on address byte formats (check the Microchip web site for availability: Note that R/W = 0 for this first address byte, indicating that the master will be a transmitter and the slave will be a receiver SLVE CKNOWLEDGE The receiving device is obliged to generate an cknowledge signal, CK, after the reception of each byte. The master device must generate an extra SCLx clock, which is associated with this cknowledge bit MSTER TRNSMIT The next two bytes, sent by the master to the slave, are data bytes containing the location of the requested EEPROM data byte. The slave must cknowledge each of the data bytes REPETED STRT t this point, the slave EEPROM has the address information necessary to return the requested data byte to the master. However, the R/W status bit from the first device address byte specifies master transmission and slave reception. The bus must be turned in the other direction for the slave to send data to the master. To perform this function without ending the message, the master sends a Repeated Start. The Repeated Start is followed with a device address byte containing the same device address as before and with the R/W = 1 to indicate slave transmission and master reception. DS70195B-page Microchip Technology Inc.

7 Inter-Integrated Circuit (I 2 C ) SLVE REPLY Now the slave transmits the data byte by driving the SDx line, while the master continues to originate clocks but releases its SDx drive MSTER CKNOWLEDGE During reads, a master must terminate data requests to the slave by Not cknowledging (generating a NCK ) on the last byte of the message STOP MESSGE The master sends a Stop to terminate the message and return the bus to an Idle state CONTROL ND STTUS REGISTERS The I 2 C module has seven registers for operation that are accessible by the user application. ll registers are accessible in either Byte or Word mode. The registers are as follows: Control Register (I2CxCON): This register (Register 19-1) allows control of the module s operation. Status Register (I2CxSTT): This register (Register 19-2) contains status flags indicating the module s state during operation. ddress Mask Register (I2CxMSK): This register (Register 19-3) designates which bit positions in the I2CxDD register can be ignored, which allows for multiple address support. Receive Buffer Register (I2CxRCV): This is the buffer register from which data bytes can be read. The I2CxRCV register is a read-only register. Transmit Register (I2CxTRN): This is the transmit register. Bytes are written to this register during a transmit operation. The I2CxTRN register is a read/write register. ddress Register (I2CxDD): This register holds the slave device address. Baud Rate Generator Reload Register (I2CxBRG): Holds the Baud Rate Generator reload value for the I 2 C module Baud Rate Generator. I2CxTRN is the register to which transmit data is written. This register is used when the module operates as a master transmitting data to the slave, or when it operates as a slave sending reply data to the master. s the message progresses, the I2CxTRN register shifts out the individual bits. Because of this, the I2CxTRN register cannot be written to unless the bus is Idle. The I2CxTRN register can be reloaded while the current data is transmitting. Data being received by either the master or the slave is shifted into a non-accessible shift register, I2CxRSR. When a complete byte is received, the byte transfers to the I2CxRCV register. In receive operations, the I2CxRSR and I2CxRCV registers create a double-buffered receiver. This allows reception of the next byte to begin before reading the current byte of received data. If the module receives another complete byte before the software reads the previous byte from the I2CxRCV register, a receiver overflow occurs and sets the I2COV bit (I2CxSTT<6>). The byte in the I2CxRSR register is lost. Further reception and clock stretching are disabled until the module sees a Start/Repeated, Start/Stop condition on the bus. If the I2COV flag has been cleared, reception can proceed normally. If the I2COV flag is not cleared, the module will receive the next byte correctly, but will send a NCK. It will then be unable to receive further bytes or stretch the clock until it detects a Start/Repeated, Start/Stop condition. The I2CxDD register holds the slave device address. In 10-bit ddressing mode, all bits are relevant. In 7-bit ddressing mode, only the I2CxDD<6:0> bits are relevant. Note that the I2CxDD<6:0> bits correspond to the upper seven bits in the address byte; the Read/Write bit is not included in the value in this register. The 10M bit (I2CxCON<10>) specifies the expected mode of the slave address. By using the I2CxMSK register with the I2CxDD register in either Slave ddressing mode, one or more bit positions can be removed from exact address matching, allowing the module in Slave mode to respond to multiple addresses. Circuit (I 2 C ) 19 Inter-Integrated 2008 Microchip Technology Inc. DS70195B-page 19-7

8 dspic33f Family Reference Manual Register 19-1: I2CxCON: I2Cx Control Register R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN I2CSIDL SCLREL IPMIEN 10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN CKDT CKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as 0 R = Readable bit W = Writable bit HS = Set in Hardware HC = Cleared in Hardware -n = Value at Reset 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDx and SCLx pins as serial port pins 0 = Disables the I2Cx module; all I 2 C pins are controlled by port functions bit 14 Unimplemented: Read as 0 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 I2CSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I 2 C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write 0 to initiate stretch and write 1 to release clock). Hardware clear at beginning of slave transmission and at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write 1 to release clock). Hardware clear at beginning of slave transmission. IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses cknowledged 0 = IPMI Support mode disabled 10M: 10-Bit Slave ddress bit 1 = I2CxDD register is a 10-bit slave address 0 = I2CxDD register is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds GCEN: General Call Enable bit (when operating as I 2 C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR register (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (I 2 C Slave mode only; used in conjunction with SCLREL bit) 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching DS70195B-page Microchip Technology Inc.

9 Inter-Integrated Circuit (I 2 C ) Register 19-1: I2CxCON: I2Cx Control Register (Continued) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CKDT: cknowledge Data bit (I 2 C Master mode; receive operation only) Value that will be transmitted when the software initiates an cknowledge sequence 1 = Send NCK during cknowledge 0 = Send CK during cknowledge CKEN: cknowledge Sequence Enable bit (I 2 C Master mode receive operation) 1 = Initiate cknowledge sequence on SDx and SCLx pins and transmit CKDT data bit (hardware clear at end of master cknowledge sequence) 0 = cknowledge sequence not in progress RCEN: Receive Enable bit (I 2 C Master mode) 1 = Enables Receive mode for I 2 C (hardware clear at end of eighth bit of master receive data byte) 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (I 2 C Master mode) 1 = Initiate Stop condition on SDx and SCLx pins (hardware clear at end of master Stop sequence) 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (I 2 C Master mode) 1 = Initiate Repeated Start condition on SDx and SCLx pins (hardware clear at end of master Repeated Start sequence) 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (I 2 C Master mode) 1 = Initiate Start condition on SDx and SCLx pins (hardware clear at end of master Start sequence) 0 = Start condition not in progress 19 Inter-Integrated Circuit (I 2 C ) 2008 Microchip Technology Inc. DS70195B-page 19-9

10 dspic33f Family Reference Manual Register 19-2: I2CxSTT: I2Cx Status Register R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC CKSTT TRSTT BCL GCSTT DD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/ P S R/W RBF TBF bit 7 bit 0 Legend: U = Unimplemented bit, read as 0 R = Readable bit C = Clearable bit HS = Set in Hardware HSC = Hardware Set/Cleared -n = Value at Reset 1 = Bit is set 0 = Bit is clear x = Bit is unknown bit 15 CKSTT: cknowledge Status bit 1 = NCK received from slave 0 = CK received from slave Hardware set or clear at end of Slave or Master cknowledge. bit 14 TRSTT: Transmit Status bit (I 2 C Master mode transmit operation) 1 = Master transmit is in progress (8 bits + CK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission; hardware clear at end of slave cknowledge. bit Unimplemented: Read as 0 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 BCL: Master Bus Collision Detect bit 1 = bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address; hardware clear at Stop detection. DD10: 10-Bit ddress Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address; hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = n attempt to write the I2CxTRN register failed because the I 2 C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN register while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR register to I2CxRCV register (cleared by software). D/: Data/ddress bit (I 2 C Slave mode) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was a device address Hardware clear at device address match; hardware set by reception of slave byte or is set after the transmission is complete and the TBF flag is cleared. P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. DS70195B-page Microchip Technology Inc.

11 Inter-Integrated Circuit (I 2 C ) Register 19-2: I2CxSTT: I2Cx Status Register (Continued) bit 3 bit 2 bit 1 bit 0 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R/W: Read/Write Information bit (when operating as I 2 C slave) 1 = Read: data transfer is output from slave 0 = Write: data transfer is input to slave Hardware set or clear after reception of I 2 C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete; I2CxRCV register is full 0 = Receive not complete; I2CxRCV register is empty Hardware set when the I2CxRCV register is written with received byte; hardware clear when software reads the I2CxRCV register. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress; I2CxTRN register is full 0 = Transmit complete; I2CxTRN register is empty Hardware set when software writes to I2CxTRN register; hardware clear at completion of data transmission. 19 Inter-Integrated Circuit (I 2 C ) 2008 Microchip Technology Inc. DS70195B-page 19-11

12 dspic33f Family Reference Manual Register 19-3: I2CxMSK: I2Cx Slave Mode ddress Mask Register U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 MSK9 MSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as 0 -n = Value at Reset 1 = Bit is set 0 = Bit is cleared x = Bit is unknown bit Unimplemented: Read as 0 bit 9-0 MSKx: Mask for ddress Bit x Select bit For 10-Bit ddress: 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position For 7-Bit ddress (I2CxMSK<6:0> only): 1 = Enable masking for bit x + 1 of incoming message address; bit match not required in this position 0 = Disable masking for bit x + 1; bit match required in this position DS70195B-page Microchip Technology Inc.

13 Inter-Integrated Circuit (I 2 C ) 19.4 ENBLING I 2 C OPERTION The module is enabled by setting the I2CEN (I2CxCON<15>) bit. The I 2 C module fully implements all master and slave functions. When the module is enabled, the master and slave functions are active simultaneously and will respond according to the software or bus events. When initially enabled, the module will release the SDx and SCLx pins, putting the bus into the Idle state. The master functions will remain in the Idle state unless software sets the SEN control bit and data is loaded into the I2CxTRN register. These two actions initiate a master event. When the master logic is active, the slave logic also remains active. Therefore, the slave functions will begin to monitor the bus. If the slave logic detects a Start event and a valid address on the bus, the slave logic will begin a slave transaction Enabling I 2 C I/O Two pins are used for bus operation. These are the SCLx pin, which is the clock, and the SDx pin, which is the data. When the module is enabled, assuming no other module with higher priority has control, the module will assume control of the SDx and SCLx pins. The module software need not be concerned with the state of the port I/O of the pins, as the module overrides the port state and direction. t initialization, the pins are tri-stated (released) I 2 C Interrupts The I 2 C module generates two interrupts. One interrupt, MI2CxIF, is assigned to master events; the other interrupt, SI2CxIF, is assigned to slave events. These interrupts set a corresponding interrupt flag bit and interrupt the software process if the corresponding interrupt enable bit is set and the corresponding interrupt priority is high enough. The MI2CxIF interrupt is generated on completion of the following master message events: Start condition Stop condition Data transfer byte transmitted/received cknowledge transmit Repeated Start Detection of a bus collision event The SI2CxIF interrupt is generated on detection of a message directed to the slave, including the following events: Detection of a valid device address (including general call) Request to transmit data (CK) or to stop data transmission (NCK) Reception of data Circuit (I 2 C ) 19 Inter-Integrated 2008 Microchip Technology Inc. DS70195B-page 19-13

14 dspic33f Family Reference Manual Setting Baud Rate When Operating as a Bus Master When operating as an I 2 C master, the module must generate the system SCLx clock. Generally, I 2 C system clocks are specified to be either 100 khz, 400 khz or 1 MHz. The system clock rate is specified as the minimum SCLx low time and the minimum SCLx high time. In most cases, that is defined by two TBRG intervals. The reload value for the Baud Rate Generator (BRG) is the I2CxBRG register, as shown in Figure When the Baud Rate Generator is loaded with this value, the generator counts down to 0 and stops until another reload has taken place. The generator count is decremented twice per instruction cycle (TCY). The Baud Rate Generator is reloaded automatically on baud rate restart. For example, if clock synchronization is taking place, the Baud Rate Generator will be reloaded when the SCLx pin is sampled high. Note: I2CxBRG register values of less than 2 are not supported. To calculate the Baud Rate Generator reload value, use the following equation: Equation 19-1: BRG Reload Value Calculation ( ) FCY FCY I2CBRG = FSCL 10,000,000 1 Table 19-1: Required System FSCL I 2 C Clock Rates FCY I2CBRG Decimal I2CBRG Hexadecimal ctual FSCL 100 khz 40 MHz 395 0x18B 100 khz 100 khz 20 MHz 197 0x0C5 100 khz 100 khz 10 MHz 98 0x0b2 100 khz 400 khz 20 MHz 47 0x02F 400 khz 400 khz 10 MHz 23 0x khz 400 khz 5 MHz 11 0x00B 400 khz 1 MHz 10 MHz 8 0x008 1 MHz Note: Equation 19-1 and Table 19-1 are only guidelines. Due to system-dependant parameters, the actual baud rate may differ slightly. Testing will be needed to confirm that the actual baud rate meets system requirements. Otherwise, the value of I2CxBRG may need to be adjusted. Figure 19-5: Baud Rate Generator Block Diagram I2CxBRG<8:0> SCLx Reload Control Reload 2 TCY Down Counter CLK DS70195B-page Microchip Technology Inc.

15 Inter-Integrated Circuit (I 2 C ) 19.5 COMMUNICTING S MSTER IN SINGLE-MSTER ENVIRONMENT The I 2 C module s typical operation in a system is using the I 2 C to communicate with an I 2 C peripheral, such as an I 2 C serial memory. In an I 2 C system, the master controls the sequence of all data communication on the bus. In this example, the dspic33f and its I 2 C module have the role of the single-master in the system. s the single-master, it is responsible for generating the SCLx clock and controlling the message protocol. In the I 2 C module, the module controls individual portions of the I 2 C message protocol; however, sequencing of the components of the protocol to construct a complete message is a software task. For example, a typical operation in a single-master environment is to read a byte from an I 2 C serial EEPROM. This example message is depicted in Figure To accomplish this message, the software will sequence through the following steps. 1. ssert a Start condition on SDx and SCLx. 2. Send the I 2 C device address byte to the slave with a write indication. 3. Wait for and verify an cknowledge from the slave. 4. Send the serial memory address high byte to the slave. 5. Wait for and verify an cknowledge from the slave. 6. Send the serial memory address low byte to the slave. 7. Wait for and verify an cknowledge from the slave. 8. ssert a Repeated Start condition on SDx and SCLx. 9. Send the device address byte to the slave with a read indication. 10. Wait for and verify an cknowledge from the slave. 11. Enable master reception to receive serial memory data. 12. Generate an CK or NCK condition at the end of a received byte of data. 13. Generate a Stop condition on SDx and SCLx. Figure 19-6: Typical I 2 C Message: Read of Serial EEPROM (Random ddress Mode) Bus ctivity Idle Start ddress Byte R/W CK EEPROM ddress High Byte CK EEPROM ddress Low Byte CK Restart ddress Byte R/W CK Data Byte NCK Stop Idle Master SDx Output S R N P 19 Slave SDx Output The I 2 C module supports Master mode communication with the inclusion of Start and Stop generators, data byte transmission, data byte reception, cknowledge generator and a Baud Rate Generator. Generally, the software will write to a control register to start a particular step, then wait for an interrupt or poll status to wait for completion. Subsequent sections detail each of these operations. Note: The I 2 C module does not allow queueing of events. For instance, the software is not allowed to initiate a Start condition and immediately write the I2CxTRN register to initiate transmission before the Start condition is complete. In this case, the I2CxTRN register will not be written to and the IWCOL status bit will be set, indicating that this write to the I2CxTRN register did not occur. Circuit (I 2 C ) Inter-Integrated 2008 Microchip Technology Inc. DS70195B-page 19-15

16 dspic33f Family Reference Manual Generating Start Bus Event To initiate a Start event, the software sets the Start Enable bit, SEN (I2CxCON<0>). Prior to setting the Start bit, the software can check the P status bit (I2CxSTT<4>) to ensure that the bus is in an Idle state. Figure 19-7 shows the timing of the Start condition. Slave logic detects the Start condition, sets the S status bit (I2CxSTT<3>) and clears the P status bit (I2CxSTT<4>). SEN bit is automatically cleared at completion of the Start condition. MI2CxIF interrupt is generated at completion of the Start condition. fter the Start condition, the SDx line and SCLx line are left low (Q state) IWCOL STTUS FLG If the software writes the I2CxTRN register when a Start sequence is in progress, the IWCOL status bit is set and the contents of the transmit buffer are unchanged (the write doesn t occur). Note: Because queueing of events is not allowed, writing to the lower five bits of the I2CxCON register is disabled until the Start condition is complete. Figure 19-7: Master Start Timing Diagram SEN I 2 C -Bus State (I) (S) (Q) TBRG TBRG SCLx (Master) SDx (Master) S P 1 2 Writing SEN = 1 initiates a master Start event. Baud Rate Generator starts. Baud Rate Generator times out. Master module drives SDx low. Baud Rate Generator restarts. 3 Slave module detects Start and sets S = 1 and P = 0. 4 Baud Rate Generator times out. Master module drives SCLx low, generates an interrupt and clears SEN. MI2CxIF Interrupt Sending Data to a Slave Device Transmission of a data byte, a 7-bit device address byte or the second byte of a 10-bit address is accomplished by simply writing the appropriate value to the I2CxTRN register. Loading this register will start the following process: The software loads the I2CxTRN register with the data byte to transmit. Writing the I2CxTRN register sets the buffer full flag bit, TBF (I2CxSTT<0>). The data byte is shifted out through the SDx pin until all 8 bits are transmitted. Each bit of address/data will be shifted out onto the SDx pin after the falling edge of SCLx. On the ninth SCLx clock, the module shifts in the CK bit from the slave device and writes its value into the CKSTT status bit (I2CxSTT<15>). The module generates the MI2CxIF interrupt at the end of the ninth SCLx clock cycle. The module does not generate or validate the data bytes. The contents and usage of the bytes are dependent on the state of the message protocol maintained by the software. DS70195B-page Microchip Technology Inc.

17 Inter-Integrated Circuit (I 2 C ) SENDING 7-BIT DDRESS TO THE SLVE Sending a 7-bit device address involves sending one byte to the slave. 7-bit address byte must contain the 7 bits of the I 2 C device address and a R/W status bit that defines whether the message will be a write to the slave (master transmission and slave reception) or a read from the slave (slave transmission and master reception). Note: In 7-bit addressing mode, each node using the I 2 C protocol should be configured with a unique address that is stored in the I2CxDD register SENDING 10-BIT DDRESS TO THE SLVE Sending a 10-bit device address involves sending 2 bytes to the slave. The first byte contains 5 bits of the I 2 C device address reserved for 10-bit ddressing modes and 2 bits of the 10-bit address. Because the next byte, which contains the remaining 8 bits of the 10-bit address, must be received by the slave, the R/W status bit in the first byte must be 0, indicating master transmission and slave reception. If the message data is also directed toward the slave, the master can continue sending the data. However, if the master expects a reply from the slave, a Repeated Start sequence with the R/W status bit at 1 will change the R/W state of the message to a read of the slave. Note: In 10-bit addressing mode, each node using the I 2 C protocol should be configured with a unique address that is stored in the I2CxDD register RECEIVING CKNOWLEDGE FROM THE SLVE On the falling edge of the eighth SCLx clock, the TBF status bit is cleared and the master will deassert the SDx pin, allowing the slave to respond with an cknowledge. The master will then generate a ninth SCLx clock. This allows the slave device being addressed to respond with an CK bit during the ninth bit time if an address match occurs or data was received properly. slave sends an cknowledge when it has recognized its device address (including a general call) or when the slave has properly received its data. The status of CK is written into the cknowledge Status bit, CKSTT (I2CxSTT<15>), on the falling edge of the ninth SCLx clock. fter the ninth SCLx clock, the module generates the MI2CxIF interrupt and enters an Idle state until the next data byte is loaded into the I2CxTRN register CKSTT STTUS FLG The CKSTT status bit (I2CxSTT<15>) is cleared when the slave has sent an cknowledge (CK = 0) and is set when the slave does not cknowledge (CK = 1) TBF STTUS FLG When transmitting, the TBF status bit (I2CxSTT<0>) is set when the CPU writes to the I2CXTRN register and is cleared when all 8 bits are shifted out IWCOL STTUS FLG If the software attempts to write to the I2CXTRN register when a transmit is already in progress (i.e., the module is still shifting out a data byte), the IWCOL status bit is set and the contents of the buffer are unchanged (the write doesn t occur). The IWCOL status bit must be cleared in software. Note: Because queueing of events is not allowed, writing to the lower 5 bits of the I2CxCON register is disabled until the transmit condition is complete. Circuit (I 2 C ) 19 Inter-Integrated 2008 Microchip Technology Inc. DS70195B-page 19-17

18 dspic33f Family Reference Manual Figure 19-8: Master Transmission Timing Diagram I2CxTRN I 2 C -Bus State (Q) (D) (Q) (D) (Q) () (Q) SCLx (Master) SCLx (Slave) TBRG TBRG SDx (Master) D7 D6 D5 D4 D3 D2 D1 D0 SDx (Slave) TRSTT TBF MI2CxIF Interrupt CKSTT Writing the I2CxTRN register will start a master transmission event. TBF status bit is set. Baud Rate Generator starts. The MSB of the I2CxTRN register drives SDx. SCLx remains low. TRSTT status bit is set. Baud Rate Generator times out. SCLx released. Baud Rate Generator restarts. Baud Rate Generator times out. SCLx driven low. fter SCLx detected low, the next bit of I2CxTRN register drives SDx. While SCLx is low, the slave can also pull SCLx low to initiate a wait (clock stretch). Master has already released SCLx and slave can release to end wait. Baud Rate Generator restarts. t falling edge of eighth SCLx clock, master releases SDx. TBF status bit is cleared. Slave drives CK/NCK. t falling edge of ninth SCLx clock, master generates interrupt. SCLx remains low until next event. Slave releases SDx. TRSTT status bit is clear Receiving Data from a Slave Device The master can receive data from a slave device after the master has transmitted the slave address with an R/W status bit value of 1. This is enabled by setting the Receive Enable bit, RCEN (I2CxCON<3>). The master logic begins to generate clocks, and before each falling edge of the SCLx, the SDx line is sampled and data is shifted into the I2CxRSR register. Note: The lower 5 bits of the I2CxCON register must be 0 before attempting to set the RCEN bit. This ensures the master logic is inactive. fter the falling edge of the eighth SCLx clock, the following events occur: The RCEN bit is automatically cleared. The contents of the I2CxRSR register transfer into the I2CxRCV register. The RBF status bit is set. The module generates the MI2CxIF interrupt. When the CPU reads the buffer, the RBF status bit is automatically cleared. The software can process the data and then execute an cknowledge sequence. DS70195B-page Microchip Technology Inc.

19 Inter-Integrated Circuit (I 2 C ) RBF STTUS FLG When receiving data, the RBF status bit is set when a device address or data byte is loaded into the I2CxRCV register from the I2CxRSR register. It is cleared when software reads the I2CxRCV register I2COV STTUS FLG If another byte is received in the I2CxRSR register while the RBF status bit remains set and the previous byte remains in the I2CxRCV register, the I2COV status bit is set and the data in the I2CxRSR register is lost. Leaving the I2COV status bit set does not inhibit further reception. If the RBF status bit is cleared by reading the I2CxRCV register and the I2CxRSR register receives another byte, that byte will be transferred to the I2CxRCV register IWCOL STTUS FLG If the software writes the I2CxTRN register when a receive is already in progress (i.e., the I2CxRSR register is still shifting in a data byte), the IWCOL status bit is set and the contents of the buffer are unchanged (the write doesn t occur). Note: Since queueing of events is not allowed, writing to the lower 5 bits of the I2CxCON register is disabled until the data reception condition is complete. Figure 19-9: Master Reception Timing Diagram RCEN I 2 C -Bus State (Q) (Q) (D) (Q) (Q) (D) (Q) TBRG TBRG SCLx (Master) SCLx (Slave) SDx (Master) SDx (Slave) I2CxRCV RBF D7 D6 D5 D4 D3 D2 D1 D0 19 MI2CxIF Interrupt Typically, the slave can pull SCLx low (clock stretch) to request a wait to prepare data response. The slave will drive the MSB of the data response on SDx when ready. 2 Writing the RCEN bit will start a master reception event. The Baud Rate Generator starts. SCLx remains low. Circuit (I 2 C ) Inter-Integrated Baud Rate Generator times out. Master attempts to release SCLx. When slave releases SCLx, Baud Rate Generator restarts. Baud Rate Generator times out. MSB of response shifted to I2CxRSR register. SCLx driven low for next baud interval. 6 t falling edge of eighth SCLx clock, I2CxRSR register is transferred to I2CxRCV register. Module clears RCEN bit. RBF status bit is set. Master generates interrupt Microchip Technology Inc. DS70195B-page 19-19

20 dspic33f Family Reference Manual cknowledge Generation Setting the cknowledge Enable bit, CKEN (I2CxCON<4>), enables generation of a master cknowledge sequence. Note: The lower 5 bits of the I2CxCON register must be 0 (master logic inactive) before attempting to set the CKEN bit. Figure shows an CK sequence and Figure shows a NCK sequence. The cknowledge Data bit, CKDT (I2CxCON<5>), specifies CK or NCK. fter two baud periods, the CKEN bit is automatically cleared and the module generates the MI2CxIF interrupt IWCOL STTUS FLG If the software writes the I2CxTRN register when an cknowledge sequence is in progress, the IWCOL status bit is set and the contents of the buffer are unchanged (the write doesn t occur). Note: Because queueing of events is not allowed, writing to the lower five bits of the I2CxCON register is disabled until the cknowledge condition is complete. Figure 19-10: Master cknowledge (CK) Timing Diagram CKDT = 0 CKEN I 2 C -Bus State (Q) (Q) () (Q) TBRG TBRG SCLx (Master) SDx (Master) MI2CxIF Interrupt Writing CKDT = 0 specifies sending an CK. Writing CKEN = 1 initiates a master cknowledge event. Baud Rate Generator starts. SCLx remains low. When SCLx detected low, module drives SDx low. Baud Rate Generator times out. Module releases SCLx. Baud Rate Generator restarts. Baud Rate Generator times out. Module drives SCLx low, then releases SDx. Module clears CKEN. Master generates interrupt Figure 19-11: Master Not cknowledge (NCK) Timing Diagram CKEN CKDT = 1 I 2 C -Bus State (Q) () (I) 1 Writing CKDT = 1 specifies sending a NCK. Writing CKEN = 1 initiates a master cknowledge event. Baud Rate Generator starts. TBRG TBRG 2 When SCLx detected low, module releases SDx. SCLx (Master) SDx (Master) MI2CxIF Interrupt 3 4 Baud Rate Generator times out. Module releases SCLx. Baud Rate Generator restarts. Baud Rate Generator times out. Module drives SCLx low, then releases SDx. Module clears CKEN. Master generates interrupt DS70195B-page Microchip Technology Inc.

21 Inter-Integrated Circuit (I 2 C ) Generating Stop Bus Event Setting the Stop Enable bit, PEN (I2CxCON<2>), enables generation of a master Stop sequence. Note: The lower 5 bits of the I2CxCON register must be 0 (master logic inactive) before attempting to set the PEN bit. When the PEN bit is set, the master generates the Stop sequence as shown in Figure The slave detects the Stop condition, sets the P status bit (I2CxSTT<4>) and clears the S status bit (I2CxSTT<3>). The PEN bit is automatically cleared. The module generates the MI2CxIF interrupt IWCOL STTUS FLG If the software writes the I2CxTRN register when a Stop sequence is in progress, the IWCOL status bit is set and the contents of the buffer are unchanged (the write doesn t occur). Note: Because queueing of events is not allowed, writing to the lower five bits of the I2CxCON register is disabled until the Stop condition is complete. Figure 19-12: Master Stop Timing Diagram PEN I 2 C -Bus State (Q) (Q) TBRG TBRG (P) TBRG (I) 1 2 Writing PEN = 1 initiates a master Stop event. Baud Rate Generator starts. Module drives SDx low. Baud Rate Generator times out. Module releases SCLx. Baud Rate Generator restarts. SCLx (Master) SDx (Master) S P Baud Rate Generator times out. Module releases SDx. Baud Rate Generator restarts. Slave logic detects Stop. Module sets P = 1 and S = 0. The Baud Rate Generator times out. Module clears PEN. Master generates interrupt. MI2CxIF Interrupt Inter-Integrated Circuit (I 2 C ) 2008 Microchip Technology Inc. DS70195B-page 19-21

22 dspic33f Family Reference Manual Generating Repeated Start Bus Event Setting the Repeated Start Enable bit, RSEN (I2CxCON<1>), enables generation of a master Repeated Start sequence (see Figure 19-13). Note: The lower 5 bits of the I2CxCON register must be 0 (master logic inactive) before attempting to set the RSEN bit. To generate a Repeated Start condition, software sets the RSEN bit (I2CxCON<1>). The module asserts the SCLx pin low. When the module samples the SCLx pin low, the module releases the SDx pin for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out and the module samples SDx high, the module deasserts the SCLx pin. When the module samples the SCLx pin high, the Baud Rate Generator reloads and begins counting. SDx and SCLx must be sampled high for one TBRG. This action is then followed by assertion of the SDx pin low for one TBRG while SCLx is high. The following is the Repeated Start sequence: The slave detects the Start condition, sets the S status bit (I2CxSTT<3>) and clears the P status bit (I2CxSTT<4>). The RSEN bit is automatically cleared. The module generates the MI2CxIF interrupt IWCOL STTUS FLG If the software writes the I2CxTRN register when a Repeated Start sequence is in progress, the IWCOL status bit is set and the contents of the buffer are unchanged (the write doesn t occur). Note: Because queueing of events is not allowed, writing of the lower five bits of the I2CxCON register is disabled until the Repeated Start condition is complete. Figure 19-13: Master Repeated Start Timing Diagram RSEN I 2 C -Bus State (Q) SCLx (Master) (Q) TBRG TBRG (S) TBRG (Q) 1 2 Writing RSEN = 1 initiates a master Repeated Start event. Baud Rate Generator starts. Module drives SCLx low and releases SDx. Baud Rate Generator times out. Module releases SCLx. Baud Rate Generator restarts. SDx (Master) S P 3 4 Baud Rate Generator times out. Module drives SDx low. Baud Rate Generator restarts. Slave logic detects Start. Module sets S = 1 and P = 0. MI2CxIF Interrupt 5 The Baud Rate Generator times out. Module drives SCLx low. Module clears RSEN. Master generates interrupt DS70195B-page Microchip Technology Inc.

23 Inter-Integrated Circuit (I 2 C ) Building Complete Master Messages s described at the beginning of 19.5 Communicating as a Master in a Single-Master Environment, the software is responsible for constructing messages with the correct message protocol. The module controls individual portions of the I 2 C message protocol; however, sequencing of the components of the protocol to construct a complete message is a software task. The software can use polling or interrupt methods while using the module. The examples shown use interrupts. The software can use the SEN, RSEN, PEN, RCEN, and CKEN bits (Least Significant 5 bits of the I2CxCON register) and the TRSTT status bit as a state flag when progressing through a message. For example, Table 19-2 shows some example state numbers associated with bus states. Table 19-2: Example State Number Master Message Protocol States I2CxCON<4:0> TRSTT (I2CxSTT<14>) State Bus Idle or Wait N/ Sending Start Event Master Transmitting N/ Sending Repeated Start Event N/ Sending Stop Event N/ Master Reception N/ Master cknowledgement Note: Example state numbers for reference only. User software can assign state numbers as desired. The software will begin a message by issuing a Start command. The software will record the state number corresponding to the Start. s each event completes and generates an interrupt, the interrupt handler may check the state number. So, for a Start state, the interrupt handler will confirm execution of the Start sequence and then start a master transmission event to send the I 2 C device address, changing the state number to correspond to the master transmission. On the next interrupt, the interrupt handler will again check the state, determining that a master transmission just completed. The interrupt handler will confirm successful transmission of the data, then move on to the next event, depending on the contents of the message. In this manner, on each interrupt, the interrupt handler will progress through the message protocol until the complete message is sent. Figure provides a more detailed examination of the same message sequence shown in Figure Figure shows some simple examples of messages using 7-bit addressing format. Figure shows an example of a 10-bit addressing format message sending data to a slave. Figure shows an example of a 10-bit addressing format message receiving data from a slave. Circuit (I 2 C ) 19 Inter-Integrated 2008 Microchip Technology Inc. DS70195B-page 19-23

24 DS70195B-page Microchip Technology Inc. Figure 19-14: SEN RSEN RCEN CKEN KDT PEN SCLx (Master) SDx (Master) SCLx (Slave) SDx (Slave) I2CxTRN TBF I2CxRCV RBF CKSTT MI2CxIF Master Message (Typical I 2 C Message: Read of Serial EEPROM) W R Setting the SEN bit starts a Start event Writing the I2CxTRN register starts a master transmission. The data is the serial EEPROM device address byte, with R/W status bit clear, indicating a write. 3 Writing the I2CxTRN register starts a master transmission. The data is the first byte of the EEPROM data address. 4 5 MI2CxIF interrupt flag cleared by user software. Writing the I2CxTRN register starts a master transmission. The data is the second byte of the EEPROM data address. Setting the RSEN bit starts a Repeated Start event D7 D6 D5 D4 D3 D2 D1 D Writing the I2CxTRN register starts a master transmission. The data is a re-send of the serial EEPROM device address byte, but with R/W status bit set, indicating a read. 7 Setting the RCEN bit starts a master reception. On interrupt, the software reads the I2CxRCV register, which clears the RBF status bit. 8 Setting the CKEN bit starts an cknowledge event. CKDT = 1 to send NCK. 9 Setting the PEN bit starts a master Stop event. 9 N dspic33f Family Reference Manual

25 2008 Microchip Technology Inc. DS70195B-page Figure 19-15: SEN RSEN RCEN CKEN KDT PEN SCLx (Master) SDx (Master) SCLx (Slave) SDx (Slave) I2CxTRN TBF I2CxRCV RBF CKSTT MI2CxIF Master Message (7-Bit ddress: Transmission nd Reception) W Setting the SEN bit starts a Start event. 9 D7 D6 D5 D4 D3 D2 D1 D0 MI2CxIF interrupt flag cleared by user software. 2 Writing the I2CxTRN register starts a master transmission. The data is the address byte with R/W status bit clear. 3 Writing the I2CxTRN register starts a master transmission. The data is the message byte. 4 Setting the PEN bit starts a master Stop event. 5 Setting the SEN bit starts a Start event D7 D6 D5 D4 D3 D2 D1 D Writing the I2CxTRN register starts a master transmission. The data is the address byte with R/W status bit set. 7 Setting the RCEN bit starts a master reception. 8 Setting the CKEN bit starts an cknowledge event. CKDT = 1 to send NCK R Setting the PEN bit starts a master Stop event. 9 N Inter-Integrated Circuit (I 2 C ) Inter-Integrated Circuit (I 2 C ) 19