MSC8156 Ethernet Interface

Transcription

1 June 21, 2010 MSC8156 Ethernet Interface QUICC Engine Ethernet Programming Andrew Temple NMG DSP Applications Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink

2 Agenda Introduction Session Objectives MSC8156 Overview QUICC Engine Overview QUICC Engine Ethernet Programming: General Setup Parameter RAMs Ethernet Filtering Class Example Session Summary References Close Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 2

3 Ethernet communication is a key point for networking based devices such as the MSC815x series devices. To maximize application performance, a programmer must understand how to set up the Ethernet for efficiency. In some cases, engineers do not want to use the available OS solution (SmartDSP) for their Ethernet software suite. In order to assist in debug, some knowledge of the Ethernet programming model is a must! Presenter: QUICC Engine lead for DSP Applications Team 1 Hour for this session Session Introduction Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 3

4 Session Objectives After completing this session, you will be able to: Understand how to set up an Ethernet Programming Model Program the QUICC Engine to manage filtering of Ethernet packets based on L2, L3, L4, etc parameters Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 4

5 MSC8156 Overview DDR800 DDR800 DDR 2/3 Controller DDR 2/3 Controller M3 Memory 1056 KB MAPLE-B FFT PE TVPE DFT PE 800MHz-1GHz StarCore SC3850 Subsystem SC3850 DSP Core 32 KB I-Cache MMU 32 KB D-Cache 800MHz-1GHz StarCore SC3850 Subsystem SC3850 DSP Core 32 KB I-Cache MMU 32 KB D-Cache 800MHz-1GHz StarCore SC3850 Subsystem SC3850 DSP Core 32 KB I-Cache MMU 32 KB D-Cache 800MHz-1GHz StarCore SC3850 Subsystem SC3850 DSP Core 32 KB I-Cache MMU 32 KB D-Cache 800MHz-1GHz StarCore SC3850 Subsystem SC3850 DSP Core 32 KB I-Cache MMU 32 KB D-Cache 800MHz-1GHz StarCore SC3850 Subsystem SC3850 DSP Core 32 KB I-Cache MMU 32 KB D-Cache RISC RISC 512 KB L2/M2 512 KB L2/M2 512 KB L2/M2 512 KB L2/M2 512 KB L2/M2 512 KB L2/M2 <8 GB/s <8 GB/s 8 GB/s 4 GB/s 8 GB/s 8 GB/s 4 GB/s 8 GB/s 4 GB/s 8 GB/s 4 GB/s 8 GB/s 4 GB/s 8 GB/s 4 GB/s 8 GB/s 4 GB/s Non-blocking Switching Matrix 500MHz 8 GB/s 8 GB/s Boot ROM JTAG/ SAP Security Engine RISC 1Gbps Ethernet QUICCEngine SPI RISC 1Gbps Ethernet High Speed Serial Interfaces (HSSI) SRIO 1x/4x LYNX OCN8 SRIO 1x/4x PCI-EX LYNX TDM 1024 Ch. I2C UART 16 ch. DMA Virtual Interrupts & Hardware Semaphores 1 Gbps 1 Gbps 1x/4x Gb 1x/4x Gb Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 5

6 QUICC Engine Overview Dual 32-bit RISC Processors ROM stores the RISC s main ucode IRAM stores uploaded ucode MURAM 48 Kbytes of multi-user data RAM Stores parameter ram, VFIFOs, user data UCC: Two Ethernet controllers Physical interfaces: RGMII SGMII MAC-to-MAC and MAC-to-PHY Connectivity Full and half-duplex support. IEEE full duplex flow control Ethernet Statistics Gathering Internal loop-back ROM0 192KB 32 bit RISC0 IRAM1 24KB SPI UCC1 UCC3 xmii SDMA MURAM 48KB ROM1 192KB 32 bit RISC1 xmii IRAM1 24KB Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 6

7 General Guidelines for QUICC Engine Programming of MSC815x Recommended to start with/use SmartDSP OS Simplifies Ethernet programming model Provided with the CodeWarrior Suite Common software model for support of MSC815x devices Examples available in the SmartDSP\demos\starcore\msc815x folder Demos include: Demos to ping ADS board and run Internal / External loopback Demos for MAC, IP, and UDP packet filtering and echoing with the QUICC Engine Demos for Filtering to one core or multiple cores Demos for Single and Multi-buffered framing Customers may wish to avoid using SmartDSP: Custom software model Running a specific test or validation suite Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 7

8 General Configuration Registers Memory Mapped Registers Parameter RAM Key QUICC Engine Programming Concepts User allocated structures containing QUICC Engine configuration settings Parse Command Descriptors Packet filtering command structures Buffer Descriptors Pointers to buffer space for sending and receiving packets QUICC Engine Command Register Tell QUICC Engine where PRAM structures are Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 8

9 Ethernet Programming Model Registers are split into 2 main categories: Memory mapped registers Interface Speed, Modes, and Enable/Disable Receive and Transmit FIFOs, I/O, and Clocks Address Filtering with MAC Station Registers Hardware Statistics MII Management and PHY control User Allocated Parameter RAM Register Data Structures RX Ethernet Parameters Packet Reception, Filtering, and Storage Firmware Statistics (Includes error counting) TX Ethernet Parameters: Packet Transmission and Storage Firmware Statistics (Includes error counting) QUICC Engine is informed of PRAM data structure locations via: CECR: QUICC Engine Command Register CECDR: QUICC Engine Command Data Register Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 9

10 Interface Setup (Memory Mapped Registers) Quick reference: Interface Mode and Speed Setup: MAC Configuration MII Gasket register UPSMR (Protocol Specific Ethernet Mode Register) Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 10

11 Parameter RAM Heirarchy InitEnet Data Structure: Programmed into QUICC Engine with CECR+CECDR Contains pointer to base address of RX and TX Global PRAM (user defined) Defines RISC and Thread allocation within QUICC Engine (SNUMs) Rx queue Table Rx Global Parameter Table InitEnet Table Tx Global Parameter Table Tx queue Table RxBD Table TxBD Table Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 11

12 Rx Global parameter RAM Rx Global Parameter RAM REMODER RQPTR RxRMONBasePointer Thread Data structure Size depends on number of threads (set in InitEnet) IntCoalecing Pointer RBDQPTR Ethernet Firmware Statistics Rx Layer2 QoS Table L2QT L3QT AF 64B Address Filtering Int Coalesing Pointer Rx Layer3 QoS Table EXPGlobalParam RxBD queue pointer LossLessFCPtr PCD chain Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 12

13 Extended Parsing Mode: Receive Packet Queues Data0 BD0 BD0 BD0 BD3 BD1 BD3 BD1 BD3 BD1 BD2 BD2 BD2 Queue0 (Default) queue1 queue2 Maximum eight queue are available. Filtering RISC process Incoming Packet Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 13

14 Packet Formats Ethernet Frame (L2): IPv4: UDP: Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 14

15 Ethernet Packet Filtering (MPC82xx vs. Extended Parsing) REMODER Register determines filtering mode Extended Parsing Mode vs MPC82xx Compatible Mode MPC82xx Compatible Mode (REMODER[EXP]=0) Reception uses L2 address matching with: MacStnAddr Register PADDR (if REMODER[EXF] set) Standard L2 Packets filtered to default queue ONLY Extended Parsing Mode (REMODER[EXP]=1) Parse Command Descriptors (PCD) create a chain of filters Hash Table used for checking for address matches Accepted frames can be sent to up to 8 queues Queues can be associated with any core Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 15

16 MPC82xx Compatible Filtering Flow Receive Unicast Frame F REMODER [EXF] == 1? T PADDR1..4 Match? F T F L2 Dest == MACSTNADR Register? T Receive Frame (Queue 0 if no VLAN) Set RxBD[Miss], Receive up to MAXD2 in Queue 0 Discard Frame Hash table search using RxGlobalPram[AF] IADDR Hash Table Match? F T T Promiscuous? F Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 16

17 MACSTNADDR Registers Usage: Address Filtering Source address for flow control frames Memory Mapped Byte ordering is reversed: For MAC Address == ABCD MACSTNADDR1 == CDAB7856 MACSTNADDR2 == Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 17

18 MPC82xx Address Filtering and Extended Features MPC82xx Extended Features Enabled when: REMODER[EXP]=0 REMODER[EXF]=1 AF[PADDR1..4] provides additional L2 address filters When MACSTNADDR and AF[PADDR1..4] match fails MPC82xx Hash Table filtering may be used Rx Global parameter RAM REMODER RQPTR RxRMONBasePointer IntCoalecing Pointer RBDQPTR L2QT L3QT AF 64B Address Filtering EXPGlobalParam IADDR_H IADDR_L GADDR_H GADDR_L TADDR_H TADDR_M TADDR_L PADDR1_H PADDR1_M PADDR1_L PADDR4_H PADDR4_M PADDR4_L LossLessFCPtr Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 18

19 MPC82xx Hash Table Filtering GADDR/IADDR bits are mapped to hash table entries Add Hash Table Entry: Place Group or Individual address value to TADDR Issue QUICC Engine CECR command with SET GROUP ADDR QUICC Engine will perform CRC32 on TADDR, and use 6 lsb for filter Filter with Hash Table: QUICC Engine performs CRC32 on incoming frame s DA Compares 6 lsb to hash table entry On match, accept NOTE: All frames matching will be accepted Of non-matching frames, up to 87.5% will be filtered out Core will have to filter the rest Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 19

20 Benefits Enables multiple filters to be applied to a single packet Extended Parsing Mode Enables parsing on L2, L3, L4 and general packet headers Packet header insertion / extraction Allows packets to be sent to different DSP Cores based on filtering results Extended Parsing Discussion: EXP parsing flow EXP Filtering (HASH Tables introduction) Parse Command Descriptors Programming Model and Example Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 20

21 Extended Parsing Mode Flow Enable: REMODER[EXP]=1 Uses a chain of PCDs for filtering packet headers Filtering for: L2 (MAC Layer) L3 (IPv4/v6 Layer) L4 (UDP/TCP Layer) Filtering for up to 8 queues Queues can be associated with any core Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 21

22 Extended Parsing Field Comparison: Hash Tables Hash tables are used to efficiently compare packet contents Hash Key Packet contents are converted into a Hash Key Key points to a specific part of the Hash Table with 4 entries (8 entries for 8 way Hash Table) Only 4 comparisons required after hash lookup for 4 way hash table Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 22

23 Extended Parsing Mode: Hash Tables Non-Hash Filtering: Incoming packet header compared against pattern Match = accept Miss = discard Worst case scenario: All patterns used in comparison Incoming pattern Hit pattern0 pattern1 pattern2 pattern3 pattern4 pattern5 pattern6 pattern7 By using hash key, QUICC Engine greatly reduces comparison overhead: Hash function leads to comparison within 1 set -> max 4 comparisons Incoming pattern HASH Hit pattern0 pattern1 pattern2 pattern3 pattern4 pattern5 pattern6 pattern7 Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 23

24 Hash Table Lookup Entry Hash Lookup Table Components: N Sets of 4 (or 8) ways. Each way containing: Termination Action Descriptor: Action when matched Exact Match Tag: Compare to Lookup Key Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 24

25 Parse Command Descriptors Extract information from incoming packets for comparison Use extracted information to compare against Hash tables On match, filter to a given RxBD Queue In our PCD discussion we will cover: PCD Types PCD Chaining PCD Programming Model Example Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 25

26 PCD Types First PCD location: EXPGlobalParam pointer PCD Type distinguished by PCD OPCODE Generate Lookup Keys L2 Specific L2, L3, L4 Mask Table Lookup TAD Last Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 26

27 Extended Parsing and PCDs QUICC Engine uses Parse Command Descriptors (PCDs) to access Hash Table TAD0 L2PCDPTR Generate L2LookupKey PCD TAD1 TAD2 Parse Miss Change Mask PCD Four-Way Hash Lookup PCD Generate L2LookupKey PCD Change Mask PCD Lookup miss TAD3 TAG0(8B) TAG1(8B) TAG2(8B) TAG3(8B) Set0 Four-Way Hash Lookup PCD TAD0 Generate L2LookupKey PCD Change Mask PCD Four-Way Hash Lookup PCD Last PCD( Chain terminate by this PCD) indicates Last, TAD1 TAD2 TAD3 TAG0(8B) Set1 LAST PCD TAG1(8B) TAG2(8B) PCD chain TAG3(8B) Lookup Table for first PCD chain Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 27

28 Chained PCDs A lookup hit can lead to further comparisons by using the CPL field of the Termination Action Descriptor: PCDs are placed contiguously in memory and execute sequentially until a match occurs or a last PCD is encountered Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 28

29 L2LookupGey generation Generate Lookup Key PCDs are used to extract the header from a frame to be used in Hash Table lookups GenerateL2LookupKey extracts L2 specific header information Configuration example below shows MAC Destination header extraction Incoming Frame L2 L3 L4 Payload DA SA Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 29

30 Change MASK PCD Change Mask allows the user to mask specific bits of the Lookup Key Mask Index indicates offset from the start of the Lookup Key where the 4 byte mask is applied LookupKey_H LookupKey_L Index[ ] Index[ ] Index[ ] Index[ ] Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 30

31 Four-way Hash Lookup PCD LookupKeySize is the size of the lookup key used in the Hash Table Lookup. If the actual lookup key is larger, it is truncated to this size Hash Key Size Decides how many bits from the key to use in the hash lookup Corresponds to the number of sets in the hash table Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 31

32 Select Four-way or Eight-way Hash Lookup Table Select Four-way or Eight-way for Hash Lookup PCD # of ways for each Set Exact Match Tags are used for comparison to the Lookup Key Termination Action Descriptors (TAD) determine what to do on a match Exact Match TAG0_H Exact Match TAG0_L Exact Match TAG1_H Exact Match TAG1_L Exact Match TAG2_H Exact Match TAG2_L Exact Match TAG3_H Exact Match TAG3_L Exact Match TAG4_H Exact Match TAG4_L Exact Match TAG5_H Exact Match TAG5_L Exact Match TAG6_H Exact Match TAG6_L Exact Match TAG7_H Exact Match TAG7_L TAD0 TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 Exact Match TAG0_H Exact Match TAG0_L Exact Match TAG1_H Exact Match TAG1_L Exact Match TAG2_H Exact Match TAG2_L Exact Match TAG3_HExact Match TAG3_L Lookup key table ( pattern ) Lookupkeysize=16byte TAD0 TAD1 TAD2 TAD3 Operation table Set Lookup key table ( pattern ) Lookupkeysize=16byte Operation table Set Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 32

33 Creating a Hash Lookup Table CECR + CECDR command points to this data structure ADDE: add or delete an entry EXLT (unused in 81xx) TAD: Termination Action Descriptor Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 33

34 Example Hash Table Entry Example hash table entry: Up to 4 Sets Destination MAC= If match, Send to Queue0 Termination Action Descriptor sets: Valid Ready for use RQoS: Use VPriority for destination queue VPriority: Queue # Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 34

35 Exercise: Set up PCDs for L4 Filtering Goal: To filter incoming packets based on UDP Port number Each port should filter packets to a different Core in the DSP subsystem Question: What do we need to set up? PRAM, PCD base, Generate Lookup, Hash Table Entries, and TADs Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 35

36 Rx Global parameter RAM Exercise Step 1: Init Rx Global PRAM REMODER RQPTR RxRMONBasePointer IntCoalecing Pointer RBDQPTR L2QT L3QT AF 64B Address Filtering EXPGlobalParam LossLessFCPtr Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 36

37 Rx Global parameter RAM Example Step 2: PCD Base setup REMODER RQPTR RxRMONBasePointer IntCoalecing Pointer RBDQPTR L2QT L3QT AF 64B Address Filtering EXPGlobalParam LossLessFCPtr Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 37

38 Example Step 3: Generate Lookup Key (UDP Port #) Extract L4 Destination Port TUSP DST Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 38

39 Example Step 4: Hash Lookup and Last PCD Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 39

40 Allocate space for hash table Add entries for the 4 UDP ports Example Step 5: Hash Lookup Table Initialization Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 40

41 Example Step 5 Hash Lookup Table (continued) After data structure created, send to QUICC Engine using: CECDR = Table Address CECR= Add Entry in Hash Lookup Table Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 41

42 Session Summary Focused on the key points of the Ethernet programming model Re-focused on Parameter RAM (PRAM) programming Learned how to set up Ethernet filtering for various types of packets Reviewed the setup using an example (Filtering to multiple queues by UDP Port) Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 42

43 For Further Information QUICC Engine Reference Manual version 3 Refer to Chapter 4, 7, 8, and 30 specifically for MSC815x Specific Material MSC8156 Reference Manual AN3428: QUICC Engine Ethernet Extended Frame Filtering using PCDs IEEE Ethernet Standards Freescale Support: support@freescale.com Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 43

44 Session Closing By now, you should be able to: Describe and discuss the key features to QE as they relate to frame filtering Effectively describe the Ethernet programming model Assist a customer with more in depth programming of Ethernet setup and frame filtering Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink 44

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