Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis,

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1 May 2013 Freescale, the Freescale logo, AltiVec, C-5, CodeTEST, CodeWarrior, ColdFire, ColdFire+, C- Ware, the Energy Efficient Solutions logo, Kinetis, mobilegt, PEG, PowerQUICC, Processor Expert, QorIQ, Qorivva, StarCore, Symphony and VortiQa are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Airfast, BeeKit, BeeStack, CoreNet, Flexis, Layerscape, MagniV, MXC, Platform in a Package, QorIQ Qonverge, QUICC Engine, Ready Play, SafeAssure, the SafeAssure logo, SMAROS, Tower, TurboLink, Vybrid and Xtrinsic are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

2 Freescale Networking SoC Evolution QorIQ T Series update Layerscape Introduction 2

3 Demands on the network infrastructure continue to grow exponentially 3

4 1995 PowerQUICC processors launch 2008 QorIQ Multicore Platform launch (P series) 2011 QorIQ Qonverge platform launch QorIQ AMP series launch 2013 QorIQ next-generation platform based on Layerscape architecture Accelerating the Network s IQ QorIQ The smarter approach to multicore 20 Years of Networking Ingenuity from the #1 Leader in Communications Processing 4

5 I/O I/O I/O I/O I/O I/O I/O Accel I/O I/O I/O I/O Accel Accel Accel Single Core with Hardware Accelerators Homogeneous Multi-core Performance Density Multi-core Multi-core with Accelerated Packet and Flow Processing CPU CPU CPU Cluster CPU Cluster CPU Cluster CPU Cluster CPU CPU CPU Shared L2 Shared L2 Shared L2 Shared L2 Shared Bus PPE Accel Accel PPE PPE Accel Hardware acceleration provides better performance/power efficiency than general purpose compute General-purpose processing with some parallelism; Hardware acceleration for specific tasks DPAA 1.0 Heavy Threading and Clustering improves performance/power density DPAA1.1 Increasing Demand for Software-Awareness Clusters of Hardware Accelerators targeted at Advanced Packet and Flow Processing 5

6 SATA, USB, SD/MMC Lower system cost SEC 5.0 Enhanced RSA Operation for SSL 1024b RSA 25K operations 2048b RSA 7.8K operations 40Gbps DES 20Gbps AES 20G CRC PME 10G Regex Engine DCE - Compression Deflate, GZIP, Zlib 10Gbps Networking 48Gbps bandwidth 2x HiGig MAC IEEE802.3az (EEE) IEEE802.3bf (Time sync) Data Center Bridging (DCB) Priority Flow Control Enhanced Transmission Selection PCIe Gen 3 SRIOV EP SERDES Upto 10GHz XFI, XUAI, QSGMII, SGMII, PCIe, SRIO, Interlaken, 6

7 Cores P2040 P2041 P3041 T1042 T2081 T2080 4x e500mc, 32b 4x e500mc, 32b 4x e500mc, 32b 4x e5500, 64b 4x e6500, 64b 4x e6500, 64b Threads Frequency 667MHz 1.2GHz GHz GHz GHz GHz GHz L2 None 256kB 256kB 1MB 2MB 2MB L3 1MB 1MB 1MB 256kB 512kB 512kB DDR 1x DDR3/3L to 1200MT/s 1x DDR3/3L to 1333MT/s 1x DDR3/3L to 1333MT/s 1x DDR3L/4 to 1333MT/s 1x DDR3/3L to 2133MT/s 1x DDR3/3L to 2133MT/s SerDes 10 to 5GHz 10 to 5GHz 18 to 5GHz 8 to 5GHz 8 to 10GHz 16 to 10GHz Enet 5x 1GE 10GE + 5x 1GE 10GE + 5x 1GE 5x 1GE 2x 1/10GE + 5x 1GE PCIe Cntrls 3 at Gen2 3 at Gen2 3 at Gen2 4 at Gen2 3 at Gen2 + 1 at Gen3 4x 1/10GE + 4x 1GE 3 at Gen2 + 1 at Gen3 SATA No 2 USB2.0 2 w/ int. PHY 2 w/ int. PHY 2 w/ int. PHY 2 w/ int. PHY 2 w/ int. PHY 2 w/ int. PHY SRIO/Rman No No 2 Aurora Yes Yes Yes Yes No Yes TDM/HDLC No No No 2 No No Acceleration SEC, PME SEC, PME SEC, PME SEC, PME, QE SEC, PME, SEC, PME, 7 DCE DCE

8 Enterprise Routers/Switches U Security Appliances Mobile Backhaul Aerospace & Defense Dual-threaded e6500 core offers the highest CoreMark/watt rating Fixed function acceleration engines for application offload Secure Boot prevents box hacking and software IP theft Advanced virtualization for safe partitioning between control and data plane AltiVec engine for DSP-like calculations The T2080 embedded processor was designed to provide maximum benefit for mid-range applications 8

9 High Performance Core/Caches Power Architecture e5500 core 256 KB/core L2 cache 256 KB platform cache Up to 1.4 GHz Hybrid 32-bit mode for legacy software support Supports up to 64 GB addressability 9

10 Enterprise Routers/Switches Industrial Computing and Networking U Security Appliances The T1042 embedded processor was architected to provide maximum performance per watt Highest performance CPU cores in the power envelop Offload engines industry highest IPSec in its class Deep packet inspection offload engine enabling U applications DPAA for QoS and balanced networking performance Virtualization to support customers and 3 rd party software Small form factor, fanless and convection cooled designs 10

11 Performance - Eight Virtual Cores up to 1.8GHz T Quad-Core up to 1.4GHz - Integrated GbE Switch T Quad-Core up to 1.4GHz - Dual-Core up to 1.4GHz - Integrated GbE Switch - Dual-Core up to 1.4GHz T1020 T1042 Scale from dual, quad to eight virtual cores with QorIQ T1/T2 devices T1022 Power 11

12 Increasing Performance P4080 T2080 Lower power 2x performance increase in same power range P3041, P2041 Lower power T1042 P1020 P2020 2x performance in same power range Decreasing Power (Watt) 12

13 PCIe PCIe PCIe PCIe Pre-fetch T1 T2 Power Arch e6500 T1 T2 Power Arch e6500 T1 T2 Power Arch e6500 T1 T2 Power Arch e KB 32 KB D-Cache I-Cache 32 KB 32 KB 32 KB 32 KB D-Cache I-Cache D-Cache I-Cache 2MB Banked L2 32 KB 32 KB D-Cache I-Cache 512KB Platform Cache 64-bit DDR3/3L DDR2/3 Memory Controller Security Fuse Processor Security Monitor Coherency Fabric IFC PAMU PAMU Peripheral Access Mgmt Unit PAMU Power Management SDXC/eMMC 2x DUART 4x I2C DCE 1.0 Security 5.2 (XoR, CRC) Queue Mgr. Parse, Classify, Distribute DCB 8ch DMA 8ch DMA SPI, GPIO 2x USB2.0 + PHY PME 2.1 Buffer Mgr. Frame Manager 2x 10G 2x 2.5G 7x 1G 8-Lane 10GHz SERDES Intelligent Integration High performance dual-threaded 64-bit cores High performance software controlled data path architecture High performance accelerators to offload compute intensive functions (IPSec, IDS/IPS, Compression) High speed connectivity 10GE, 10GHz SerDes 13

14 Accelerating the Network s IQ Layerscape architecture is an evolution of our Data Path Acceleration Architecture (DPAA) Modular and flexible hardware framework includes independently scalable layers to maximize performance and power efficiency Full programmability with ease through embedded C-based structured programming Autonomous and value-add capabilities through a traditional sequential, synchronous, run to completion model True deterministic wire-rate performance between all network interfaces supporting L2+ switching capabilities Enhanced manageability and control offering non-intrusive, comprehensive view into the system Single architecture and consistent software 14

15 System Interfaces System Control System Visualization (Debug/Tuning) GPP Layer APP Layer EPI Layer General Purpose Processing Layer (GPPL) Core-agnostic (Power Architecture or ARM cores) Accelerated Packet Processing Layer (APPL) Decomp Engine CPU(s) Security Engine Load Balance Engine Caches Pattern Match Engine Accelerated Packet Processor L2-L7 Switch Engine Mem. Cont. Packet Buffer Consistent APIs/libraries with tools abstract hardware changes Single framework for programming for GGPL/APPL Capable of fully autonomous offload Synchronous run to completion model True programmability Ethernet Interlaken Express Packet I/O Layer (EPIL) 100/40/10/1G SERDES RapidIO PCI-Express Deterministic performance Scalability from 1G-100G Packetized I/O between all interfaces supporting L2+ switching Performance insights for real-time network adjustments 15

16 First Families Based on Layerscape Architecture for the Lowest-Power Tier of the QorIQ Portfolio Scalable portfolio of software- and pin-compatible families Purpose-built for fan-less, small-form-factor networking applications High-performance ARM Cortex -A7 and Cortex-A15 cores Exceptional performance per watt enabling a new class of applications starting at under 3W Advanced capabilities including virtualization support Combines Freescale networking expertise with ARM ecosystem reach Accelerating the Network s IQ 16

17 LS-1 Family Integrated Services Router I/O Controller Home Media Hub Robotic Material Handling Feature Layerscape architecture for advanced packet processing Advanced ARM Cortex v7 cores for optimized performance/power Industry best security and IP forwarding performance in class Software and pin compatibility across familes Freescale Trust architecture Enabling smallest form factor fan-less design Highest level of integration below 3W 17

18 Integrates dual ARM Cortex-A7 cores up to 1 GHz each 5,000 CoreMark of performance under 3W Enables smallest form factor, fan-less designs Ideal migration path from MCU based designs QSPI, SATA, LCDC Optimized performance to power for networking applications, including: Low end routers Line cards Industrial automation slave devices Smart energy Networked media hubs 18

19 New Accelerating the Network s IQ The industry s first software-aware, coreagnostic networking architecture delivers unprecedented efficiency and scale for smarter, more capable network of tomorrow end to end. Our next-generation QorIQ platform offers: Exceptional performance and power efficiency Extreme programming flexibility Real-time deployment, configuration and management of the network Unparalleled portfolio breadth and scalability with continued innovation on Power Architecture cores and introduction of ARM cores 19

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