Introduction to Mechatronics. Fall Instructor: Professor Charles Ume. Interrupts and Resets

Transcription

1 ME645 Introduction to Mechatronics Fall 24 Instructor: Professor Charles Ume Interrupts and Resets

2 Reason for Interrupts You might want instructions executed immediately after internal request and/or request from peripheral devices when certain condition are met. Interrupt provides way to temporarily suspend current program execution in order to execute certain set of tasks.

3 Methods of Checking for Requests There are two methods of checking when requests are made internally or from peripheral devices. Polling Interrupts

4 Polling An iterative approach which constantly checks devices for data Inefficient method for checking when input data has come in because no other instructions can be executed during polling process

5 Interrupts Communication between CPU and I/O devices can be established with issue of interrupt request NOTE: Request can be issued at any time CPU suspends execution of main program, until instructions in Interrupt Service Routine (ISR) are completely executed Returns to main program after ISR is completed

6 Types of Interrupts There are two types of interrupts. Maskable Non-Maskable

7 Maskable Interrupts 5 Maskable Interrupts Two types of Masking Local Interrupt enable bit Global I-bit in CCR Follows a default priority arrangement Any one interrupt can be promoted to higher priority using HPRIO register. IRQ 2. Real-Time Interrupt 3. Timer Input Capture 4. Timer Input Capture2 5. Timer Input Capture3 6. Timer Output Compare 7. Timer Output Compare 2 8. Timer Output Compare 3 9. Timer Output Compare 4. Timer Input Capture 4/Output Compare 5. Timer Overflow 2. Pulse Accumulator Overflow 3. Pulse Accumulator Input Edge 4. SPI transfer Complete 5. SCI system

8 Maskable Interrupts: IRQ Input IRQ pin provides additional external interrupting source IRQE bit in Options Register used to configure IRQ for Edge-Sensitive-Only Operation IRQE = IRQ is configured for level sensitive Operation IRQE = IRQ is configured for edge-sensitive-only Operation

9 Maskable Interrupts: Peripheral Subsystems Interrupts from Internal Peripheral Subsystems Flag bit, which is set after action takes place Interrupt enable bit, which enables flag to generate interrupt service

10 Interrupt Priority: Maskable Maskable Interrupts Priority. IRQ 2. Real Time Interrupt 3. Timer Input Capture 4. Timer Input Capture 2 5. Timer Input Capture 3 6. Timer Output Compare 7. Timer Output Compare 2 8. Timer Output Compare 3 9. Timer Output Compare 4. Timer Input Capture4/Output Compare 5. Timer Overflow 2. Pulse Accumulator Overflow 3. Pulse Accumulator Input Edge 4. SPI Transfer Complete 5. SCI System Any can be assigned the highest maskable interrupt priority...

11 HPRIO Register for Maskable Interrupts Used to elevate priority of any one maskable interrupt Default is IRQ Set using bits -3 of HPRIO (Highest Priority Interrupt Register) Can only be written when I-bit is set

12 HPRIO Register for Maskable Interrupts Address: $3C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit RBOOT SMOD MDA IRVNE PSEL3 PSEL2 PSEL PSEL RBOOT Read Bootstrap ROM Bit Has meaning when the SMOD bit is a SMOD Special Mode Select Bit Reflect inverse of the MODB input pin MDA Mode Select A Bit Reflects status of the MODA input pin IRVNE Internal Read Visibility/Not E Bit Allows internal read accesses on external bus in expanded mode Determines whether E-clock is driven out an external pin PSEL[3:] Priority Select Bits Selects one interrupts source to be elevated Can only be written while I-bit in the CCR is set

13 HPRIO register for Maskable Interrupts PSEL3 PSEL2 PSEL PSEL Interrupt Source Promoted Timer overflow Pulse accumulator overflow Pulse accumulator input edge SPI serial transfer complete SCI serial system Reserved (default to IRQ) IRQ (external pin or parallel I/O) Real-time interrupt Timer input capture Timer input capture 2 Timer input capture 3 Timer output compare Timer output compare 2 Timer output compare 3 Timer output compare 4 Timer input capture 4/output compare 5

14 HPRIO register for Maskable Interrupts Example: Set Timer Input Capture 3 to have the highest maskable priority Address: $3C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit Bit RBOOT SMOD MDA IRVNE PSEL3 PSEL2 PSEL PSEL

15 Non-Maskable Interrupts 6 Non-Maskable Interrupts Follows a default priority arrangement Interrupts are not subject to global masking. POR of RESET pin 2. Clock monitor reset 3. COP watchdog reset 4. XIRQ interrupt 5. Illegal opcode interrupt 6. Software interrupt (SWI)

16 Non-Maskable Interrupts: Illegal Opcode Generates interrupt request to illegal opcode vector Reinitializes stack pointer once interrupt service is completed Left un-initialized, illegal opcode vector can cause infinite loop causing stack underflow

17 Non-Maskable Interrupts: Software Interrupt Software instruction, thus cannot be interrupted until completed Uninhibited by global mask bits in the CCR Similar to other interrupts, sets I-bit upon servicing

18 Non-Maskable Interrupts: XIRQ Enabled by TAP instruction by clearing X-bit upon system initialization After being cleared, software cannot set X-bit, thus XIRQ is non-maskable Higher priority than any source maskable by I-bit Both X and I bits are automatically set by Reset or recognition of XIRQ interrupt RTI restores X and I bit to pre-interrupt states

19 Stacking Order when an Interrupt Occurs Memory Location SP SP- SP-2 SP-3 SP-4 SP-5 SP-6 SP-7 SP-8 CPU Registers PCL PCH IYL IYH IXL IXH ACCA ACCB CCR Last value to be pulled from stack

20 Interrupt Vectors Each type of interrupt has associated vector addresses Vector addresses change depending on whether ROMON is Enabled or Disabled This has to do with Buffalo refer to lecture #4 With ROMON enabled, each vector is set of addresses which contain both Jump (JMP ie 7E) statement, and starting address of interrupt subroutine (ISR)

21 Interrupt Vector Table: ROMON Disabled Vector Address Interrupt Source CCR Mask Bit Local Mask FFC, C FFD4, D5 Reserved - - FFD6, D7 SCI receive data register full SCI receiver overrun SCI transmit data register empty SCI transmit complete SCI idle line detect I RIE RIE TIE TCIE ILIE FFD8, D9 SPI serial transfer complete I SPIE FFDA,DB Pulse accumulator input edge I PAII FFDC, DD Pulse accumulator overflow I PAOVI FFDE, DF Timer overflow I TOI FFE, E Timer IC4/OC5 I I4/O5I FFE2, E3 Timer output compare 4 I OC4I FFE4, E5 Timer output compare 3 I OC3I FFE6, E7 Timer output compare 2 I OC2I FFE8, E9 Timer output compare I OCI FFEA, EB Timer input capture 3 I IC3I FFEC, ED Timer input capture 2 I IC2I FFEE, EF Timer input capture I ICI FFF, F Real-time interrupt I RTII FFF2, F3 IRQ (external pin) I None FFF4, F5 XIRQ pin X None FFF6, F7 Software interrupt None None FFF8, F9 Illegal opcode trap None None FFFA, FB COP failure None NOCOP FFFC, FD Clock monitor fail None CME FFFE, FF RESET None None

22 ROMON Disabled Interrupt vector addresses are usually occupied by Buffalo With ROMON disabled, only starting ISR address must be programmed in vector address

23 Interrupt Vector Table: ROMON Enabled Vector Address Interrupt Source CCR Mask Bit Local Mask C4-C6 SCI receive data register full SCI receiver overrun SCI transmit data register empty SCI transmit complete SCI idle line detect - - RIE RIE TIE I TCIE ILIE C7-C9 SPI serial transfer complete I SPIE CA-CC Pulse accumulator input edge I PAII CD-CF Pulse accumulator overflow I PAOVI D-D2 Timer overflow I TOI D3-D5 Timer IC4/OC5 I I4/O5I D6-D8 Timer output compare 4 I OC4I D9-DB Timer output compare 3 I OC3I DC-DE Timer output compare 2 I OC2I DF-E Timer output compare I OCI E2-E4 Timer input capture 3 I IC3I E5-E7 Timer input capture 2 I IC2I E8-EA Timer input capture I ICI EB-ED Real-time interrupt I RTII EE-F IRQ (external pin) I None F-F3 XIRQ pin X None F4-F6 Software interrupt None None F7-F9 Illegal opcode trap None None FA-FC COP failure None NOCOP FD-FF Clock monitor fail None CME

24 ROMON Enabled Buffalo is active READ ONLY MEMORY(ROM) In this case you must write the jump command ($7E) to the first byte of the vector address The remaining two bytes write the starting location of your ISR

25 Interrupt Flow Interrupt condition is met A B YES Global Masking Analyze Priority ISR instruction YES NO Local Masking Set (I) or (X) to prohibit another Interrupt RTI YES NO NO Complete Current Instruction Store all registers on the Stack Standard Interrupt Table Load Address in appropriate vector Clear I or X bit in CCR Restore Registers w/ org. Values Continue Program A B Note: Local mask must be cleared prior to performing RTI

26 Elapsed Time Example ME645 Write a routine to interrupt the MC68HC after msec of elapsed time (Assume E= Mhz, Prescaler = ) ORG $4 LDD #$FFFF /*Delays any OC3 compares*/ STD TOC3 /*Set output compare to the longest time so that you would not have output compare occurring when you are initializing*/ OR SEI /*Set I-bit to prevent interrupt service during set-up*/ LDAA #BIT5HI /* BIT5HI = %*/ STAA TFLG /* Clear previously set OC3 Flag*/ STAA TMSKI /* Enable OC3 Interrupt */ LDAB #$3 STAB TCTL /* OC3 will be high for a successful compare */ LDAA #JUMP /* JUMP = $7E */ STAA FIRSTAD /* FIRSTAD = $D9 */ LDX #OC3ISR /* OC3ISR = $D, 2 bytes- beginning address of interrupt service routine*/ STX SECONDAD /* SECONDAD = $DA, This will cause the high byte ($DO) of the service routine address to be stored in location $DA and the low byte ($) to be stored in $DB */ LDD TCNT ADDD #DLYIOMS /* DLYIOMS = $27 = */ STD TOC3 /* IF not done elsewhere */ Introduction to to Mechatronics, Georgia Georgia Tech Tech CLI /* Clear I bit */

27 Write a routine to interrupt the MC68HC after msec of elapsed time (Assume E= Mhz, Prescaler = ) ORG $4 LDD #$FFFF /*Delays any OC3 compares*/ STD TOC3 /*Set output compare to the longest time so that you would not have output compare occurring when you are initializing*/ OR SEI /*Set I-bit to prevent interrupt service during set-up*/ LDAA #BIT5HI /* BIT5HI = %*/ STAA TFLG /* Clear previously set OC3 Flag*/ STAA TMSKI /* Enable OC3 Interrupt */ LDAB #$3 STAB TCTL /* OC3 will be high for a successful compare */ LDD TCNT ADDD #DLYIOMS /* DLYIOMS = $27 = */ STD TOC3 /* IF not done elsewhere */ CLI /* Clear I bit */. SWI END Elapsed Time Example Alternative ORG $D9 JMP OC3ISR

28 Example: Timer Overflow Interrupt TFLG2 EQU $25 *Timer Interrupt Flag 2 TMSK2 EQU $24 *Timer Interrupt Mask 2 TOVISR EQU $5 *ISR memory location PROGRAM EQU $4 STRING EQU $2 OUTSTRG EQU $FFC7 VECTOR EQU $D ORG STRING FCC 'TICK' FCB $4 ORG PROGRAM *Set I-bit to prevent interrupt service during set-up SEI LDAA #$8 STAA TMSK2 *TOF Interrupt Enabled STAA TFLG2 *Clears TOF Interrupt Flag LDAA #$7E *JMP STAA VECTOR *Stores JMP to vector LDX #TOVISR *Loads register X with #5 *Stores content of register X to address Vector incremented STX VECTOR+ CLR $ CLI * Clears I-bit to allow servicing of interrupt LOOP BRA LOOP SWI *Software Interrupt End ORG TOVISR LDAA $ * Loads address $ content INCA *Increment by STAA $ *Stores value back to address CMPA #3 *Compares value to decimal 3 BNE A *Loads index register X with content of STRING LDX #STRING JSR OUTSTRG CLR $ *Clear address A LDAA #$8 *Loads binary STAA TFLG2 *Clears local flag RTI Pre-interrupt service set-up

29 Resets Forces the MCU to: assume set of initial conditions begin executing instructions at predetermined starting address.

30 Resets Like interrupts, resets share concept of vector fetching to force new starting point for further CPU operations. In contrast to interrupts, resets stop completely execution of set of instructions. As well, they always rest MCU hardware.

31 Sources of Resets Power on Reset (POR) External Reset (RESET) Computer Operating Properly (COP) Reset Clock Monitor Reset

32 Power-On Resets Power-On Reset (POR) Used only for power-up conditions to initialize MCU internal circuits. Applying Vdd to MCU triggers POR circuit, initiates reset sequence, and starts internal timing circuit. 464 clock cycle delay after oscillator becomes active, allows clock generator to stabilize.

33 External Reset System reset can also be forced by applying low level to RESET pin. External source must hold pin low for more than 4 cycles. If this happens, pin is further sampled 2 cycles after Low level at sampling instant indicates that reset has been caused by external device.

34 Computer Operating Properly Reset Protects against software failures When enabled, software to keep free- running watchdog timer from timing out is activated System reset is initiated when software stops executing in the intended sequence

35 COP Reset continued COP is enabled or disabled by setting NOCOP bit in CONFIG register. To change status of COP system, contents of CONFIG register are changed and system reset is initiated. COP timer rate is controlled in OPTION Register. The system E-clock is divided by 2^5 and further scaled by, 2 and 4.

36 Clock Monitor Reset Clock Monitor Reset circuit is based on internal resistor capacitor time delay. If no MCU clock edges are detected within this RC time delay, clock monitor, if set by CME control bit, would generate system reset.

37 How the MPU Distinguishes between Internal and External Resets MPU senses whether reset pin rises to logic within two E-clock cycles after internal device releases reset. When reset condition is sensed, RESET pin is driven low by internal device for 4 E-clock cycles, then released. Two E-clock cycles later, it is sampled. If pin is still held low, CPU assumes that external reset has occurred. If pin is high, it indicates that reset was internally initiated.

38 Occurrence of Reset Affects CPU Memory Map Timer Real-time Interrupt Pulse Accumulator SPI ADC System COP SCI

39 Process Flow out of Resets When Reset is triggered Vector fetch (Program counter loaded with contents of specified address) S, X and I bits set in CCR MCU hardware reset Checks for interrupts

40 Standby Modes Suspends CPU operation until reset or interrupt occurs Used to reduce power consumption Two standby modes: WAIT STOP

41 Standby Modes: WAIT Opcode (WAI) Suspends CPU processing CPU registers are stacked On-chip crystal oscillator remains active Exit WAIT mode through external IRQ, XIRQ, or any internally generated interrupts

42 Standby Modes: STOP If S-bit in the CCR is, CPU goes into stop mode Else, opcode is treated as NOP All clocks stopped internal peripherals stopped Retains data in Internal RAM if V DD is maintained CPU state and I/O pin levels are static Exit STOP mode through external interrupts, pending edge-triggered IRQ or RESET pin

43 Standby Modes: STOP Recovering through XIRQ X-bit is clear Returns to stacking sequence leading to normal XIRQ request X-bit is set Returns to instruction immediately following STOP instruction

44 Questions???