Input/Output Modes Chapter 8

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1 Input/Output Modes Chapter 8 Microcomputers can communicate with a variety of I/O devices This information can be either data or control Data is usually encoded in numeric or alphanumeric forms such as binary, BCD, and ASCII Control is usually one of several types, such as commands from the MPU, service requests from I/O devices, control codes from the MPU or status codes from I/O devices Roberto Muscedere Images and Text Portions 2003 Prentice Hall 1

2 Input/Output Modes I/O involves the transmission of data from one device to another Sender, transmitter, or source sends the data Receiver or destination receives the data Sender may use a DAV or Data Available signal to let the device know that it is ready The receiver may send back a DACK or Data Acknowledged signal to let the sender know the information was received Known as hardware handshaking Roberto Muscedere Images and Text Portions 2003 Prentice Hall 2

3 Input/Output Modes I/O transfers can be initiated in many ways The MPU may do so either: Unconditionally, the device is always ready for a transfer Conditionally, the device must be asked if it is ready for the transfer Roberto Muscedere Images and Text Portions 2003 Prentice Hall 3

4 Input/Output Modes The device may initiate the transfer as well It can do so by using: An interrupt Requesting the MPU to look at some result from the device A DMA or Direct Memory Access MPU is disabled and external circuit has access to full memory 68HC11 does not support this Roberto Muscedere Images and Text Portions 2003 Prentice Hall 4

5 Input/Output Modes MPU Initiated Unconditional Transfer Circuit was seen before Reads from $8004 gets the status of switches while writes to $8000 enable/disable Light Emitting Diodes (LEDs) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 5

6 Input/Output Modes MPU Initiated Conditional Transfer The MPU begins the transfer, but must wait for the device to finish An example of this is an A/D converter Must wait t c time before data is available Some devices may have a ready flag when completed (EOC) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 6

7 Complete 68HC11 Block Diagram Functional Diagram Has 5 ports: A, B, C, D, and E B and C are reserved in expanded mode, but can be used for parallel hardware handshaking Roberto Muscedere Images and Text Portions 2003 Prentice Hall 7

8 Data Converters All physical signals exist in analog form Binary is an analog signal; however, we commonly exclude it from analog terminology We can perform analog processing on signals; however, it is sometimes more attractive to use economical digital ICs to perform the same types of processing algorithms (if not better ones) Digital Signal Processing (DSP) Microcontrollers Roberto Muscedere Images and Text Portions 2003 Prentice Hall 8

9 Data Converters In order to use digital processing effectively, we need to move information from the analog domain into the digital domain (binary) To convert analog signals to digital numbers, we use an analog-to-digital converter (A-to-D, A/D converter, ADC) Once we have processed this information, we may need to move the digital data back into analog form To convert digital numbers back to analog signals, we use a digital-to-analog converter (D-to-A, D/A converter, DAC) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 9

10 Sampling of Analog Signals DSP relies on the sampling of analog signals A switch closes periodically under the control of a periodic clock The switch is closed for a short period of time and the samples are stored (held) on the capacitor This is a sample-and-hold circuit We sample the data during the hold intervals Output is fed to an A/D converter Roberto Muscedere Images and Text Portions 2003 Prentice Hall 10

11 Signal Quantization Consider an analog signal between 0 and 10V Assume we wish to convert this to a 4-bit binary value (0 to 15) Our resolution will then be 10/15V or 2/3V, therefore: 0V will be represented as /3V will be represented as V will be represented as V will be represented as V could be represented as 1001 or 1010, but will be 1001 as it is closer to 6V This adjustment is known as quantization This error in coding is known as quantization error Using more bits for the digital representation reduces this error Roberto Muscedere Images and Text Portions 2003 Prentice Hall 11

12 D-to-A Conversion In order to produce smooth analog signals, the output of a DAC is fed to a sample and hold circuit and then goes through a low pass filter (eliminate high-frequency transitions) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 12

13 Functional Blocks In schematic form, we use functional blocks to describe ADCs and DACs Analog signal is v A Digital signal width depends on accuracy of the converters (N) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 13

14 A/D Converter Circuits (Feedback type Converter) Uses a DAC! Comparator has a single bit output, v A >v O or v A <v O Up/down counter changes v O based on comparison Process continues until DAC output is very close to input (comparator output oscillates) Slower converter, low bit resolution (8-10 bits), economical (microcontrollers) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 14

A/D Converter Circuits (Parallel or Flash Converter) Utilizes 2 N -1 comparators to compare the input signal to the 2 N -1 possible quantization levels The outputs of the comparators are fed into an

15 A/D Converter Circuits (Parallel or Flash Converter) Utilizes 2 N -1 comparators to compare the input signal to the 2 N -1 possible quantization levels The outputs of the comparators are fed into an encoding block, which outputs the digital word Very fast (hundreds of megahertz, one clock cycle), low bit resolution (10-12 bits), and expensive (complex circuits) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 15

A/D Conversion 68HC11 Port E is used for either input or for A/D conversion $1039 Bit 7 (ADPU) enables the A/D Bit 6 (CSEL) selects which clock generator to use, E- clock (0) or built in RC (1) $1030

16 A/D Conversion 68HC11 Port E is used for either input or for A/D conversion $1039 Bit 7 (ADPU) enables the A/D Bit 6 (CSEL) selects which clock generator to use, E- clock (0) or built in RC (1) $1030 Bit 7 (CCF) indicates when a conversion is done Bit 5 (SCAN) is set to continuously convert signals Bit 4 (MULT) is set to convert multiple signals Bit 3-0 select which input to convert (when MULT=0) Roberto Muscedere Images and Text Portions 2003 Prentice Hall 16

17 A/D Conversion 68HC11 Conversion is performed 4 times, either on the same input or on 4 in sequence 32 E-clocks are required for each conversion 128 total E-clocks are used for one full conversion round Roberto Muscedere Images and Text Portions 2003 Prentice Hall 17

18 Device Initiated Transfers - Interrupts Interrupts are the preferred method for transferring data to and from devices Polling (or waiting) can consume a significant amount of CPU resources May miss something when MPU is handling other requests Roberto Muscedere Images and Text Portions 2003 Prentice Hall 18

19 Device Initiated Transfers - Interrupts When an interrupt occurs, the MPU automatically pushes the PC, IY, IX, ACCA, ACCB and CCR onto the stack It then proceeds to the ISR location Once a RTI instruction is reached, the MPU pops all previous registers and PC off the stack to continue prior operation Roberto Muscedere Images and Text Portions 2003 Prentice Hall 19

20 Interrupts /XIRQ is active low /IRQ can be programmed to be active low, or falling edge sensitive by setting bit 5 (IRQE) of $1039 /IRQ interrupts can be disabled by using SEI and enabled by using CLI /XIRQ can only be disabled in the first 64 E-clocks of the MPU /XIRQ can be initiated by a power-failure Roberto Muscedere Images and Text Portions 2003 Prentice Hall 20

others are generated by internal microcontroller components

21 Interrupts The address of all ISR is in upper memory starting at $FFC0 Only /IRQ and /XIRQ are generated externally while most others are generated by internal microcontroller components Roberto Muscedere Images and Text Portions 2003 Prentice Hall 21

22 Interrupts Interrupts can be interrupted (another interrupt occurs in the ISR) if I=0 (CCR) See figure When an interrupt occurs, I (CCR) is set to 1 in ISR automatically Set to avoid signal bouncing Roberto Muscedere Images and Text Portions 2003 Prentice Hall 22

23 Multiple Interrupts Multiple devices share a single interrupt line A secondary line (or other method) is later polled in the ISR to determine the true source of the interrupt Roberto Muscedere Images and Text Portions 2003 Prentice Hall 23

Port A is used for either I/O or for pulse accumulation or input capture and output compare As an I/O port, 5 pins are outputs and 3 are inputs (default)

24 Port A is used for either I/O or for pulse accumulation or input capture and output compare As an I/O port, 5 pins are outputs and 3 are inputs (default) Controlled by $1021, $1022 & $1026 $1000 (PORTA) Each bit corresponds to I/O pin Port A 68HC Roberto Muscedere Images and Text Portions 2003 Prentice Hall 24

25 Port A 68HC11 Bit 7 of Port A can be used as a pulse accumulator $1027 Increments based on settings of next register $1026 PAEN enables pulse accumulation PAMOD & PEDGE set the external events required to increment counter Remaining bits control alternative functions Roberto Muscedere Images and Text Portions 2003 Prentice Hall 25

26 Port A 68HC11 First 4 pins can be used as an input capture (one is shared with output compare) $1021 (TCTL2) Select the mode of capture (which edge) When event occurs, free running timer is copied to TIC1-3 ($1010-$1015) $1022 (TMSK1) Selects which capture will generate an interrupt $1023 (TFLG1) Write a 1 here to clear the interrupt so it can occur again Roberto Muscedere Images and Text Portions 2003 Prentice Hall 26

Port A 68HC11 Other pins can be used as an output compare When the free running timer equals one of the output compares ($1016-$101F), the corresponding output pin is changed $1020 (TCTL1) Select the

27 Port A 68HC11 Other pins can be used as an output compare When the free running timer equals one of the output compares ($1016-$101F), the corresponding output pin is changed $1020 (TCTL1) Select the action of the compare $1022 (TMSK1) Selects which compare will generate an interrupt $1023 (TFLG1) Write a 1 here to clear the interrupt so it can occur again Roberto Muscedere Images and Text Portions 2003 Prentice Hall 27

Roberto Muscedere Images and Text Portions 2003 Prentice Hall 1

Roberto Muscedere Images and Text Portions 2003 Prentice Hall 1 Microcomputer Structure and Operation Chapter 5 A Microprocessor ( P) contains the controller, ALU and internal registers A Microcomputer ( C) contains a microprocessor, memory (RAM, ROM, etc), input and