Interrupts. How can we synchronize with a peripheral? Polling

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1 Interrupts How can we synchronize with a peripheral? Polling run a program loop continually checking status of the peripheral wait for it to be ready for us to communicate with it Then handle I/O with the peripheral Multiple devices need to check devices serially Polling version 1 - read data from peripheral Main loop processing while PeripheralDataNotReady unrelated processing ReadFrom:Peripheral processing based on data end

2 Polling version 2 - read data from peripheral (no busy wait) Main loop processing if PeripheralDataReady ReadFrom:Peripheral processing based on data other processing end Problems with polling May be stuck busy waiting More likely significant overhead incurred to check status Program structure gets messy and littered with status checks Often long and highly variable latency on servicing of peripheral requests (need to wait until other processing completed) Interrupts can help alleviate these problems

3 What is an interrupt? An input to a processor that temporarily redirects program flow (assumption - this is review of COSC2021) An asynchronous event that suspends normal processing and temporarily diverts the flow of control through an "interrupt handler" routine. (hyperdictionary.com) Caused by signals external or internal to the CPU External interrupts typically generated by external hardware (peripherals) Internal interrupts Exceptions such as divide by zero Software interrupt sources Generally, processor halts execution and runs a interrupt handler or interrupt service routine (ISR) to process the event generating the interrupt These are common and critical components of embedded systems

4 Interrupt Service Routine Typically, interrupt hardware (usually on chip) is initialised by software at start-up On receiving interrupt processor Saves program counter and system state Acknowledge interrupt. Determine appropriate interrupt service routine (e.g. vectored interrupts) Processor branches to address of interrupt service routine ISR must handle event that caused the interrupt and return On return from interrupt, restore system state and resume execution from interrupted instruction Superficially similar to other eventdriven programming but events detected in hardware during execution of instructions Interrupt priority If several interrupts are pending need to decide which to service If interrupt is being serviced do we interrupt it to service another? Useful to prioritise interrupts Fixed Programmable Round-robin

5 Higher priority interrupt serviced before lower HCS12 priorities (see data sheet) Resets (highest) Unimplemented instruction trap SWI (trap) External hardware interrupts XIRQ, IRQ Various peripherals in a default order One peripheral can be set to highest priority through HPRIO register Interrupt masking Often useful to selectively enable interrupts Two-level control is common: global mask and mask of individual bits In HCS12 I bit in CCR enables maskable interrupts - IRQ and peripherals X bit enables XIRQ Peripherals have control bit that enable individual interrupts SWI not maskable Vectored interrupts: An interrupt scheme where the interrupting device identifies itself when generating interrupts (and is associated with one of a table of ISR s) Avoids polling possible devices to determine origin of the interrupt Used by HCS12

6 HCS12 interrupt processing If enabled, an interrupt request can be recognized at any time after the I mask bit is cleared. CPU responds at the completion of the instruction being executed. Interrupt latency varies according to the number of cycles required to complete the current instruction. After the CCR is stacked, the I bit (and the X bit for XIRQ ISR) is set to prevent other interrupts. Execution continues at the vectored address for the highest-priority pending interrupt. At the end of the ISR, an RTI instruction restores context from the stacked registers returns to interrupted routine.

7 Why use interrupts? Coordinate asynchronous processing or events Handle exceptions, task switching, event handling Efficiency - allow other processing to continue while waiting for an event (as opposed to a busy wait) Low latency response to external events Interrupt timing implications Interrupts incur some overhead - recognizing source, saving of PC and CPU registers, return from interrupt Latency to servicing interrupts can be variable and depend on order and timing of interrupts low priority interrupts may occasionally have long latency May be critical problem in hard-real time system ISR Guidelines Keep track of timing budget for ISRs and prioritise and code accordingly Keep ISRs short (in time) and simple - use separate tasks to handle complex or non-essential processing

8 To reduce latency of other ISRs reenable interrupts as soon as possible in ISR after hardware critical and nonreentrant parts ISRs can have side effects - watch critical code segments Hardware interrupt signals Level-sensitive Generates an interrupt if the interrupt line is the active state Susceptible to stuck interrupt failures (repeatedly generating interrupts) Amenable to sharing, daisy chaining interrupt lines Edge sensitive Interrupt generated on transition of interrupt signal Ideal for interrupts without explicit acknowledge Harder to share lines

9 Assembler Example (Huang) Need to set up interrupt vector table org $FF80 fdb default_isr; defensive fdb oc7_isr ; output compare 7 Initialise peripheral hardware movb #$80,tscr ; enable timer, timer runs during wait ;state, and while in ; background mode, also clear flags normally clr tmsk1 ; disable all output compare interrupts movb #$80,tios ; select channel 7 to act as output compare movb #$2B,tmsk2 ; set the timer counter prescale factor to 8 ; and reset tcnt o successful oc 7 event movb #$00,pactl ; choose timer prescaler clock as timer ; counter clock ; Interrupt handler oc7_isr: bclr tflg1,$7f ; clear c7f flag dec oc7_cnt rti Metrowerks C timer example Initialise interrupt table extern void near _Startup(void); /* Startup routine */ extern void near RTI_ISR(void); #pragma CODE_SEG NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ interrupt void UnimplementedISR(void) { /* Unimplemented ISRs trap.*/ asm BGND; typedef void (*near tisrfunc)(void); const tisrfunc = { /* Interrupt table */ UnimplementedISR, /* vector 63 */ UnimplementedISR, /* vector 62 */ UnimplementedISR, /* vector 61 */ UnimplementedISR, /* vector 60 */ UnimplementedISR, /* vector 59 */

10 ; /* more of these for */ UnimplementedISR, /* vector 08 */ RTI_ISR, /* vector 07 */ UnimplementedISR, /* vector 06 */ UnimplementedISR, /* vector 05 */ UnimplementedISR, /* vector 04 */ UnimplementedISR, /* vector 03 */ UnimplementedISR, /* vector 02 */ UnimplementedISR, /* vector 01 */ _Startup /* Reset vector */ Initialize RTI timer, enable interrupts /* these defines are in hidef.h file */ #define EnableInterrupts { asm CLI; #define DisableInterrupts { asm SEI; absolutetime = 0; /* setup of the RTI interrupt frequency */ /* adjusted to get 1 millisecond (1.024 ms) with 16 MHz oscillator */ RTICTL = 0x1F; /* set RTI prescaler */ CRGINT = 0x80; /* enable RTI interrupts */ EnableInterrupts; RTI interrupt handler #pragma CODE_SEG NEAR_SEG NON_BANKED interrupt void RTI_ISR(void) { absolutetime++; /* clear RTIF bit */ CRGFLG = 0x80;

11 Entire Main program #include <hidef.h> /* PORTB definitions */ #define PORTB (*((volatile unsigned char*)(0x0001))) #define DDRB (*((volatile unsigned char*)(0x0003))) /* RTI definitions */ #define CRGINT (*((volatile unsigned char*)(0x0038))) #define CRGFLG (*((volatile unsigned char*)(0x0037))) #define RTICTL (*((volatile unsigned char*)(0x003b))) /* global variables definitions */ static int waittime = 5; static long absolutetime = 0; static void setnextsegment(void){ static unsigned char seg = 0; static const char segs[]={~0x01,~0x02,~0x04,~0x08,~0x10,~0x20; seg++; if (seg == 6) { seg = 0; PORTB = segs[seg]; #pragma CODE_SEG NEAR_SEG NON_BANKED interrupt void RTI_ISR(void) { absolutetime++; /* clear RTIF bit */ CRGFLG = 0x80; #pragma CODE_SEG DEFAULT static void RTIInit(void) { /* setup of the RTI interrupt frequency */ /* adjusted to get 1 millisecond (1.024 ms) with 16 MHz oscillator */ RTICTL = 0x1F; /* set RTI prescaler */ CRGINT = 0x80; /* enable RTI interrupts */ static void starttimebase(void){ absolutetime = 0; RTIInit(); EnableInterrupts; static void wait(long ms){ long timeout; timeout = absolutetime + ms; while (timeout!= absolutetime) { asm NOP; /* asm WAI; */ /* will be waken up by the RTI exception. Not well supported in BDM mode */ void main(void) { DDRB = 0xFF; starttimebase(); for (;;){ setnextsegment(); wait(waittime * 100);

12 D-BUG12 ISRs D-BUG12 provides default ISRs in EVB mode The function SetUserVector() allows the user to substitute their own interrupt service routines by means of a RAM based interrupt vector table int SetUserVector (int VectNum, Address UserAddress); Pointer Address: $EEA4 Each of the 64 entries in the table consists of a two byte address with the table beginning at $3E00. For user ISR Store a value other than the default $0000 at the appropriate entry When associated interrupt occurs, interrupt service routine pointed to by this address is executed. D-BUG12 interrupts