SV3C DPRX MIPI D-PHY Analyzer. Data Sheet

Transcription

1 SV3C DPRX MIPI D-PHY Analyzer Data Sheet

2 Table of Contents Table of Contents Table of Contents... 1 List of Figures... 2 List of Tables... 2 Introduction... 3 Overview... 3 Key Benefits... 3 Applications... 3 Features... 4 Analyzer Block Diagrams... 4 PHY-Level Burst-Mode Raw Data Capture... 5 Packet Analysis and Lane Merging... 6 CSI-2 Video Frame Construction and Advanced BER Testing... 6 HS Termination Control... 8 Automation... 9 Physical Description and Pinout Specifications

3 Table of Contents List of Figures Figure 1 System-level block diagram of D-PHY Analyzer Figure 2 Receiver detail illustrating automatic termination switches Figure 3 Illustration of multi-packet, per lane PHY level data capture Figure 4 Illustration of triggered packet capture Figure 5 Packet analysis views in the SV3C DPRX: (a) complete listing of all packets received, (b) Python return variables for individual packet isolation and analysis Figure 6 Two constructed image frames using the SV3C DPRX. The DPRX offers a visual representation of erroneous packets (second image) to help correlate physical layer failures with protocol effects Figure 7 Basic concept of burst-mode BER measurement Figure 8 IntrospectESP software environment and example image captures using the Introspect tools. 9 Figure 9 Illustration of the SV3C DPRX D-PHY Analyzer connectors Figure 10 Illustration of the 240 pin Searay connector List of Tables Table 1 Summary of HS termination modes Table 2 Physical Dimensions Table 3 Listing of SV3C-DPRX D-PHY connectors Table 4 Mapping of SV3C-DPRX D-PHY MXP signals Table 5 General Specifications Table 6 Receiver Characteristics Table 7 Clocking Characteristics Table 8 Pattern Handling Characteristics

4 Introduction and Features Introduction Overview The SV3C-DPRX D-PHY Analyzer is an ultra-portable, high-performance instrument that enables exercising and validating MIPI D-PHY transmitter ports. Capable of analyzing any traffic and being completely data-rate agile, the D- PHY Analyzer includes complete hardware LP and HS receivers, dynamic termination, and offers sophisticated capture and compare modes. The D-PHY Analyzer operates using the highly versatile IntrospectESP Software environment. This environment allows for automating transmitter tests such as BER or protocol timings. This document includes electrical specifications. It also describes the block diagram of the D-PHY Analyzer and provides information about the various measurement and operating modes. Please refer to User Manual documentation for additional operating instructions. Key Benefits Any-rate operation Complete D-PHY receiver Burst-mode and continuous mode analysis Raw data capture as well as complete packet decode CSI-2 video frame extraction State of the art programming environment based on the highly intuitive Python language De-serialized parallel output (for FPGA prototyping) Reconfigurable, protocol customization (on request) Applications Parallel physical layer validation Interface test Plug-and-play system-level validation 3

5 Introduction and Features Features Analyzer Block Diagrams Figure 1 shows the overall connection diagram for the SV3C DPRX D-PHY Analyzer. As can be seen, the Analyzer is a complete integrated 4-lane receiver which contains the analog front-end circuitry for D-PHY as well as a complete protocol back-end. Specifically, referring to Figure 2, the SV3C DPRX front-end contains LP threshold voltage detectors, dynamically controlled D-PHY termination resistors, and fully differential HS receivers. Figure 1 System-level block diagram of D-PHY Analyzer. Figure 2 Receiver detail illustrating automatic termination switches. 4

6 Introduction and Features PHY-Level Burst-Mode Raw Data Capture To enable the deepest insight into all events in the transmitter under test, the SV3C DPRX is capable of performing deep raw captures on each lane individually. These captures are performed using an immediate capture command and are completely independent of any underlying protocol parameters. Referring to Figure 3, the Analyzer captures data as soon as it is commanded and fills up its entire memory buffer size specified by the user, potentially capturing multiple packets and multiple frames. The benefit of the immediate capture mode is that it allows for pattern learning or for detecting multiple non-deterministic / non-repetitive packets. Figure 3 Illustration of multi-packet, per lane PHY level data capture. For a more focused view of D-PHY global timing parameters, the SV3C DPRX offers a triggered packet capture operation. In this mode, the D-PHY Analyzer sets the termination resistors into automatic mode. Then, the analyzer waits for a valid LP to HS entry sequence before enabling a capture. If no valid HS-entry transition is detected, the capture returns an empty array. However, when a valid HS-entry transition is detected, the capture starts immediately. Completion of the capture happens at the earliest of two events: the appearance of the EOT sequence, or saturation of the capture memory buffer. For most packet sizes, the former condition (appearance of EOT) is what is observed. As such, the D-PHY analyzer produces a single record with a single SOT word and a single packet (burst) transmission. This is illustrated in Figure 4. Figure 4 Illustration of triggered packet capture. 5

7 Introduction and Features Packet Analysis and Lane Merging Through a software toggle, the SV3C DPRX performs autonomous packet analysis on received data, and it allows for identification (and isolation) of individual packets within a transmission. For example, it can enumerate short packets and long ones, and it provides sophisticated utilities for validating header information, ECC information, and Checksum values. Figure 5 shows two output formats out of the SV3C DPRX. In one, a complete listing of packets and packet analyses is provided in exportable formats; and in the other, Python return variables are offered for customizable packet analyses. For example, tools for detecting user-defined protocol commands can easily be constructed using the dynamic Python variables. Figure 5 Packet analysis views in the SV3C DPRX: (a) complete listing of all packets received, (b) Python return variables for individual packet isolation and analysis. CSI-2 Video Frame Construction and Advanced BER Testing Big-picture analysis is provided by the SV3C DPRX through additional CSI-2 image handling utilities. Referring to Figure 6, received frames are displayed in software (or saved for data logging). Most significantly, the SV3C DPRX attempts to display all video frames even if packets are improperly constructed or contain a lot of bit errors. This provides the ability to correlate low-level (or physical layer) BER failures with high level protocol behavior. 6

8 Introduction and Features Figure 6 Two constructed image frames using the SV3C DPRX. The DPRX offers a visual representation of erroneous packets (second image) to help correlate physical layer failures with protocol effects. 7

9 Introduction and Features Another fundamental feature of the SV3C-DPRX D-PHY Analyzer is burst-mode BER. It enables the measurement of realistic D-PHY transmissions from CSI generators or test chips. Referring to Figure 7, the Analyzer is able to ignore all signal waveforms (including LP) and only performs BER comparison on packet data that is transmitted between SOT and end of packet conditions. Figure 7 Basic concept of burst-mode BER measurement. HS Termination Control On power-up, the D-PHY Analyzer operates in automatic HS termination mode. In this mode, the termination is enabled for HS transmissions (after valid entry into HS) and disabled for LP transmissions. Detection of the LP transitions is based on the programmable threshold level lpthresholdvoltage. The termination can be forced enabled using the Immediate capture mode. Generally, termination can be switched between Auto mode and HS Only mode, and this is described in Table 1. Table 1 Summary of HS termination modes. Termination Mode Entry Condition Operation Supported Auto Power-up, IESP SW Continuous mode, burst mode HS Only IESP SW Continuous mode, burst mode 8

10 Introduction and Features Automation The SV3C DPRX D-PHY Analyzer is operated using the award winning IntrospectESP Software. It features a comprehensive scripting language with an intuitive component-based design as shown in the screen shot in Figure 8(a). Component-based design is Introspect ESP s way of organizing the flexibility of the instrument in a manner that allows for easy program development. It highlights to the user only the parameters that are needed for any given task, thus allowing program execution in a matter of minutes. Figure 8(b) shows sample video frames that are automatically detected and displayed using the analyzer. (a) (b) Figure 8 IntrospectESP software environment and example image captures using the Introspect tools. 9

11 Physical Description and Pinout Physical Description and Pinout Figure 9 shows a diagram of the SV3C DPRX physical connectors, and Figure 10 shows a view of the Searay connector on the left side of the SV3C DPRX system. The Searay connector is useful for interfacing to FPGA boards (e.g. providing deserialized D-PHY data from the analog front end of the SV3C DPRX) or for controlling devices under test. Figure 9 Illustration of the SV3C DPRX D-PHY Analyzer connectors. Figure 10 Illustration of the 240 pin Searay connector. 10

12 Physical Description and Pinout The physical dimensions and weight of the SV3C DPRX are shown in Table 2. Additionally, Table 3 provides a listing of the physical interfaces on the SV3C DPRX. The pinout for the RX Data Lanes and Clock Lane is provided in Table 4. Table 2 Physical Dimensions Parameter Length Width Height Weight Value 9.5 (241.3 mm) 4.25 ( mm) 1.3 (33.3 mm) 2 lb Table 3 Listing of SV3C-DPRX D-PHY connectors. Port / Indicator Name Connector Type 240 pin Searay Connector Samtec Connector Part Number CON-SAMTEC-SEAF L-06-2-RA-LP-TR Ref Clock In SMP Differential Pair Ref Clock Out A SMP Differential Pair Ref Clock Out B SMP Differential Pair Rx Data Lanes 1 4 MXP Rx Clock Lane MXP USB Port USB Power Switch / Connector AC Adapter provided (110V/220V, 50Hz/60Hz) Power dissipation <60 W Table 4 Mapping of SV3C-DPRX D-PHY MXP signals. Connector Pin Number Corresponding Rx Lanes 1,2 Lane 1 P, N 3,4 Lane 2 P, N 5,6 Lane 3 P, N 9,10 Lane 4 P, N 13,14 Clock Lane P, N 11

13 Specifications Specifications Table 5 General Specifications Parameter Value Units Description and Conditions Application / Protocol Support Physical layer interface MIPI protocol D-PHY CSI-2, DSI, Custom LP/HS Handling Automatic Tester automatically detects LP and HS data Ports Number of Receiver Lanes 4 Data + 1 Clock Number of Dedicated Clock Outputs 2 Separate clock for providing reference to the DUT Number of Dedicated Clock Inputs 1 Used as external Reference Clock input Number of Trigger Input Pins 3 Armed in software to trigger the start of specific measurements Number of Flag Output Pins 3 Armed in software to flag test completion or pass/fail criteria Data Rates and Frequencies Minimum Data Rate 500* Mbps * Extended minimum data rate under development Maximum Data Rate 3.125* Gbps * Extension to 4.5 Gbps under evaluation Minimum External Input Clock Frequency Maximum External Input Clock Frequency 10 MHz 250 MHz Minimum Output Clock Frequency 10 MHz Maximum Output Clock Frequency 250 MHz Output Clock Frequency Resolution 1 khz Supported External Input Clock I/O Standards Minimum LP State Period 25 ns Support for LVDS, LVPECL, CML, HCSL, and CMOS. 12

14 Specifications Table 6 Receiver Characteristics Parameter Value Units Description and Conditions Input Coupling HS Performance Input Impedance 50 Hi-Z Minimum Detectable Differential Voltage Maximum Allowable Differential Voltage Resolution Enhancement & Equalization 90 mv 600 mv Minimum DC Gain 0 db Maximum DC Gain 8 db DC Gain Control Equalization Control Timing Generator Performance Per-receiver Per-receiver Resolution at Maximum Data Rate mui Differential Non-Linearity Error +/- 0.5 LSB Integral Non-Linearity Error +/- 5 ps Range +/- 2 UI LP Voltage Threshold Controls Minimum Programmable Threshold Voltage Maximum Programmable Threshold Voltage -100 mv 1500 mv Threshold Voltage Resolution 1 mv Threshold Voltage Accuracy Larger of 5.0 mv or 2.0 % of programmed value Table 7 Clocking Characteristics Parameter Value Units Description and Conditions Internal Time Base Number of Internal Frequency References Frequency Resolution of Programmed Data Rate 1 1 Kbps 13

15 Specifications Table 8 Pattern Handling Characteristics Parameter Value Units Description and Conditions Preset Patterns Standard Built-In Patterns All Zeros D21.5 K28.5 K28.7 DIV.16 DIV.20 DIV.40 DIV.50 PRBS.5 PRBS.7 PRBS.9 PRBS.11 PRBS.13 PRBS.15 PRBS.18 PRBS.23 PRBS.31 User-programmable Pattern Memory Individual Expected Pattern Per-lane Minimum Pattern Segment Size 8 bits Total Memory Space for 4G Bytes Expected Patterns BERT Characteristics Maximum Packet Size Maximum Number of Packets Maximum Number of Repeats Maximum Time Between SOT in Burst Mode 1 ms Minimum Time Between SOT in TBD UI Burst Mode Capture Memory Depth 4G Bytes Additional Pattern Characteristics Escape Mode Command Detection Per Lane 14

16 Introspect Technology Revision Number History Date 1.0 Import from CPRX v1.1. June 7, Updated document template. June 3, 2015 The information in this document is subject to change without notice and should not be construed as a commitment by Introspect Technology. While reasonable precautions have been taken, Introspect Technology assumes no responsibility for any errors that may appear in this document. Introspect Technology, 2015 Published on June 3, 2015 EN-D004E-E-15154