Chapter 5 Embedded Soft Core Processors

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Abigayle Whitehead
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1 Embedded Soft Core Processors

2 Coarse Grained Architecture. The programmable gate array (PGA) has provided the opportunity for the design and implementation of a soft core processor in embedded design. Although the early coarse grained complex programmable logic device (CPLD) had limited capabilities and resources, soft core processors could still be implemented within their restricted structure. Figure 1.2 Simplified depiction of the Xilinx Spartan FPGA architecture

3 Fine Grained Architecture. The coarse gained CPLD is an assembly of macrocells and a programmable interconnection system without the benefit of the random access memory (RAM) of the recent fine grained PGA devices. Figure 1.3 Simplified depiction of a corner segment of the Xilinx Spartan -3E FPGA architecture

Xilinx EDK. The optional Xilinx Embedded Development Kit (EDK) supports the 32-bit MicroBlaze reduced instruction set computer (RISC) soft core processor.

4 Xilinx EDK. The optional Xilinx Embedded Development Kit (EDK) supports the 32-bit MicroBlaze reduced instruction set computer (RISC) soft core processor. The Xilinx EDK includes the Xilinx Platform Studio (XPS) and Software Development Kit (SDK) which have an integrated Development environment (IDE). GNU C/C++ compilers, debuggers and software utilities are provided for the MicroBlaze processor in the SDK.

5 Xilinx EDK. Support for the 32-bit MicroBlaze processor in the Xilinx EDK is extended to on-chip busing and operating systems (OS). The Xilinx Microkernel for the MicroBlaze processor is a modular library of nucleus system calls for OS services.

6 Xilinx EDK. The processor local bus (PLB), on-chip peripheral bus (OPB) and soft core peripherals facilitate the concept of the system on a chip (SOC) in embedded design.

7 Xilinx PicoBlaze. The Xilinx ISE WebPACK can be configured to provide an electronic design automation (EDA) environment for the 8-bit 8 PicoBlaze soft core processor, a separate download and installation procedure is required.

8 Xilinx PicoBlaze. Originally termed the Constant (k) Coded Programmable State Machine (KCPSM) (or more appropriately Ken Chapman s s Programmable State Machine after the Xilinx system designer who first implemented it) it is now called the Xilinx PicoBlaze.

9 Xilinx PicoBlaze EDK. The PicoBlaze processor EDA software tools as a partial EDK for the Spartan-3E field programmable gate array (FPGA) are downloaded as a ZIP archive file KCPSM3.zip and extracted to a working directory. ( Figure 5.1

10 Xilinx PicoBlaze EDK. The subfolders include an Assembler, Verilog files, a JTAG design file loader and a manual KCPSM3_Manual.pdf. The PicoBlaze processor is also described in a User Guide (UG129, Figure 5.1

11 Xilinx PicoBlaze EDK. The PicoBlaze processor is provided as a synthesizable Verilog hardware description language (HDL) module kcpsm3.v in the Verilog subfolder. The Verilog module embedded_kcpsm3.v instantiates the PicoBlaze processor in the Xilinx ISE WebPACK project and connects it to a Spartan-3E FPGA block RAM as program memory. Figure 5.2

12 Xilinx PicoBlaze DOS EDA. The KCPSM Assembler for the PicoBlaze processor executes in a DOS based environment in a Command Prompt window in Microsoft Windows XP and Vista.

13 Xilinx PicoBlaze DOS EDA. Note that DOS command line functions are used, such as dir for a directory listing, and names greater than eight characters or are truncated as in PICOBL~1 for PICOBLAZE in the directory tree.

14 Xilinx PicoBlaze DOS EDA. The files in the Assembler folder include the KCPSM3.EXE assembler. The assembled PicoBlaze processor program is stored in the block random access memory (RAM) of the Spartan-3E FPGA configured as read-only memory (ROM). Figure 5.4

15 Xilinx PicoBlaze DOS EDA. The extension for a PicoBlaze assembly language source file is.psm and the output is the instruction code Verilog module that replaces the ROM_form.v template which configures the block RAM. Figure 5.4

16 Xilinx PicoBlaze DOS EDA. The files KCPSM3.EXE, ROM_form.v and ROM_form.coe are copied into the Xilinx ISE WebPACK project directory. A Command Prompt or DOS box window can be opened and the PicoBlaze source file name.psm assembled with the command: kcpsm3 name.psm. Figure 5.4

17 Xilinx PicoBlaze DOS EDA. A PicoBlaze program is reconfigured by the auxiliary EDA software JTAG loader. The files in the JTAG_loader subfolder include the hex2svfsetup.exe, hex2svf.exe and svf2xsvf.exe, where SVF is the serial vector format protocol. Figure 5.5

18 Xilinx PicoBlaze DOS EDA. The hex2svfsetup.exe utility is used to describe the JTAG chain on the target hardware board and is executed once in a DOS Command Prompt window. Listing 5.1

19 Xilinx PicoBlaze DOS EDA. The input to the hex to SVF setup utility is the configuration of JTAG chain and the instruction length of the other devices in the chain. The instruction length can also be obtained from the IEEE standard boundary-scan description language (BSDL) file of the FPGA, CPLD or flash programmable read-only memory (PROM) device ( Figure 5.6

20 Xilinx PicoBlaze DOS EDA. A translation to a Xilinx SVF format is then performed by the utility svf2xsvf.exe by the DOS command: svf2xsvf newname.svf newname.xsvf. Finally, the transfer utility playxsvf.exe is used to download the new PicoBlaze design to the Spartan-3E FPGA by the DOS command: playxsvf name.xsvf. Figure 5.6

21 Xilinx PicoBlaze Architecture. The Xilinx PicoBlaze is an 8-bit 8 reduced instruction set computer (RISC) soft core processor optimized for efficiency and very low use of the available resources of the Xilinx field programmable gate arrays (FPGA). Figure 5.7

22 Xilinx PicoBlaze Architecture. The PicoBlaze processor does not require any external resources, such as random access memory (RAM) and uses only a minuscule 96 occupied slices and a single block RAM for program memory. Figure 5.7

23 Xilinx PicoBlaze Architecture. The PicoBlaze processor shows the use of 76 slice flip-flops flops (1%), input 4 LUTs (2%), 96 occupied slices (2%) and a total of equivalent gates in the XC3S500E Spartan-3E FPGA synthesis. Figure 5.7

24 Xilinx PicoBlaze Architecture. The PicoBlaze processor features 16 8-bit 8 general data registers and 1024 (1 K) 18- bit program locations typically using a single block RAM. Figure 5.7

25 Xilinx PicoBlaze Architecture. The PicoBlaze processor has an 8-bit 8 arithmetic logic unit (ALU), a 64 byte internal scratchpad RAM, 256 input and 256 output ports and a 31 location stack for subroutine call and return. Figure 5.7

26 Xilinx PicoBlaze Architecture. The 10-bit program counter (PC) addresses the 1 K program memory and indirect addressing is not supported. Figure 5.7

27 Xilinx PicoBlaze Architecture. Unlike several traditional microprocessor architectures, the Xilinx PicoBlaze processor does not have a specific accumulator and any of the general purpose registers can be utilized.

28 Xilinx PicoBlaze Architecture. The ALU provides addition, subtraction, arithmetic and bitwise compare and test and shift and rotate operations. ALU operations affect the zero and carry flags and interrupts can be enabled (IE). Figure 5.7

29 Xilinx PicoBlaze Architecture. The reset input (RESET) of the PicoBlaze processor sets the PC to 0, clears the zero and carry flags, disables interrupts and the sets the stack pointer to the top of the stack. Figure 5.7

30 Xilinx PicoBlaze IO. The input-output (IO) interface signals to and from the PicoBlaze processor demonstrates the usefulness of this architecture as a controller. The 8-bit input data port IN_PORT provides data on the rising edge of the clock with the INPUT instruction. Figure 5.8

31 Xilinx PicoBlaze IO. Data appears on the 8-bit 8 output port OUT_PORT for two clock cycles during the OUTPUT instruction. The input or output port address appears on the 8-bit 8 PORT_ID during the INPUT or OUTPUT instruction. Figure 5.8

32 Xilinx PicoBlaze IO. The INPUT and OUTPUT instructions can be either directly address as an 8-bit 8 immediate constant or indirectly addressed as the contents of any of the general purpose registers. Figure 5.8

33 Xilinx PicoBlaze IO. The READ_STROBE output when logic 1 indicates that the input data was captured and the WRITE_STROKE output when logic 1 indicates validates the output data. Figure 5.8

34 Xilinx PicoBlaze IO. The IO operations of the PicoBlaze processor are convenient to use as a controller or finite state machine (FSM) for low speed peripherals in an embedded design, such as the liquid crystal display (LCD) or auxiliary PS/2 mouse and keyboard of the Spartan-3E Starter Board. Figure 5.8

35 Xilinx PicoBlaze IO. The PicoBlaze processor operates at the maximum clock frequency of the Xilinx FPGA, which for the Spartan-3E (-4( 4 speed grade) FPGA is 88 MHz and utilizes two clock cycles per instruction. Figure 5.8

36 Xilkinx PicoBlaze IO. When used as a controller or FSM for low speed peripherals and processes in an embedded design the PicoBlaze can operate at a lower clock frequency which reduces idle clock cycles and lowers DC power consumption. The PicoBlaze processor is a fully static logic design and can actually operate down to DC. Figure 5.8

37 Xilinx PicoBlaze. The Xilinx PicoBlaze processor instruction set is more expansive that merely the INPUT and OUTPUT instructions. The instruction set is standard and includes add and subtract with and without the carry (borrow) flag for multiple byte arithmetic.

38 Xilinx PicoBlaze. The Xilinx PicoBlaze processor instruction set has unconditional and condition subroutine call and comparison and test of unaffected registers using the zero and carry flags and bitwise combination logic operations (AND, OR and XOR).

39 Xilinx PicoBlaze. The Xilinx PicoBlaze processor instruction set has store and fetch data to the scratchpad RAM, rotate and shift the general purpose registers and disabling or enabling and processing asynchronous interrupts.

40 Xilinx PicoBlaze. The extensive PicoBlaze processor User Guide (UG129, ) provides complete details of the architecture, interface signals, performance, assembler directives and EDA software tools.

41 Xilinx PicoBlaze. The performance of an embedded design using a soft core processor can be maximized if multiple PicoBlaze processors partition the IO tasks and coordinate their operation using semaphores implemented with the input and output ports.

42 Xilinx PicoBlaze. The reduced number of IO ports on a single PicoBlaze processor then simplifies the input data multiplexing and decoding of the 8-bit 8 IO address. If only one or two IO ports are needed, then no multiplexing or decoding is necessary.

43 Xilinx PicoBlaze. If eight or less IO ports are used, then a single input multiplexer for binary encoding of IN_PORT and an efficient one-hot encoding of OUT_PORT is required.

44 Xilinx PicoBlaze. An innovative application in embedded design is to use the PicoBlaze processor as an on-chip test and debugging processor. The rapid download of new PicoBlaze soft-core processor code using the JTAG loader without resynthesizing the FPGA hardware provides a means of inputting a new test vector to verify the performance of the logic.

45 Xilinx PicoBlaze Reference Projects. The programmable amplifier (PA) and analog-to to-digital converter (ADC) Xilinx PicoBlaze reference project for the Spartan-3E Starter Board is available as a ZIP archive file. The DOS batch file install_picoblaze_amp_ adc_ control.bat opens a DOS Command Prompt window and runs the Xilinx ISE impact programming tool to download the project. Figure 5.11

46 Xilinx PicoBlaze Reference Projects. The PA-ADC ADC Xilinx PicoBlaze project initializes the PA and the LCD, initiates an analog signal conversion to digital data by the ADC, reads the data using the serial peripheral interface (SPI) bus and displays the results on the LCD. Figure 5.12

47 Xilinx PicoBlaze Reference Projects. The PA-ADC ADC Xilinx PicoBlaze project initializes the PA and the LCD, initiates an analog signal conversion to digital data by the ADC, reads the data using the serial peripheral interface (SPI) bus and displays the results on the LCD. Figure 5.12

48 Xilinx PicoBlaze Reference Projects. The digital-to to-analog converter (DAC) Xilinx PicoBlaze reference project for the Spartan-3E Starter Board is available as a ZIP archive file. The DOS batch file install_picoblaze_dac_control.bat opens a DOS Command Prompt window and runs the Xilinx ISE impact programming tool to download the project. Figure 5.13

49 Xilinx PicoBlaze Reference Projects. The DAC Xilinx PicoBlaze project initiates a four channel digital data transfer using the SPI bus to the DAC, conversion and outputting the four analog signals by the DAC. Figure 5.14 Figure 5.15

50 Xilinx PicoBlaze Reference Projects. The DAC Xilinx PicoBlaze project outputs a 2 khz square wave on DAC A, 200 Hz triangle wave on DAC B, another 2 khz square wave on DAC C and an approximate 770 Hz sine wave on DAC D. Figure 5.14 Figure 5.15

51 Xilinx PicoBlaze Reference Projects. The PicoBlaze processor is interrupted to generate the four analog signal outputs every 125 µsec or an 8 khz sampling rate Figure 5.14 Figure 5.15

52 Xilinx PicoBlaze Reference Projects. An equivalent Verilog HDL project is the top module s3esincosdtmf.v which generates a dual-tone multiple frequency (DTMF) audio signal using the Xilinx CORE Sine-Cosine Look-Up Table LogiCORE block. In that project the rate Figure 4.24 of the sinusoidal tone generation is at the design maximum of the DAC of the Spartan-3E Starter Board of 1.47 Msamples /sec.

Xilinx PicoBlaze Reference Projects. The frequency generator Xilinx PicoBlaze reference project for the Spartan-3E Starter Board is available as a ZIP archive file.

53 Xilinx PicoBlaze Reference Projects. The frequency generator Xilinx PicoBlaze reference project for the Spartan-3E Starter Board is available as a ZIP archive file. The DOS batch file install_frequency_generator.bat opens a DOS Command Prompt window and runs the Xilinx ISE impact programming tool to download the project. Figure 5.16

54 Xilinx PicoBlaze Reference Projects. The frequency generator Xilinx PicoBlaze reference project uses a configured DDS circuit, rather than the Xilinx CORE Generator DDS LogiCORE block, to output a square wave at a frequency of 1 Hz to approximately 100 MHz. The rotary shaft encoder and the LEDs to provide an editor that can modify the individual output frequency digit values. Figure 5.17

Xilinx PicoBlaze Reference Projects. The frequency counter Xilinx PicoBlaze reference project for the Spartan-3E Starter Board is available as a ZIP archive file.

55 Xilinx PicoBlaze Reference Projects. The frequency counter Xilinx PicoBlaze reference project for the Spartan-3E Starter Board is available as a ZIP archive file. The DOS batch file install_frequency_generator.bat opens a DOS Command Prompt window and runs the Xilinx ISE impact programming tool to download the project. Figure 5.18

56 Xilinx PicoBlaze Reference Projects. The Xilinx PicoBlaze project initial display selects one of four input signals used to the frequency counter. The reference clock oscillator for the frequency counter is the nominal 50 MHz crystal clock oscillator on the Spartan-3E Starter Board. Figure 5.19 Figure 5.20

57 Xilinx PicoBlaze Reference Projects. The pulse width modulation (PWM) and control Xilinx PicoBlaze reference project for the Spartan-3E Starter Board is available as a ZIP archive file. The DOS batch file install_ picoblaze_ pwm_control.bat opens a DOS Command Prompt window and runs the Xilinx ISE impact programming tool to download the project. Figure 5.21

58 Xilinx PicoBlaze Reference Projects. The first two channels of the eight channel output of the PWM Xilinx PicoBlaze project is shown. The pulse period is 1 msec and the approximate duty cycle for channel 1 is 10% and that of channel 2 is 75%. Figure 5.22

59 Xilinx PicoBlaze Reference Projects. The PWM Xilinx PicoBlaze project has a data throughput rate that is a function of the number of channels, the pulse width resolution and the pulse frequency or = Figure 5.22

60 Xilinx PicoBlaze Reference Projects. Although the PicoBlaze can utilize an 88 MHz clock, the highest clock frequency available for the XC3S500E (-4( 4 speed) Spartan-3E FPGA, the soft core processor uses the 50 MHz crystal oscillator of the Spartan-3E Starter Board. Figure 5.22

61 Xilinx PicoBlaze Reference Projects. The PicoBlaze soft core processor requires two clock cycles per instruction or an instruction period of 40 nsec. Therefore in the µsec available between a PWM step only about 97 PicoBlaze processor instructions can be executed. Figure 5.22

62 Xilinx PicoBlaze Reference Projects. Although the PWM process here requires only approximately half of the available instructions, if either the channels, resolution or pulse frequency is doubled, the number of instructions available is halved and the PicoBlaze soft core processor could not perform the real-time task. This is certainly problematic for all sequential processors such as the PicoBlaze. Figure 5.22

63 Soft Core Processors. Both the Xilinx 8-bit 8 PicoBlaze soft core processor and the Verilog HDL controller and datapath construct can utilize soft core peripherals to augment their performance and functionality in an embedded design.

64 Soft Core Processors. However, the Xilinx LogiCORE blocks often require more than 8-bits 8 of data. External latches and logic would be required to interface the PicoBlaze soft core processor.

65 Soft Core Processors. Other soft core peripherals are quite comparable with the Xilinx 8-bit 8 PicoBlaze soft core processor. The soft core universal asynchronous receiver transmitter (UART) can be used to provide RS-232 standard serial data communication in an embedded design.

66 Soft Core Processors. Alternatively, the Verilog HDL controller and datapath construct is readily extensible and interfacing to a LogiCORE block is therefore not so problematic.

67 Soft Core Processors. The Xilinx MicroBlaze 32-bit RISC soft core processor can conveniently interface to the Xilinx LogiCORE blocks and Xilinx and third-party Output Peripheral Bus (OPB) soft core peripheral devices.

68 Soft Core Processors. The Xilinx PicoBlaze soft core processor and the Verilog HDL controller and datapath construct can also interact synergistically through the interface. An embedded design then would consist of processing elements appropriate for the task.

69 Soft Core Processors. Nevertheless, the Verilog HDL controller and datapath construct is seemingly more suited to high throughput internal soft peripherals and external hard peripherals, such as a digital-to to-analog converter (DAC) and an analog-to to- digital converter (ADC) in a wavefront digital signal processing (DSP) systems.

70 End of Embedded Soft Core Processors

Agenda. PicoBlaze Hello World project using the PicoBlaze. Class 9 Copyright 2011 Greg Tumbush Ver 1.0 1

Agenda. PicoBlaze Hello World project using the PicoBlaze. Class 9 Copyright 2011 Greg Tumbush Ver 1.0 1 Agenda PicoBlaze Hello World project using the PicoBlaze Class 9 Copyright 2011 Greg Tumbush Ver 1.0 1 Embedded Processor Why? Firmware is easier to maintain/modify/deploy If the constraints of you system