Delft-Java Dynamic Translation

Transcription

1 Delft-Java Dynamic Translation John Glossner 1,2 and Stamatis Vassiliadis 2 1 IBM Research DSP and Embedded Computing Yorktown Heights, NY glossner@us.ibm.com (formerly with Lucent Technologies) 2 Delft University of Technology CARDIT - Computer Architecture and Digital Technique Delft, The Netherlands {glossner,stamatis}@cardit.et.tudelft.nl

2 Overview Java Properties Delft-Java Engine Dynamic Translation Indirect Register Access Translated Instructions Non-translated Instructions Results Related Work Conclusions

3 Java Properties Object-Oriented Programming Language Inheritance and Polymorphism Supported Programmer Supplied Parallelism (Threads) Dynamically Linked Resolved C++ s fragile class problem but imposes performance constraints on class access Entire set of objects in system not required at compile time Strongly Typed Statically determinable type state enables simple on-the-fly translation of bytecodes into efficient machine code [Gos95] Compiled to Platform Independent Virtual Machine

4 Delft-Java Engine RISC-style Architecture 32-bit Instructions Multiple Register Files Concurrent Multithreaded Organization Multiple Hdwr Thread Units Multiple Instruction Issue Per Thread Indirect Register Access Supervisory Instructions Branch Java View (bex) Integer & Floating Point 8, 16, 32, and 64-bit Signed & Unsigned Integers IEEE-754 Floating Point Multimedia Instructions SIMD Parallelism DSP Arithmetic Extensions Saturation Logic Rounding Modes 32-bit Address Space Base + Offset + Displacement

5 Java Hardware Support Transparent Extraction of Parallelism Multiple concurrent thread units Dynamic Java Instruction Translation Register file caches stack with indirect access JVM Reserved Instruction Used For BEX Link Translation Buffer For Dynamic Linking Associates a caller s object reference and constant pool entry ID with a linked object invocation Logical Controller For Non-Supported Translations Thin interpretive layer and Java run-time

6 Delft-Java Organization

7 Indirect Access idx[7] o o o Resolved Registers idx[1] idx[0] ix iy it Post / pre update IsJava imm imm imm adjust Overflow / Underflow Update Offset Register

8 Register Mapping Resolved Register Register File r31 r30 r29 O O O r0 Tags V A L I D M O D I F I E D Main Memory r31 r30 r29 Stack llimit displacement offset Base address + O O O r0 Stack ulimit

9 Java Dynamic Translation Step 1: Translate Java instr To Indirect Instruction iadd translates to add.ind.w32 idx[7] ++it, it, ++it idx[7] is an index into the register file Step 2: Translate Indirect To Direct Instruction if idx[7].rt = 20, then translated instruction becomes: add.w32 r21, r20, r21 ; (r21=r20 + r21) In Java-mode, ix, iy, and it are locked together. In native-mode, they are free to contain independent offsets for Vector operations.

10 Vector Multiply class VectorMultiply { public static final int MAXVEC = 100; public static void main( String[] args ) { int[] a,b,c; a = new int[maxvec]; b = new int[maxvec]; c = new int[maxvec]; for( int i=0; i<maxvec; i++ ) { // Init Arrays a[i] = i; b[i] = 2*i; c[i] = 0; } for( int i=0; i<maxvec; i++ ) { c[i] = a[i] * b[i] }}}

11 Compiled Inner Loop 1 a_3 ; address of c[0] on heap 2 i 5 ; index into c[] 3 a_1 ; address of a[0] 4 i 5 ; index into a[] 5 ia ; element from a[index] 6 a_2 ; address of b[0] 7 i 5 ; index into b[] 8 ia ; element from b[index] 9 imul ; multiple a[i]*b[i] 10 iastore ; store it into c[index]

12 Translated Bytecode Opcode mpy store [idx7] [idx7] [idx7] [idx7] [idx7] [idx7] [idx7] [idx7] [idx7] [idx7] Indirect Register --it, base_lv + #3 --it, base_lv + #5 --it, base_lv + #1 --it, base_lv + #5 ++it, ++it + it --it, base_lv + #2 --it, base_lv + #5 ++it, ++it + it ++it, it, ++it 2+it + 1+it, it

13 DJ Executed Instructions Opcode mpy store Direct Register Initial value of idx[7] = 24 r23 <- Mem[base_LV + #3] r22 <- Mem[base_LV + #5] r21 <- Mem[base_LV + #1] r20 <- Mem[base_LV + #5] r21 <- Mem[r21 + r20] r20 <- Mem[base_LV + #2] r19 <- Mem[base_LV + #5] r20 <- Mem[r20 + r19] r21 <- r20 * r21 Mem[r23 + r22] <- r21

14 Translated Instructions anewarray arraylength athrow checkcast getfield getstatic goto_w 1 instanceof invokeinterface 1 invokespecial invokestatic invokevirtual jsr_w 1 lookupswitch 1 monitorenter monitorexit multianewarray new newarray putfield putstatic tableswitch wide 1 (traps) These instructions have special hardware support All other instructions are transparently translated

15 Model Characteristics IS: Ideal Stack Does not remove stack bottlenecks IX: Ideal Translated Uses Delft-Java Translation Multiple Issue (inorder) No Renaming IR: Ideal Translated with Renaming Out-of-order multiple issue PS: Pipelined Stack Pipeline Latency of 4 Cycles for Memory Pipeline Latency of 1 Cycle for Arithmetic No Delft-Java Translation PX: Pipelined Stack with Translation Model IS IX IR PS PX PR Rename No No Yes No No Yes Issue Inorder Inorder OOO Inorder Inorder OOO L/S Units ` ` ` ` ` ` Latency In-order Multiple Issue PR: Pipelined Translation and Renaming BR Yes OOO 2LV/2H 4 Out-of-order Multiple Issue BR: Bounded Resource PR 2 Concurrent Memory Space Accesses

16 Results PS (Pipelined Stack) Chosen as Basis for Comparison A potentially realizable implementation IS (Ideal Stack) is 3.5x faster than PS (Pipelined Stack) Stack Bottlenecks were reduced by 40% with the IX (Ideal Translated) model versus the IS (Ideal Stack) model. When Register Renaming was applied (IR model), stack bottlenecks were reduced 60%. Bounded Resources (BR) still performed 3.2x better than the pipelined stack. Register renaming with out-of-order execution successfully enhanced performance by 50% Model IS IX IR PS PX PR BR Peak Issue IPC Speedup

17 Results IS: Ideal Stack Does not remove stack bottlenecks IX: Ideal Translated Uses Delft-Java Translation Speedup Multiple Issue (inorder) 8 No Renaming IR: Ideal Translated with Renaming Out-of-order multiple issue PS: Pipelined Stack Pipeline Latency of 4 Cycles for Memory Pipeline Latency of 1 Cycle for Arithmetic No Delft-Java Translation PX: Pipelined Stack with Translation In-order Multiple Issue IS IX IR PS PX PR BR PR: Pipelined Translation and Renaming Out-of-order Multiple Issue 0 Vector Multiply BR: Bounded Resource PR 2 Concurrent Memory Space Accesses

18 Comparison Sun picojava Direct Execution Stack Cache Implemented with registers Automatic stack spill/fill Acceleration instruction folding Instruction and Data Cache Global L1 Extended bytecodes Complex instructions trap Contiguous Stack Frame Delft-Java Dynamic Translation Translated to RISC instructions Indirect register access Runtime register allocation Acceleration compounding instruction issue multiple thread units Link Translation Buffer Instruction and Data Cache Global L1 Cache Per thread L0 Instruction, Stack, Local Variable Cache Superset of instructions (w/ BEX) Complex instructions trap Contiguous Stack Frame

19 Comparison Tomasulo Dynamic Scheduling Munsil and Wang, 1998 Reduced Stack usage Stack Folding Sun, 1998 Chang, et. al Detect true dependencies in instruction stream and execute as single compound instruction Similar to our 1997 collapsing ALU technique. Virtual Registers Li, et. al., 1998 Allows arithmetic instructions to obtain source operands from a virtual register which may reference operands below the top of the stack. Multiple instructions can be issued in parallel Similar to our 1997 translation technique

20 Conclusion Dynamic Translation A form of hardware register allocation Transform stack bottlenecks into pipeline dependencies Pipeline dependencies are removed using superscalar techniques 3.2x speedup achieved over a pipelined stack model Up to 60% of stack bottlenecks removed For translated instruction streams, out-of-order execution realized a 50% performance improvement when compared with in-order execution