The University of Adelaide, School of Computer Science 13 September 2018

Transcription

1 Computer Architecture A Quantitative Approach, Sixth Edition Chapter 2 Memory Hierarchy Design 1 Programmers want unlimited amounts of memory with low latency Fast memory technology is more expensive per bit than slower memory Solution: organize memory system into a hierarchy Entire addressable memory space available in largest, slowest memory Incrementally smaller and faster memories, each containing a subset of the memory below it, proceed in steps up toward the processor Temporal and spatial locality insures that nearly all references can be found in smaller memories Gives the allusion of a large, fast memory being presented to the processor Memory Hierarchy 2 3 Chapter 2 Instructions: Language of the Computer 1

2 Memory Performance Gap Memory Hierarchy Design Memory hierarchy design becomes more crucial with recent multi-core processors: Aggregate peak bandwidth grows with # cores: Intel Core i7 can generate two references per core per clock Four cores and 3.2 GHz clock 25.6 billion 64-bit data references/second billion 128-bit instruction references/second = GB/s! DRAM bandwidth is only 8% of this (34.1 GB/s) Requires: Multi-port, pipelined caches Two levels of cache per core Shared third-level cache on chip Dynamic RAM One transistor Data stored as charge on a capacitor Leaks need refreshing Bit line Switching element Word line Storage element Chapter 2 Instructions: Language of the Computer 2

3 Dynamic RAM m+n n m Row Decoder Static RAM 2 n x 2 m array Sense amplifier +MUX Cross coupled inverters (2 transistor each) + 2 access transistor bit line bit line Row select 7 8 memory Would like a memory that is fast, big and cheap. Hierarchy of memories (multi-level caches, main memory, disk). How to manage the data? Where to put it and who is responsible for moving it? Manual: The programmer does that Automatic: The system does that. 9 Chapter 2 Instructions: Language of the Computer 3

4 Memory Hierarchy Core L1 Cache L2 Cache L3 Cache RAM 1-4 cycles DISK 10 cycles $I $D 30 cycles cycles 10 Performance and Power High-end microprocessors have >10 MB on-chip cache Consumes large amount of area and power budget 11 Locality Temporal Locality When you access a specific address, you will probably access the same address soon Spatial Locality When you access a specific address, nearby addresses will be accessed soon (more for instruction that data) 12 Chapter 2 Instructions: Language of the Computer 4

5 Performance and Power A Block: The smallest unit of information transferred between two levels. Hit: Item is found in some block in the upper level (example: Block X) Miss: Item needs to be retrieved from a block in the lower level (Block Y) Miss Rate = 1 - (Hit Rate) Miss Penalty: Time to replace a block in the upper level + Time to deliver the block the processor 13 When a word is not found in the cache, a miss occurs: Fetch word from lower level in hierarchy, requiring a higher latency reference Lower level may be another cache or the main memory When you move a word, get the nearby ones. 14 When a word is not found in the cache, a miss occurs: Fetch word from lower level in hierarchy, requiring a higher latency reference Also fetch the other words contained within the block Takes advantage of spatial locality Place block into cache in any location within its set, determined by address block address MOD number of sets in cache 15 Chapter 2 Instructions: Language of the Computer 5

6 n sets => n-way set associative Direct-mapped cache => one block per set Fully associative => one set Writing to cache: two strategies Write-through Immediately update lower levels of hierarchy Write-back Only update lower levels of hierarchy when an updated block is replaced Both strategies use write buffer to make writes asynchronous 16 Miss rate Fraction of cache access that result in a miss Causes of misses Compulsory First reference to a block Capacity Blocks discarded and later retrieved Conflict Program makes repeated references to multiple addresses from different blocks that map to the same location in the cache 17 Speculative and multithreaded processors may execute other instructions during a miss Reduces performance impact of misses 18 Chapter 2 Instructions: Language of the Computer 6

7 Six basic cache optimizations: Larger block size Reduces compulsory misses Increases capacity and conflict misses, increases miss penalty Larger total cache capacity to reduce miss rate Increases hit time, increases power consumption Higher associativity Reduces conflict misses Increases hit time, increases power consumption Higher number of cache levels Reduces overall memory access time Giving priority to read misses over writes Reduces miss penalty Avoiding address translation in cache indexing Reduces hit time 19 Dynamic RAM Data stored by charging/discharging a capacitor. One access transistor One capacitor Charges leak, data will be lost in a second Must refresh Cheap row enable Memory Architecture bitline 20 Static RAM Two cross coupled inverters(4 transistors) 2 access transistors Memory Architecture row select bitline _bitline 21 Chapter 2 Instructions: Language of the Computer 7

8 Memory Technology and Optimizations Performance metrics Latency is concern of cache Bandwidth is concern of multiprocessors and I/O Access time Time between read request and when desired word arrives Cycle time Minimum time between unrelated requests to memory Memory Technology and Optimizations SRAM memory has low latency, use for cache Organize DRAM chips into many banks for high bandwidth, use for main memory 22 Memory Technology SRAM Requires low power to retain bit Requires 6 transistors/bit DRAM Must be re-written after being read Must also be periodically refeshed Every ~ 8 ms (roughly 5% of time) Each row can be refreshed simultaneously One transistor/bit Address lines are multiplexed: Upper half of address: row access strobe (RAS) Lower half of address: column access strobe (CAS) cache Memory Organization Technology and Optimizations Placement Direct mapped cache Cache Memory 24 Chapter 2 Instructions: Language of the Computer 8

9 placement -- DM 1K = 1024 Blocks Each block = one word Can cache up to 2 32 bytes = 4 GB of memory Hit Byte offset Byte address Tag Index In de x Valid Tag Data 0 1 Data 2 Mapping function: Cache Block frame number = (Block address) MOD (1024) i.e. index field or 10 low bit of block address Block Address = 30 bits Tag = 20 bits Index = 10 bits Block offset = 2 bits 25 Placement -- DM Address (showing bit positions) Byte 12 Hit Tag o ffset Ind ex 16 bits 128 bits V Tag Data Block offset Data 4K entries Mux 32 Block Address = 28 bits Tag = 16 bits Index = 12 bits Block offset = 4 bits 26 Placement -- DM Each block frame in cache has an address tag. The tags of every cache block that might contain the required data are checked in parallel. A valid bit is added to the tag to indicate whether this entry contains a valid address. The address from the CPU to cache is divided into: A block address, further divided into: An index field to choose a block set in cache. (no index field when fully associative). A tag field to search and match addresses in the selected set. A block offset to select the data from the block. Tag Block Address Index Block Offset 27 Chapter 2 Instructions: Language of the Computer 9

10 Placement -- DM Physical Memory Address Generated by CPU Tag Block Address Index Block Offset Block offset size = log2(block size) Index size = log2(total number of blocks/associativity) Tag size = address size - index size - offset size Mapping function: Cache set or block frame number = Index = Number of Sets = (Block Address) MOD (Number of Sets) 28 Set Associative 4KB 4-way 1024 block frames Each block = one word 4-way set associative 1024 / 4= 256 sets Can cache up to 2 32 bytes = 4 GB of memory Index V Tag Address Data V Tag Data V Tag Data V Tag Data Block Address = 30 bits Tag = 22 bits Index = 8 bits Block offset = 2 bits 4-to-1 m ultiplexor Mapping Function: Cache Set Number = index= (Block address) MOD (256) Hit Data 29 Placement -- DM 30 Chapter 2 Instructions: Language of the Computer 10