802.3bj FEC Overview and Status. 1x400G vs 4x100G FEC Implications DRAFT. IEEE P802.3bs 400 Gb/s Ethernet Task Force. Bill Wilkie Xilinx

Transcription

1 802.3bj FEC Overview and Status 1x400G vs 4x100G FEC Implications DRAFT IEEE P802.3bs 400 Gb/s Ethernet Task Force July 2015 Hawaii Bill Wilkie Xilinx

2 Introduction This presentation takes a look at the differences in implementation of a 1x400G and a 4x100G FEC architecture The implementation types/styles are just some valid options, there are many ways to implement each architecture The sizing data presented is a combination of real design data and the results from micro architecture analysis and extrapolation Page 2

3 Data Rates These bus widths, clock frequencies and data rates are investigated in this presentation 425Gbps RS(544,514) Encoding Input Input Data Rate Input Width Nominal Input Clock Frequency Cycles per RS Codeword Gbps 257/256 Transcoding KP4 400Gbps FPGA 425Gbps MHz 4.25 FPGA RS Decoder Gbps MHz 4 Payload data 400Gbps KP4 400Gbps ASIC 425Gbps MHz 8.5 ASIC RS Decoder Gbps MHz 8 Page 3

4 4x 100G KP4 Datapath: 340-bit Decoder Current FPGA appropriate bus widths and clock frequencies Uses free running local clock for most of the circuitry Running off a local clock with periodic gaps eases design issues with unstable clocks Gearboxing from 320b to 340b is essentially free since this logic is used for alignment, re-ordering etc. Recovered clock MHz 17:16 duty cycle takes care of clock ppm variation. 17 th clock cycle not used unless recovered clock is faster than fixed clock, in which case it will occasionally be used. If recovered clock is slower then extra dead cycles are inserted here. Fixed clock MHz Gbps 4x Gbps SerDes MHz 320-bit lock & Deskew + gearbox 340-bit RS Decode 340-bit Descramble Transcode & removal + gearbox 330-bit 400Gbps Rest of PCS Size = T 100 Size = A 100 Size = D 100 Gearbox ~63% of T 100 x4 Page 4

5 100G Transcode Gearboxing: 340-bit Decoder Gearbox complexity is high for this option 340 Decode 340 Transcode 330 PU1 PU2 5*264 -> 330*4 Gearbox 5*264 -> 330*4 5*264 -> 330*4 Buffer input mux is 16:1 PU1 Gearbox mux is 16:1 PU2 Gearbox mux is 4:1 Output gearbox needed.to convert from 5*264 to 4*330 5*264 -> 330*4 PU1 idle 1/17 PU2 idle 13/17 Gearbox = parity Complex gearbox + 2 Processing Units (PU) Page 5

6 4x 100G KP4 332MHz Datapath: 320-bit Decoder Current FPGA appropriate bus widths and clock frequencies Uses recovered clock for all of the circuitry No gearbox required on lock and De-skew Recovered clock MHz 17:17 duty cycle 17:16 duty cycle Gbps 4x Gbps SerDes MHz 320-bit lock & Deskew 320-bit RS Decode 320-bit Descramble Transcode & removal + gearbox 330-bit 400Gbps Rest of PCS Size = A 100 Size = D 100 Size = T 100 Gearbox ~63% of T 100 x4 Page 6

7 100G Transcode Gearboxing: 320-bit Decoder Gearbox complexity is high for this option, similar to the 340b decoder 320 Decode 320 Transcode /17 17/17 PU1 PU2 5*264 -> 330*4 Gearbox 5*264 -> 330*4 5*264 -> 330*4 5*264 -> 330*4 Gearbox = parity PU1 idle 1/17 PU2 idle 13/17 Page 7

8 4x 100G KP4 Datapath: 170-bit Decoder Current ASIC and future FPGA appropriate bus widths and clock frequencies Uses free running local clock for most of the circuitry Running off a local clock with periodic gaps eases design issues with unstable clocks Gearboxing from 160b to 170b is essentially free since this logic is used for alignment, re-ordering etc. Recovered clock MHz 17:16 duty cycle takes care of clock ppm variation. 17 th clock cycle not used unless recovered clock is faster than fixed clock, in which case it will occasionally be used. If recovered clock is slower then extra dead cycles are inserted here. Fixed clock MHz Gbps 4x Gbps SerDes MHz 160-bit lock & Deskew + gearbox 170-bit RS Decode 170-bit Descramble Transcode & removal + gearbox 165-bit 400Gbps Rest of PCS Size = A 100A Size = D 100A x4 Size = T 100A Gearbox ~63% of T 100 Page 8

9 100G Transcode Gearboxing: 170-bit Decoder Gearbox complexity is high for this option 170 Decode 170 Transcode 165 Lane Distribution 5*33 5*264 -> 165*8 Gearbox 5*264 -> 165*8 5*264 -> 165*8 Buffer input mux is 31:1 PU Gearbox is 20:1 mux Output gearbox needed.to convert from 5*264 to 8*165 5*264 -> 165*8 PU Idle 14/34 Gearbox = parity Very complex gearbox + 1 Processing Unit XILINX CONFIDENTIAL.

10 4x 100G KP4 664MHz Datapath: 160-bit Decoder Current ASIC and future FPGA appropriate bus widths and clock frequencies Uses recovered clock for all of the circuitry Drawback of dealing with a potentially unstable clock No gearbox required on lock and De-skew Recovered clock MHz 17:17 duty cycle 17:16 duty cycle Gbps 4x Gbps SerDes MHz 160-bit lock & Deskew 160-bit RS Decode 160-bit Descramble Transcode & removal + gearbox 165-bit 400Gbps Rest of PCS Size = A 100A Size = D 100A x4 Size = T 100A Gearbox ~88% of T 100A Page 10

11 100G Transcode Gearboxing: 160-bit Decoder Gearbox complexity is high for this option 160 Decode 160 Transcode /17 17/17 Gearbox 5*264 -> 165*8 5*264 -> 165*8 5*264 -> 165*8 Buffer input mux is 33:1 PU Gearbox is 20:1 mux Output gearbox needed.to convert from 5*264 to 8*165 5*264 -> 165*8 = parity PU Idle 14/34 Very complex gearbox + 1 Processing Unit Gearbox Page 11

12 1x400G KP4 332MHz Datapath Current FPGA appropriate bus widths and clock frequencies Uses free running local clock for most of the circuitry Running off a local clock with periodic gaps easies design issues with unstable clocks Gearboxing from 1280b to 1360b is essentially free since this logic is used for alignment, re-ordering etc. 17:16 duty cycle takes care of clock ppm variation Recovered clock MHz Fixed clock MHz Transcode: 257 in, 264 out 425Gbps 16x Gbps 1280-bit lock & Deskew 1360-bit RS Decode Gbps gearbox 332MHz 1360-bit Descramble Transcode & removal + gearbox 1320-bit Rest of PCS 400Gbps Size = A 400 = 4xA 100 Size = D 400 = 4xD 100 Size = T 400 = 1.35xT 100 Gearbox ~30% of T 400 Page 12

13 1x400G Transcode Gearboxing: 1360-bit Decoder Low complexity gearboxing for this option 5* RS Decode 1360 Parity Removal 1285 Transcode 1320 PU1 PU2 PU3 PU4 PU5 1 RS Codeword 4 cycles of 1360 bits 4 cycles of 1285 bits Buffer input mux is 4:1 Gearbox mux is 4:1 No output gearbox needed. = parity bits Simple gearbox + 5 Processing Units (PU), busy 100% of the time Page 13

14 1x400G KP4 664MHz Datapath Current ASIC and future FPGA appropriate bus widths and clock frequencies Uses free running local clock for most of the circuitry Running off a local clock with periodic gaps easies design issues with unstable clocks Gearboxing from 640b to 680b is essentially free since this logic is used for alignment, re-ordering etc. 17:16 duty cycle takes care of clock ppm variation Recovered clock MHz Fixed clock MHz Transcode: 257 in, 264 out 425Gbps 16x Gbps lock & Deskew 680-bit RS Decode gearbox Gbps 664MHz 680-bit Descramble Transcode & removal + gearbox 660-bit Rest of PCS 400Gbps Size = A 400A = 4xA 100A Size = D 400A = 3.7xD 100A Size = T 400A = T 100A Gearbox ~57% of T 400A Page 14

15 400G Transcode Gearboxing: 680-bit Decoder Medium complexity gearboxing for this option 680 Decode 680 Transcode 660 PU1 PU2 PU3 5*264 -> 2*660 5*264 -> 2*660 5*264 -> 2*660 1 RS Codeword 8 cycles of 680 bits Idle 1/17 Idle 1/17 Idle 9/17 Gearbox + 3 Processing Units 5*264 -> 2*660 Buffer input mux is 8:1 PU1 & PU2 gearbox mux s are 8:1 PU3 gearbox mux is 4:1 Output gearbox needed.to convert from 5*264 to 2*660 Page 15

16 Size Comparison: 332MHz Clock 4x100G (KP4) 100G RS Decoder, size = D G, lock and de-skew & gearboxes, size = A 100 ~= 0.131D G Transcode, alignment removal & gearboxes, size = T 100 ~= 0.094D 100 4x100G overall size = 4 * (D A T 100 ) ~= 4.9D 100 1x400G (KP4) 400G RS Decoder, size = D 400 ~= 4D G, lock and de-skew & gearboxes, size = A 400 ~= 4A G Transcode, alignment removal & gearboxes, size = T 400 ~= 1.35T G overall size = D A T 400 ~= 4.7D 100 Page 16

17 Size Comparison: 664MHz Clock 4x100G (KP4) 100G RS Decoder, size = D 100A 100G, lock and de-skew & gearboxes, size = A 100A ~= 0.187D 100A 100G Transcode, alignment removal & gearboxes, size = T 100A ~= 0.272D 100A 4x100G overall size = 4 * (D 100A + A 100A + T 100A ) ~= 5.84D 100A 1x400G (KP4) 400G RS Decoder, size = D 400A ~= 3.68D 100A 400G, lock and de-skew & gearboxes, size = A 400A ~= 4A 100A 400G Transcode, alignment removal & gearboxes, size = T 400A ~= 0.94T 100A 400G overall size = D 400A + A 400A + T 400A ~= 4.68D 100A Page 17

18 Conclusion Both 4x100G (KP4) and 1x400G (KP4) architectures are implementable in both current ASIC and FPGA technology Gearboxing on either side of the decoder is not a concern, the logic is already there to do this function as part of the other required functions A 1x400G FEC architecture has a small size advantage Page 18