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2 3 Volt Advanced+ Boot Block Flash Memory (C3) to Intel StrataFlash Memory (J3) Design Guide Application Note 74 December 2 Order Number:

3 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel's website at Copyright Intel Corporation, 2. *Other brands and names are the property of their respective owners.

4 Contents. Introduction.... C3 Overview....2 J3 Overview Feature Differences C3 Flexible Block Locking Locking Operation Locked State Unlocked State Lock-Down State Reading a Block s Lock Status Locking Operations during Erase Suspend Status Register Error Checking bit One Time Programmable Register Reading the Protection Register Programming the Protection Register Locking the Protection Register J3 Page Mode J3 Block Locking Configuration J3 Clear Block Lock-Bits Hardware Considerations C3 Pin Differences J3 Pin Differences Software Considerations System Implications J3 32-Byte Buffer C3 Automatic Power Savings Common User Interface Multi-Site Layout Summary...3 Appendix A The Bus Operations for the C3 and J Appendix B Word Programming/Suspend/Resume Flowcharts...36 Appendix C Erase/ Suspend/Resume Flowcharts...4 iii

5 Revision History Date of Revision Version Description 9/29/ - Original version iv

6 . Introduction Why would someone want the flexibility of using either the J3 or C3? The answer is one footprint accomodates -6M Bytes. The purpose of this application note is to enable versatile designs that can use either the 3 Volt Advanced+ Boot Block Memory (C3) or 3 Volt Intel StrataFlash Memory (J3). The 3 Volt Advanced + Boot Block Memory (C3) and the 3 Volt Intel StrataFlash Memory (J3) began on the same lithography (.25u), contain different technologies (single bit per cell vs. multilevel cell technology), and offer various features. Before we delve into the difference, let s look at the product overview for the C3 and J3.. C3 Overview Intel provides secure low voltage memory solutions with the Advanced Boot Block family of products. A new block-locking feature allows instant locking/unlocking of any block with zerolatency. A 28-bit protection register allows unique flash device identification. Discrete supply pins provide single voltage read, program, and erase capability at 2.7 V, while also allowing 2 V V PP for faster production programming. Improved 2 V, a new feature designed to reduce external logic, simplifies board designs when combining 2 V production programming with 2.7 V in-field programming. The 2 V programming feature should not be used in this multi-site layout. It is not available on the J3. The 3 Volt Advanced+ Boot Block flash memory products are available in x6 packages in the following densities: 8-Mbit (8,388,68 bit) flash memories organized as 52 Kwords of 6 bits each; or 6-Mbit (6,777,26 bit) flash memories organized as 24 Kwords of 6 bits each; or 32-Mbit (33,554,432 bit) flash memories organized as either 248 Kwords of 6 bits each. V CC Max for the 32-Mbit C3 is 3.3 V. Eight 4-Kword parameter blocks are located at either the top (denoted by -T suffix) or the bottom (denoted by -B suffix) of the address map in order to accommodate different microprocessor protocols for kernel code location. The remaining memory is grouped into 64-Kbyte main blocks. All blocks can be locked or unlocked instantly to provide complete protection for code or data. The User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the flash memory. The internal State Machine (WSM) automatically executes the algorithms and timings necessary for program and erase operations, including verification, thereby unburdening the microprocessor or microcontroller. The status register indicates the status of the WSM by signifying block erase or word program completion and status. Refer to Figure, C3 Block Diagram on page 2 and Table on page 2 for the pin definitions.

7 Figure. C3 Block Diagram DQ -DQ 5 V CCQ Output Buffer Input Buffer Output Multiplexer Identifier Register Status Register Data Register I/O Logic Power Reduction Control Data Comparator User Interface CE# WE# OE# RP# A -A 9 Input Buffer Y-Decoder Y-Gating/Sensing State Machine Program/Erase Voltage Switch WP# V PP Address Latch Address Counter X-Decoder 4-KWord Parameter Block 4-KWord Parameter Block 32-KWord Main Block 32-KWord Main Block V CC GND Table. 3 Volt Advanced+ Boot Block Pin Descriptions (Sheet of 2) Symbol Type Name and Function A A 2 DQ DQ 7 DQ 8 DQ 5 CE# OE# WE# RP# INPUT INPUT/ OUTPUT INPUT/ OUTPUT INPUT INPUT INPUT INPUT ADDRESS INPUTS: Memory addresses are internally latched during a program or erase cycle. 8-Mbit: A[-8], 6-Mbit: A[-9], 32-Mbit: A[-2] DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Inputs commands to the User Interface when CE# and WE# are active. Data is internally latched. Outputs array, configuration and status register data. The data pins float to tri-state when the chip is de-selected or the outputs are disabled. DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. Outputs array and configuration data. The data pins float to tri-state when the chip is de-selected. CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OUTPUT ENABLE: Enables the device s outputs through the data buffers during a read operation. OE# is active low. WRITE ENABLE: Controls writes to the command register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. RESET/DEEP POWER-DOWN: Uses two voltage levels (V IL, V IH ) to control reset/deep powerdown mode. When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the State Machine, and minimizes current levels (I CCD ). When RP# is at logic high, the device is in standard operation. When RP# transitions from logic-low to logic-high, the device resets all blocks to locked and defaults to the read array mode. 2

8 WP# INPUT WRITE PROTECT: Controls the lock-down function of the flexible locking feature. When WP# is a logic low, the lock-down mechanism is enabled and blocks marked lock-down cannot be unlocked through software. When WP# is logic high, the lock-down mechanism is disabled and blocks previously lockeddown are now locked and can be unlocked and locked through software. After WP# goes low, any blocks previously marked lock-down revert to that state. See Section 2., C3 Flexible Block Locking on page 3 for details on block locking. V CC SUPPLY DEVICE POWER SUPPLY: [2.7 V 3.6 V] Supplies power for device operations. V CCQ Table. 3 Volt Advanced+ Boot Block Pin Descriptions (Sheet 2 of 2) Symbol Type Name and Function INPUT I/O POWER SUPPLY: Supplies power for input/output buffers. [2.7 V 3.6 V] This input should be tied directly to V CC. PROGRAM/ERASE POWER SUPPLY: [.65 V 3.6 V or.4 V 2.6 V] Operates as an input at logic levels to control complete device protection. Supplies power for accelerated program and erase operations in 2 V ± 5% range. This pin cannot be left floating. Lower V PP V PPLK, to protect all contents against Program and Erase commands. V PP INPUT/ Set V PP =V CC for in-system read, program and erase operations. In this configuration, V PP SUPPLY can drop as low as.65 V to allow for resistor or diode drop from the system supply. Note that if V PP is driven by a logic signal, V IH =.65. That is, V PP must remain above.65v to perform insystem flash modifications. Raise V PP to 2 V ± 5% for faster program and erase in a production environment. Applying 2 V ± 5% to V PP can only be done for a maximum of cycles on the main blocks and 25 cycles on the parameter blocks. V PP may be connected to 2 V for a total of 8 hours maximum. GND SUPPLY GROUND: For all internal circuitry. All ground inputs must be connected. NC NO CONNECT: Pin may be driven or left floating. Program and erase automation allows program and erase operations to be executed using an industry-standard, two-write command sequence to the CUI. Program operations are performed in word increments. Erase operations erase all locations within a block simultaneously. Both program and erase operations can be suspended by the system software in order to read from any other block. In addition, data can be programmed to another block during an erase suspend. The 3 Volt Advanced+ Boot Block flash memories offer two low power savings features: Automatic Power Savings (APS) and standby mode. The device automatically enters APS mode following the completion of a read cycle. mode is initiated when the system deselects the device by driving CE# inactive. Combined, these two power savings features significantly reduce power consumption. The device can be reset by lowering RP# to GND. This provides CPU-memory reset synchronization and additional protection against bus noise that may occur during system reset and power-up/down sequences. The C3 is available in 48-lead TSOP (Figure 2, 48-Lead TSOP Package on page 4), 48-Ball ubga (Figure 3, 48-Ball µbga* Chip Size Package (Top View, Ball Down) on page 5) and 64- Ball EasyBGA (Figure 4, 8 X 8 EasyBGA Package on page 6). 3

9 Figure Lead TSOP Package 64 M 32 M 6 M A 5 A 4 2 A 3 3 A 2 4 A 5 A 6 A 9 7 A 8 8 A 2 9 A 2 WE# RP# 2 V PP 3 WP# 4 A 9 5 A 8 6 A 7 7 A 7 8 A 6 9 A A 4 A 3 A 2 A Advanced+ Boot Block 48-Lead TSOP 2 mm x 2 mm TOP VIEW A 6 V CCQ GND DQ 5 DQ 7 DQ 4 DQ 6 DQ 3 DQ 5 DQ 2 DQ 4 V CC DQ DQ 3 DQ DQ 2 DQ 9 DQ DQ 8 DQ OE# GND CE# A NOTE: Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on Pins 9 and 5. 4

10 Figure Ball µbga* Chip Size Package (Top View, Ball Down) M A A 3 A A 8 V PP WP# A 9 A 7 A 4 B A 4 A WE# RP# A 8 A 7 A 5 A 2 C A 5 A 2 A 9 64M A 2 32M A 2 A 6 A 3 A D A 6 D 4 D 5 D D 2 D 8 CE# A E V CCQ D 5 D 6 D 2 D 3 D 9 D GND F GND D 7 D 3 D 4 V CC D D OE# NOTES:. Shaded connections indicate the upgrade address connections. Lower density devices will not have the upper address solder balls. Routing is not recommended in this area. A 9 is the upgrade address for the 6-Mbit device. A 2 is the upgrade address for the 32-Mbit device Mbit not available on µbga* CSP. 5

11 Figure 4. 8 X 8 EasyBGA Package A A B A A 6 A 8 V PP V CC GND A A 5 B A 5 A GND V CC V PP A 8 A 6 A C A 2 A 7 A 9 () RP# DU A 2 () A A 4 C A 4 A A 2 () DU RP# A 9 () A 7 A 2 A 3 A 7 WP# WE# DU A 2 () A 2 A 3 A 3 A 2 A 2 () DU WE# WP# A 7 A 3 D A 4 A 5 DU DU DU DU A 8 A 9 D A 9 A 8 DU DU DU DU A 5 A 4 E DQ 8 DQ DQ 9 DQ 3 DQ 2 DQ 6 DU DU E DU DU DQ 6 DQ 2 DQ 3 DQ 9 DQ DQ 8 F CE# DQ DQ DQ DQ 5 DQ 4 DU DU F DU DU DQ 4 DQ 5 DQ DQ DQ CE# G G A V SSQ DQ 2 DQ 4 DQ 3 DQ 5 GND A 6 A 6 GND D 5 D 3 DQ 4 DQ 2 V SSQ A H A 22 (2) OE# V CCQ V CC V SSQ DQ 7 V CCQ DU H DU V CCQ D 7 V SSQ V CC V CCQ OE# A 22 (2) Top View - Ball Side Down Bottom View - Ball Side Up NOTES:. A 9 denotes 6-Mbit; A 2 denotes 32-Mbit 2. A 2 and A 22 indicate future density upgrade paths to 64 Mbit and 28 Mbit, respectively (not yet available)..2 J3 Overview The.25 µ 3 Volt Intel StrataFlash memory family contains high-density memories organized as 6 -Mbytes or 8-Mwords (28-Mbit), 8-Mbytes or 4-Mwords (64-Mbit), and 4-Mbytes or 2-Mwords (32-Mbit). These devices can be accessed as 8- or 6-bit words. The 28-Mbit device is organized as one-hundred-twenty-eight 28-Kbyte (3,72 bytes) erase blocks. The 64-Mbit device is organized as sixty-four 28-Kbyte erase blocks, while the 32-Mbits device contains thirty-two 28-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-system. A 28-bit protection register has multiple uses, including unique flash device identification. The device s optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. 6

12 A User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device s 28-Kbyte blocks typically within one second independent of other blocks. Each block can be independently erased, times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Buffer of 32 bytes (6 words) to allow optimum programming performance. By using the Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 2 times over non- Buffer writes. Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The status register indicates when the WSM s block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates that the WSM is ready for a new command, block erase is suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS pin to be configured to pulse on completion of programming and/or block erases. Refer to Table 2, J3 Pin Descriptions on page 8 for additional pin definitions. 7

13 Table 2. J3 Pin Descriptions Symbol Type Name and Function A A A 23 DQ DQ 7 DQ 8 DQ 5 CE, CE, CE 2 RP# OE# WE# STS BYTE# V PEN INPUT INPUT INPUT/ OUTPUT INPUT/ OUTPUT INPUT INPUT INPUT INPUT OPEN DRAIN OUTPUT INPUT INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x6 mode (i.e., the A input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A A 2 64-Mbit: A A Mbit: A A 23 LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during User Interface (CUI) writes. Outputs array, query, identifier, or status data in the appropriate read mode. Floated when the chip is de-selected or the outputs are disabled. Outputs DQ 6 DQ are also floated when the State Machine (WSM) is busy. Check SR.7 (status register bit 7) to determine WSM status. HIGH-BYTE DATA BUS: Inputs data during x6 buffer writes and programming operations. Outputs array, query, or identifier data in the appropriate read mode; not used for status register reads. Floated when the chip is de-selected, the outputs are disabled, or the WSM is busy. CHIP ENABLES: Activates the device s control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 3, 3 Volt Intel StrataFlash Components Chip Enable Truth Table on page ), power reduces to standby levels. All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE, CE, or CE 2 that enables the device. Device deselection occurs with the first edge of CE, CE, or CE 2 that disables the device (see Table 3). RESET/ POWER-DOWN: Resets internal automation and puts the device in power-down mode. RP#- high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates the device s outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the User Interface, the Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. STATUS: Indicates the status of the internal state machine. When configured in level mode (default mode), it acts as a RY/BY# pin. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS pin, see the Configurations command. Tie STS to V CCQ with a pull-up resistor. BYTE ENABLE: BYTE# low places the device in x8 mode. All data is then input or output on DQ DQ 7, while DQ 8 DQ 5 float. Address A selects between the high and low byte. BYTE# high places the device in x6 mode, and turns off the A input buffer. Address A then becomes the lowest order address. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With V PEN V PENLK, memory contents cannot be altered. V CC SUPPLY DEVICE POWER SUPPLY: With V CC V LKO, all write attempts to the flash memory are inhibited. V CCQ OUTPUT BUFFER SUPPLY OUTPUT BUFFER POWER SUPPLY: This voltage controls the device s output voltages. To obtain output voltages compatible with system data bus voltages, connect V CCQ to the system supply voltage. GND SUPPLY GROUND: Do not float any ground pins. NC NO CONNECT: Lead is not internally connected; it may be driven or floated. Three CE pins are used to enable and disable the device. A unique CE logic design (see Table 3, 3 Volt Intel StrataFlash Components Chip Enable Truth Table on page ) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or SIMM module. 8

14 The BYTE# pin allows either x8 or x6 read/writes to the device. BYTE# at logic low selects 8-bit mode; address A selects between the low byte and high byte. BYTE# at logic high enables 6-bit operation; address A becomes the lowest order address and address A is not used (don t care). A device block diagram is shown in Figure 5, 3 Volt Intel StrataFlash Memory Block Diagram on page 9. When the device is disabled (see Table 3, 3 Volt Intel StrataFlash Components Chip Enable Truth Table on page ) and the RP# pin is at V CC, the standby mode is enabled. When the RP# pin is at GND, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (t PHQV ) is required from RP# switching high until outputs are valid. Likewise, the device has a wake time (t PHWL ) from RP#-high until writes to the CUI are recognized. With RP# at GND, the WSM is reset and the status register is cleared. 3 Volt Intel StrataFlash memory devices are available in two package types. Both 56-lead TSOP (Thin Small Outline Package) and BGA (Ball Grid Array Package) support all offered densities. Figure 6, 3 Volt Intel StrataFlash Memory 56-Lead TSOP (32/64/28 Mbit) on page and Figure 7, 3 Volt Intel StrataFlash Memory Easy BGA Package on page show the pinouts. Figure 5. 3 Volt Intel StrataFlash Memory Block Diagram DQ - DQ 5 V CCQ Output Buffer Input Buffer Output Latch/Multiplexer Query Identifier Register Status Register Data Register Buffer User Interface I/O Logic CE Logic V CC BYTE# CE CE CE 2 WE# OE# RP# A - A 2 Data Comparator Multiplexer 32-Mbit: A - A 2 64-Mbit: A - A Mbit: A - A 23 Input Buffer Address Latch Address Counter Y-Decoder X-Decoder Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 28-Mbit: One-hundred twenty-eight 28-Kbyte Blocks State Machine Program/Erase Voltage Switch STS V PEN V CC GND 9

15 Figure 6. 3 Volt Intel StrataFlash Memory 56-Lead TSOP (32/64/28 Mbit) 3 Volt Intel StrataFlash Memory 3 Volt Intel StrataFlash Memory 32/64/28M 32/64/28M A 22 () CE A 2 A 2 A 9 A 8 A 7 A 6 V CC A 5 A 4 A 3 A 2 CE V PEN RP# A A A 9 A 8 GND A 7 A 6 A 5 A 4 A 3 A 2 A Volt Intel StrataFlash Memory 56-Lead TSOP Standard Pinout 4 mm x 2 mm Top View A 24 (3) WE# OE# STS DQ 5 DQ 7 DQ 4 DQ 6 GND DQ 3 DQ 5 DQ 2 DQ 4 V CCQ GND DQ DQ 3 DQ DQ 2 V CC DQ 9 DQ DQ 8 DQ A BYTE# A 23 (Note ) CE 2 NOTES:. Address A22 is only valid on 64-Mbit densities and above; otherwise, it is a no connect (NC) 2. Address A23 is only valid on 28-Mbit densities and above; otherwise, it is a no connect (NC) 3. Address A24 is only valid on 256-Mbit densities and above; otherwise, it is a no connect (NC)

16 Figure 7. 3 Volt Intel StrataFlash Memory Easy BGA Package A B C A A 6 A 8 V PEN A 3 V CC A 8 A 22 () A 2 GND A 9 CE # A 4 DU A 9 CE # A () A 22 A 8 V CC A 3 V PEN A 8 A 6 A B CE # A 9 DU A 4 CE # A 9 GND A 2 C A 3 A 7 A A 2 A 5 DU A 2 A 2 D A 4 A 5 A RP# DU DU A 6 A 7 E DQ 8 DQ DQ 9 DQ 3 DQ 4 DU DQ 5 STS F BYTE# DQ DQ DQ DQ 2 DU DU OE# G (2) A 23 A DQ 2 V CCQ DQ 5 DQ 6 DQ 4 WE# H CE 2 # DU V CC GND DQ 3 GND DQ 7 (3) A 24 A 2 A 2 DU A 5 A 2 A A 7 A 3 D A 7 A 6 DU DU RP# A A 5 A 4 E STS DQ 5 DU DQ 4 DQ 3 DQ 9 DQ DQ 8 F OE# DU DU DQ 2 DQ DQ DQ BYTE# G (2) WE# DQ 4 DQ 6 DQ 5 V CCQ DQ 2 A A 23 H (3) A 24 DQ 7 GND DQ 3 GND V CC DU CE 2 # Top View - Ball Side Down Bottom View - Ball Side Up 32 Mbit, 64 Mbit and 28 Mbit: x 3 x.2 mm. mm-ball pitch Table 3. 3 Volt Intel StrataFlash Components Chip Enable Truth Table CE 2 CE CE Device V IL V IL V IL Enabled V IL V IL V IH Disabled V IL V IH V IL Disabled V IL V IH V IH Disabled V IH V IL V IL Enabled V IH V IL V IH Enabled V IH V IH V IL Enabled V IH V IH V IH Disabled NOTE: For single-chip applications, CE 2 and CE can be strapped to GND. 2. Feature Differences To better understand the design considerations, one must understand the feature differences between the C3 and J3. The C3 has two key features: Flexible Block Locking and 28-bit One Time Programming Register (OTP). The J3 has a different Block Locking Configuration which will be discussed later. The J3 also has two key features: Page Mode and 28-bit One Time Programming Register (OTP).

17 The next sub-sections will discuss these key features and J3 Block Locking. Table 4 below provides a comparison. Table 4. Summary Differences Differences 28FxxxC3 28FxxxJ3 Densities 32, 6, 8-Mbit 28, 64, 32 M-bit Bus Width 6 bits 8 or 6 bits (user can choose) Input/Output Bus 3V I/O 3V I/O Asynchronous Read Speeds V CC Page Mode Read Speed 8/6-Mbit: 9,ns 32-Mbit:, ns 8/6 Mbit: 2.7 V 3.6 V 32-Mbit: 2.7 V 3.3 V Not Applicable 28-Mbit: 5ns 64-Mbit: 2ns 32-Mbit: ns 2.7 V 3.6 V 28-Mbit: 5 [25]ns 64-Mbit: 2 [25]ns 32-Mbit: [25]ns Block Architecture Asymmetrical Symmetrical 28-bit One Time Programmable Register YES YES Common Flash Interface (CFI) YES YES Programming Voltage 2 V or 3 V Programming 3 V Programming Block Locking Flexible Block Locking Block Lock-Bit Block Sizes Temperature Cycles Blocking (Top or Bottom): Eight 4KW Parameter Blocks Up to sixty-three, 32KW Main Blocks -4C to 85C, Program/Erase Cycles per Block 64KW Blocks 28-Mbit: C to +7C 64/32-Mbit: -25C to 85C, Erase Cycles per Block 32-bit Buffer Not Applicable 32-byte Buffer Power Down Current V CC Deep Power-Down Current Max = 2uA V CC Power-Down Current Max = ua (No Deep Power Down Mode) Current V CC Current Max= 25uA V CC Current Max = 2uA Erase Current V CC Erase Current = 55mA V CC Block Erase or Clear Block Lock-Bits Current = 7mA Program Current V CC Program Current = 55mA V CC Program = 6mA Program Suspend Latency Erase Suspend Latency Max. Program Suspend Latency = us Max. Erase Suspend Latency = 2us Max. Program Suspend Latency = 3us Max. Erase Suspend Latency = 35us Hardware Protect V PP <.V Vpen<.8V 2

18 2. C3 Flexible Block Locking Intel 3 Volt Advanced+ Boot Block products offer an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. This locking scheme offers two levels of protection. The first level allows software-only control of block locking (useful for data blocks that change frequently), while the second level requires hardware interaction before locking can be changed (useful for code blocks that change infrequently). The following sections will discuss the operation of the locking system. The term state [XYZ] will be used to specify locking states; e.g., state [], where X = value of WP#, Y = bit DQ of the Block Lock status register, and Z = bit DQ of the Block Lock status register. Table 7, Block Locking State Transitions on page 7 defines all of these possible locking states. 2.. Locking Operation The following concisely summarizes the locking functionality. All blocks power-up locked, then can be unlocked or locked with the Unlock and Lock commands. The Lock-Down command locks a block and prevents it from being unlocked when WP# =. When WP# =, Lock-Down is overridden and commands can unlock/lock locked-down blocks. When WP# returns to, locked-down blocks return to Lock-Down. Lock-Down is cleared only when the device is reset or powered-down. The locking status of each block can be set to Locked, Unlocked, and Lock-Down, each of which will be described in the following sections. A comprehensive state table for the locking functions is shown in Table 7, Block Locking State Transitions on page 7, and a flowchart for locking operations is shown in Figure 8 on page 4. 3

19 Figure 8. Locking Operations Flowchart Start Bus Operation Comments 6H (Configuration Setup) H, DH, or 2FH (Optional) Config. Setup Lock, Unlock, or Lockdown Read Configuration Data = 6H Addr = X Data= H (Lock Block) DH (Unlock Block) 2FH (Lockdown Block) Addr=Within block to lock Data = 9H Addr = X Optional 9H (Read Configuration) Read Block Lock Status Read (Optional) (Optional) Block Lock Status Block Lock Status Data Addr = Second addr of block Confirm Locking Change on DQ, DQ. (See Block Locking State Table for valid combinations.) Locking Change Confirmed? No FFh (Read Array) Locking Change Complete 2..2 Locked State The default status of all blocks upon power-up or reset is locked (states [] or []). Locked blocks are fully protected from alteration. Any program or erase operations attempted on a locked block will return an error on bit SR. of the status register. The status of a locked block can be changed to unlocked or lock-down using the appropriate software commands. An unlocked block can be locked by writing the Lock command sequence, 6H followed by H Unlocked State Unlocked blocks (states [], [], []) can be programmed or erased. All unlocked blocks return to the locked state when the device is reset or powered down. The status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. A locked block can be unlocked by writing the Unlock command sequence, 6H followed by DH. 4

20 2..4 Lock-Down State Blocks that are locked-down (state []) are protected from program and erase operations (just like locked blocks), but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked-down by writing the Lock-Down command sequence, 6H followed by 2FH. Locked-down blocks revert to the locked state when the device is reset or powered down. The Lock-down function is dependent on the WP# input pin. When WP# =, blocks in lock-down [] are protected from program, erase, and lock status changes. When WP# =, the lock-down function is disabled ([]) and locked-down blocks can be individually unlocked by software command to the [] state, where they can be erased and programmed. These blocks can then be relocked [] and unlocked [] as desired while WP# remains high. When WP# goes low, blocks that were previously locked-down return to the lock-down state [] regardless of any changes made while WP# was high. Device reset or power-down resets all blocks, including those in lock-down, to locked state Reading a Block s Lock Status The lock status of every block can be read in the configuration read mode of the device. To enter this mode, write 9H to the device. Subsequent reads at Block Address + 2 will output the lock status of that block. The lock status is represented by DQ and DQ. DQ indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering lock-down. DQ indicates lock-down status and is set by the Lock- Down command. It cannot be cleared by software, only by device reset or power-down. Table 5. Block Lock Status Item Address Data Block Lock Configuration XX2 LOCK Block Is Unlocked DQ = Block Is Locked DQ = Block Is Locked-Down DQ = 2..6 Locking Operations during Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock, or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command (BH), then check the status register until it indicates that the erase operation has been suspended. Next write the desired lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command (DH). If a block is locked or locked-down during a suspended erase of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to the Datasheet for detailed information on which commands are valid during erase suspend. 5

21 2..7 Status Register Error Checking Using nested locking or program command sequences during erase suspend can introduce ambiguity into status register results. Since locking changes are performed using a two-cycle command sequence, e.g., 6H followed by H to lock a block, following the Configuration Setup command (6H) with an invalid command will produce a lock command error (SR.4 and SR.5 will be set to ) in the status register. Refer to Table 6 below. (The C3 Status Register Bit Definition is different from the J3.) Table 6. C3 Status Register Bit Definition WSMS ESS ES PS VPPS PSS BLS R NOTES: SR.7 WRITE STATE MACHINE STATUS (WSMS) = Ready =Busy SR.6 = ERASE-SUSPEND STATUS (ESS) = Erase Suspended = Erase In Progress/Completed SR.5 = ERASE STATUS (ES) = Error In Block Erase = Successful Block Erase SR.4 = PROGRAM STATUS (PS) = Error in Programming = Successful Programming SR.3 = V PP STATUS (VPPS) =V PP Low Detect, Operation Abort =V PP OK SR.2 = PROGRAM SUSPEND STATUS (PSS) = Program Suspended = Program in Progress/Completed SR. = BLOCK LOCK STATUS = Prog/Erase attempted on a locked block; Operation aborted. = No operation to locked blocks SR. = RESERVED FOR FUTURE ENHANCEMENTS (R) Check State Machine bit first to determine Word Program or Block Erase completion, before checking Program or Erase Status bits. When Erase Suspend is issued, WSM halts execution and sets both WSMS and ESS bits to. ESS bit remains set to until an Erase Resume command is issued. When this bit is set to, WSM has applied the max. number of erase pulses to the block and is still unable to verify successful block erasure. When this bit is set to, WSM has attempted but failed to program a word/byte. The V PP status bit does not provide continuous indication of V PP level. The WSM interrogates V PP level only after the Program or Erase command sequences have been entered, and informs the system if V PP has not been switched on. The V PP is also checked before the operation is verified by the WSM. The V PP status bit is not guaranteed to report accurate feedback between V PPLK and V PP Min. When Program Suspend is issued, WSM halts execution and sets both WSMS and PSS bits to. PSS bit remains set to until a Program Resume command is issued. If a program or erase operation is attempted to one of the locked blocks, this bit is set by the WSM. The operation specified is aborted and the device is returned to read status mode. This bit is reserved for future use and should be masked out when polling the status register. NOTE: A Sequence Error is indicated when both SR.4, SR.5 and SR.7 are set If a lock command error occurs during an erase suspend, SR.4 and SR.5 will be set to and will remain at after the erase is resumed. When erase is complete, any possible error during the erase cannot be detected via the status register because of the previous locking command error. A similar situation happens if an error occurs during a program operation error nested within an erase suspend. 6

22 Table 7. Block Locking State Transitions X Y Z Current State WP# DQ DQ Name Erase/ Program Allowed? Lock Input Result (Next State) Lock Unlock Lock-Down Unlocked Goes To [] No Change Goes To [] Locked (Default) No No Change Goes To [] Goes To [] Locked-Down No No Change No Change No Change Unlocked Goes To [] No Change Goes To [] Locked No No Change Goes To [] Goes To [] Lock-Down Disabled Goes To [] No Change Goes To [] Lock-Down Disabled No No Change Goes To [] No Change NOTES:. In this table, the notation [XYZ] denotes the locking state of a block, where X = WP#, Y = DQ, and Z = DQ. The current locking state of a block is defined by the state of WP# and the two bits of the block lock status (DQ, DQ ). DQ indicates if a block is locked () or unlocked (). DQ indicates if a block has been lockeddown () or not (). 2. At power-up or device reset, all blocks default to locked state [] (if WP# = ). Holding WP# = is the recommended default. 3. The Erase/Program Allowed? column shows whether erase and program operations are enabled () or disabled (No) in that block s current locking state. 4. The Lock Input Result [Next State] column shows the result of writing the three locking commands (Lock, Unlock, Lock-Down) in the current locking state. For example, Goes To [] would mean that writing the command to a block in the current locking state would change it to [] bit One Time Programmable Register Both the C3 and J3 have a 28-bit one time programmable register. They function the same way in each product. The 28-bit protection register can be used to increase the security of a system design. For example, the number contained in the protection register can be used to mate the flash component with other system components, such as the CPU or ASIC, preventing device substitution. The 28-bits of the protection register are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unchangeable. The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent reprogramming Reading the Protection Register The protection register is read in the identification read mode. The device is switched to this mode by writing the Read Identifier command (9H). Once in this mode, read cycles retrieve the specified information. To return to read array mode, write the Read Array command (FFH). 7

23 2.2.2 Programming the Protection Register The protection register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 6 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. First write the Protection Program Setup command, CH. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in the datasheets for the C3 (3 Volt Advanced+ Boot Block Flash Memory, datasheet 29645) and the J3 (3 Volt Intel StrataFlash Memory, datasheet 29667). See Figure, J3 Protection Register Programming Flowchart on page 2. Any attempt to address Protection Program commands outside the defined protection register address space will result in a status register error (program error bit SR.4 will be set to ). Attempting to program a locked protection register segment will result in a status register error (program error bit SR.4 and lock error bit SR. will be set to ). The Protection Register Programming Flowcharts are the same for the C3 and J3. Since the C3 and J3 have different programming voltage pin definitions (V PEN vs. V PP ), the flowcharts take this into account by pointing to the source of an error. Refer to Figure, J3 Protection Register Programming Flowchart on page Locking the Protection Register The user-programmable segment of the protection register is lockable by programming Bit of the PR-LOCK location to. Bit of this location is programmed to at the Intel factory to protect the unique device number. Bit is set using the Protection Program command to program FFFD to the PR-LOCK location. After these bits have been programmed, no further changes can be made to the values stored in the protection register. Protection Program commands to a locked section will result in a status register error (program error bit SR.4 and lock error bit SR. will be set to ). Protection register lockout state is not reversible. 8

24 Figure 9. C3 Protection Register Programming Flowchart Start Bus Operation Comments CH (Protection Reg. Program Setup) Protect. Register Address/Data Read Status Register Read Protection Program Setup Protection Program Data = CH Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 = WSM Ready = WSM Busy SR.7 =? Full Status Check if Desired Program Complete No Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. FFH after the last program operation to reset device to read array mode. FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above), Bus Operation Comments SR. SR.3 SR.4 V PP Low SR.3, SR.4 = V PP Range Error Prot. Reg. Prog. Error SR., SR.4 = SR., SR.4 =,, Protection Register Programming Error Attempted Program to Locked Register - Aborted Register Locked: Aborted SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the State Machine. SR., SR.3 and SR.4 are only cleared by the Clear Staus Register, in cases of multiple protection register program operations before full status is checked. Program Successful If an error is detected, clear the status register before attempting retry or other error recovery. 9

25 Figure. J3 Protection Register Programming Flowchart Start Bus Operation Comments CH (Protection Reg. Program Setup) Protection Program Setup Protection Program Data = CH Data = Data to Program Addr = Location to Program Protect. Register Address/Data Read Status Register Data Toggle CE# or OE# to Update Status Register Data Read Status Register Check SR.7 = WSM Ready = WSM Busy SR.7 =? Full Status Check if Desired Program Complete No Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. FFH after the last program operation to reset device to read array mode. FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above), Bus Operation Comments SR. SR.3 SR.4 V PEN Low SR.3, SR.4 = V PEN Range Error Prot. Reg. Prog. Error SR., SR.4 = SR., SR.4 =,, Protection Register Programming Error Attempted Program to Locked Register - Aborted Register Locked: Aborted SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the State Machine. SR., SR.3 and SR.4 are only cleared by the Clear Staus Register, in cases of multiple protection register program operations before full status is checked. Program Successful If an error is detected, clear the status register before attempting retry or other error recovery. 2.3 J3 Page Mode When reading information in read array mode, the device defaults to asynchronous page mode. This mode provides high data transfer rate for memory subsystems. In this state, data is internally read and stored in a high-speed page buffer. A 2: addresses data in the page buffer. The page size is four words or eight bytes. Asynchronous word/byte mode is supported with no additional commands required. 2

26 2.4 J3 Block Locking Configuration A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock- Bit command. This command is invalid while the WSM is running or the device is suspended. Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with appropriate block address is followed by the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs status register data when read (see Figure, Set Block Lock-Bit Flowchart on page 22). The CPU can detect the completion of the set lock-bit event by analyzing the STS pin output or status register bit SR.7. When the set lock-bit operation is complete, status register bit SR.4 should be checked. If an error is detected, the status register should be cleared. The CUI will remain in read status register mode until a new command is issued. This two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in status register bits SR.4 and SR.5 being set to. Also, reliable operations occur only when V CC and V PEN are valid. With V PEN V PENLK, lock-bit contents are protected against alteration. 2.5 J3 Clear Block Lock-Bits All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lockbits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is running or the device is suspended. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs status register data when read (see Figure 2, Clear Lock-Bit Flowchart on page 23). The CPU can detect completion of the clear block lockbits event by analyzing the STS pin output or status register bit SR.7. When the operation is complete, status register bit SR.5 should be checked. If a clear block lock-bit error is detected, the status register should be cleared. The CUI will remain in read status register mode until another command is issued. This two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in status register bits SR.4 and SR.5 being set to. Also, a reliable clear block lock-bits operation can only occur when V CC and V PEN are valid. If a clear block lock-bits operation is attempted while V PEN V PENLK, SR.3 and SR.5 will be set to. If a clear block lock-bits operation is aborted due to V PEN or V CC transitions out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. 2

27 Figure. Set Block Lock-Bit Flowchart Start Bus Operation Comments 6H, Block Address Set Block Lock-Bit Setup Data = 6H Addr =Block Address H, Block Address Read Set Block Lock-Bit Confirm Data = H Addr = Block Address Status Register Data Read Status Register SR.7 = Full Status Check if Desired Repeat for subsequent lock-bit operations. Check SR.7 = WSM Ready = WSM Busy Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. FFH after the last lock-bit set operation to place device in read array mode. Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = SR.4,5 = SR.4 = Set Lock-Bit Successful Voltage Range Error Sequence Error Set Lock-Bit Error Bus Operation Comments Check SR.3 = Programming Voltage Error Detect Check SR.4, 5 Both = Sequence Error Check SR.4 = Set Lock-Bit Error SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register command, in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 66_b 22

28 Figure 2. Clear Lock-Bit Flowchart Start Bus Operation Comments 6H Clear Block Lock-Bits Setup Data = 6H Addr = X DH Clear Block or Lock-Bits Confirm Data = DH Addr = X Read Status Register Data Read Status Register SR.7 = Check SR.7 = WSM Ready = WSM Busy FFH after the clear lock-bits operation to place device in read array mode. Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) SR.3 = SR.4,5 = SR.5 = Clear Block Lock-Bits Successful Voltage Range Error Sequence Error Clear Block Lock-Bits Error Bus Operation Comments Check SR.3 = Programming Voltage Error Detect Check SR.4, 5 Both = Sequence Error Check SR.5 = Clear Block Lock-Bits Error SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register command. If an error is detected, clear the status register before attempting retry or other error recovery. The C3 is based on single bit per cell technology, while the J3 is based on multi-level cell technology. Multi-level cell technology, or MLC, allows the storage of two bits in one cell by changing voltage threshold (V t ) levels (see Figure 3, Intel StrataFlash Memory Vt Levels. on page 24). Programming the J3 devices increases the cell's V t Level. 23

29 Figure 3. Intel StrataFlash Memory V t Levels. V t,,,, Level 3 Level 2 Level Level Designs that do not use flexible block locking on the C3 and page mode on the J3 should consider using a multi-site layout for additional design versatility. For project flexibility, the designer must bear in mind the hardware considerations, software considerations and system implications of the C3 and J3. 3. Hardware Considerations Figure 8 covers the hardware considerations of a multi-site layout between the C3 and J3. Table 8. Hardware Considerations (Sheet of 2) 3 V Advanced+ Boot Block Memory (C3) 3 V Intel StrataFlash Memory (J3) V PP Voltage Range (V).65 V 3.6 V or V 3.6 V V CC Voltage Range (V) Block Size and Blocking Package 32-Mbit: 2.7 V 3.3 V 8, 6-Mbit: 2.7 V 3.6 V Blocking (Top or Bottom): 8 x 4KW Parameter Blocks Up to 63, 32KW Main Blocks 48-Lead TSOP, 48-Ball µbga* CSP, 64-Ball EasyBGA 2.7 V 3.6 V 64KW 56-Lead TSOP, 64-Ball EasyBGA Pinout Differences CE#, WP#, V PP A 22, A 23, CE, CE, CE 2, STS, BYTE#, V PEN Asynchronous Read Page Mode Read 3 V Programming Typical Word Pgm Time 8/6-Mbit: 9, ns 32-Mbit:, ns N/A 4KW Parameter Block:.ns 32KW Main Block:.8s 28-Mbit: 5ns 64-Mbit: 2ns 32-Mbit: ns 28-Mbit: 5[25]ns 64-Mbit: 2[25]ns 32-Mbit: [25]ns 6.8us 24