Datasheet Summary. P2020 QorIQ Integrated Processor Hardware Specifications. The following list provides an overview of the P2020 feature set:

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1 QorIQ Integrated Processor Hardware Specifications Datasheet Summary The following list provides an overview of the feature set: Dual () High-performance Power rchitecture e500 Cores. 36 bit Physical addressing Double-precision floating-point support 32 kbyte L1 instruction Cache and 32 kbyte L1 data Cache for each Core 800 MHz to 1.2 GHz Clock frequency 512 Kbyte L2 Cache with ECC. lso Configurable as SRM and stashing memory. Three 10/100/1000 Mbps enhanced three-speed Ethernet Controllers (etsecs) TCP/IP acceleration, quality of service, and Classification Capabilities IEEE Std 1588 support Lossless flow Control R/G/MII, R/TBI, SGMII High-speed interfaces supporting various multiplexing options: Four SerDes to GHz multiplexed across controllers Three PCI Express interfaces Two Serial RapidIO interfaces Two SGMII interfaces High-Speed USB Controller (USB 2.0) Host and device support Enhanced host Controller interface (EHCI) ULPI interface to PHY Enhanced secure digital host Controller (SD/MMC) Enhanced Serial peripheral interface (espi) Integrated Security Engine Protocol Support Includes SNOW, RC4, 3DES, ES, RS/ECC, RNG, single-pass SSL/TLS, Kasumi XOR cceleration 64 bit DDR2/DDR3 SDRM memory Controller with ECC Support Programmable Interrupt Controller (PIC) Compliant with OpenPIC Standard Two Four-channel DM Controllers Two I 2 C Controllers, DURT, Timers Enhanced local bus Controller (elbc) 16 general-purpose I/O signals Operating Junction Temperature (Tj) range: 55 C/125 C and 40 C/125 C (Industrial Specification) mm 689-pin WB-TePBG II (Wire Bond Temperature-enhanced Plastic BG) Visit our website: for the latest version of the datasheet

2 Block Diagram Figure shows the major functional units within the. Power Management I-Cache e500 Core D-Cache 512-Kbyte L2 Cache I-Cache e500 Core D-Cache Enhanced Local Bus OpenPIC Security cceleration with XOR cceleration SD/MMC e500 Coherency Module 64-/32-Bit DDR2/DDR3 SDRM Controller Performance Monitor DURT 2x I 2 C espi USB Host/Device ULPI Gigabit Ethernet DM SRIO/ DM SRIO/ RIO Msg Unit/ SGMII SGMII SerDes 2

3 1. Package Information This section provides the package parameters and ordering information. 1.1 Package Parameters for the WB-TePBG The package parameters are provided in the following list. The package type is 31 mm 31 mm, 689 plastic ball grid array (WB-TePBG). Package outline 31 mm 31 mm Interconnects 689 Pitch 1.00 mm Module height (typical) 2.0 mm to 2.46 mm (Maximum) Solder Balls 3.5% g, 96.5% Sn Ball diameter (typical) 0.60 mm Figure 1-1. Package 1 Corner M B C B C 689X M B C Seating plane X 0.2 Top 28X 1 J H G F E D C B Y W V U T R P N M L K J H G F E D C B Bottom 28X 1 689X M 0.1 M 3 B C (1.73) Side Notes: 1. ll dimensions are in millimeters. 2. Dimensioning and tolerancing per SME Y14. 5M Maximum solder ball diameter measured parallel to Datum. 4. Datum, the seating plane, is determined by the spherical crowns of the solder balls. 5. Parallelism measurement shall exclude any effect of mark on top surface of package. 3

4 1.2 Ordering Information Table 1-1 provides the e2v part numbering nomenclature for the. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local e2v sales office. Each part number also contains a revision code which refers to the die mask revision number. Table 1-1. Ordering Information p 2 02 or 01 0 y e n c d r Generation (1) Platform Number of Cores Derivative Temperatur e Range Encryption Package Type CPU Frequency Y DDR Speed Die Revision P(X) (2) = 45 nm 2 01 = Single core 02 = Dual core 0-9 F: 40/125 M: 55/125 E = SEC Present N = SEC Not Present 4 = TEPBG2 Pb 2 = TEPBG2 Pb free H = 800 MHz K = 1000 MHz M = 1200 MHz Z = Not Specified B = Rev 2.0 Notes: 1. For availability of the different versions, contact your local e2v sales office. 2. The letter X in the part number designates a "Prototype" product that has not been qualified by e2v. Reliability of a PCX partnumber is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes. 3. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. dditionally, parts addressed by part number specifications may support other maximum core frequencies. 2. Document Revision History Table 2-1 provides a revision history for the hardware specification. Table 2-1. Document Revision History Rev. No Date Substantive Change(s) 1048S 10/2010 Initial revision. 4

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