P2040 QorIQ implementation

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James Sparks
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Course objectives: This course has 6 main objectives: Describing the hardware implementation, particularly the boot sequence and the DDR3 controller Understanding the features of the internal

1 Course objectives: This course has 6 main objectives: Describing the hardware implementation, particularly the boot sequence and the DDR3 controller Understanding the features of the internal interconnect and related units and mechanisms such as PAMU, CPC and stashing Explaining the standard bus interface controllers, PCIe, SRIO, USB, SATA and MMC-SD Describing the units which are interconnected to other modules, such as clocking, interrupt controller and DMA controller, because the boot program generally has to modify the setting of these units Clarifying the operation of the Datapath Acceleration Architecture that assists the processor core in taking in charge buffer allocation, queue management, frame management and particularly incoming frame classification, pattern searching, and encryption Describing the various debug units and their utilization to fix errors in a multicore / multimaster SoC Prerequisites: Experience of a 32-bit processor or DSP is mandatory Note that the e500mc Power core is covered in a separate course reference FCC1 The e500mc cores implemented in the P2040 do not support L2 caches See our following related courses: - Gigabit Ethernet (ref N1) - 10 Gigabit Ethernet (ref N3) - PCI express gen2 (ref I3) - RapidIO 2.1 (ref I4) - USB 2.0 (ref I6) - SD / MMC (ref I18) - S-ATA (ref I11) 1. P204X ARCHITECTURE [1- Block diagram Internal architecture CoreNet coherency fabric Coherency subdomains Memory map, local access windows Highlighting data paths inside the P204X, benefit of a dual-ddr controller system Application examples Multicore processing scenarios e500mc core integration SOC PLATFORM [9-2. POWER, RESET AND CLOCKING [2- DC and AC electrical characteristics Reset causes Configuration signals sampled at reset Output signals state during reset Reset configuration words source Pre-boot loader, initializing the platform prior to starting the processor core Required data structure PCIe, SRIO Host / Agent configuration Boot memory space, boot space translation Clocking, system clock domains Dynamically changing core clocks SerDes high speed lanes configuration Reference clocks for SerDes protocols Advanced power management 3. SECURE BOOT [2- Objectives of trust architecture Internal boot ROM, secure boot sequence Utilization of scratch write once registers to pass the address of the user boot program Security fuse processor Code signing External tamper detection Run time integrity checker Secure debug controller 4. CORENET PLATFORM CACHE [2- Cache operation, write-through or write-back operation Entry locking Operation as memory-mapped SRAM Support for interleaving Partitioning between coherency domains

2 Stashing, address-based or CoreNet signalled Soft error detection and correction Programming interface 5. PERIPHERAL ACCESS MANAGEMENT UNIT (PAMU) [2- Controlling master access permissions through Logical I/O Device Number Address translation Descriptor organization Peer-to-peer operations, transferring through CoreNet without using the DDR memory Data structures, Peripheral Access Authorization and Control Entry Operation mode translation, mapping for instance PCIe Mem writes into local decorated storage transactions Steps in processing of DSA operations by pamu PAMU caches PAMU gate closed state Interrupt signalling, ECC protection for PAMU caches 6. MULTIPROCESSOR PERIPHERAL INTERRUPT CONTROLLER [1- Open PIC architecture compatibility Interrupt nesting Description of the 4 timers / counters Message interrupts e500-to-e500 interrupt capability Interrupt assignment 7. LOW SPEED PERIPHERALS [On request] Introduction to UART protocol - Description of the NS16452/16552 compliant Uarts - FIFO mode - Flow control signal management I2C protocol fundamentals: addressing, multimaster operation - Transfer timing diagrams, SCL and SDA pins - Transmit and receive sequence espi controller 8. ENHANCED SDHC [On request] Interface to SD and MMC cards Transfer protocol, single block, multiple block read and write Internal and external DMA capabilities Error management SD protocol unit Card insertion and removal detection 9. USB CONTROLLERS [On request] Host or device support High-speed operation EHCI support, scheduling the various transactions into frames Integrated PHY Full speed operation Endpoint configuration Non-EHCI tuning control registers, miscellaneous variations from EHCI Device operation HARDWARE IMPLEMENTATION [ THE DDR3 / 3L MEMORY CONTROLLER [3- Jedec specification basics, mode register initialization, bank selection and precharge On-Die termination and calibration DDR3 fly-by architecture, write leveling Reset sequence, dynamic ODT, ZQ calibration Command truth table Hardware interface Refresh types Bank activation, read, write and precharge timing diagrams, page mode DDR-SDRAM controller overview Initial configuration following Power-on-Reset Controller interleaving support Address decode unit Timing parameters programming Initialization routine Tuning the performance of the DDR3 controller Testing the memory using patterns Active zeroization of system memory upon detection of a user-defined security violation 11. ENHANCED LOCAL BUS CONTROLLER [2- Multiplexed or non-multiplexed address and data buses Connecting 8- and 16-bit devices Atomic operations Burst support Dynamic bus sizing GPCM, UPMs states machines Interfacing to ZBT SRAMs Introduction to NAND flashs NAND flash controller, FCM buffer RAM ECC checking enable/disable feature supported during boot 12. INTEGRATED DMA CONTROLLERS [1- Priority between the 4 channels Support for cascading descriptor chains Scatter / gathering Selectable hardware enforced coherency Ability to start DMA from external 3-pin interface 13. PCI EXPRESS INTERFACE [2- Modes of operation, Root Complex / Endpoint

3 Acting as a bridge when Root Complex Byte swapping Transaction ordering rules Programming inbound and outbound ATMUs Supported messages Benefits of MSIs Low power management Configuration, initialization Enhanced error reporting 14. SERIAL RAPIDIO INTERFACE [1- RapidIO port Accept-all mode of operation RapidIO doorbell and port-write unit Accessing configuration registers via RapidIO packets Programming inbound and outbound ATMUs Critical request flow Hot-swap support Error handling 15. SATA CONTROLLERS [2- SATA basics Support for SATA II extensions Electrical specification Bringing the SATA controller online/offline Native command queuing, command descriptor Standard ATA master-only emulation Interrupt coalescing Hot plug Initialization steps DATAPATH PROCESSING SUBSYSTEM [ DPAA OVERVIEW [1- Definitions: buffer, buffer pool, frame, frame queue, work queue, channel Data formats Frame formats Packet walk through DPAA Configuration and Initialization 17. QUEUE MANAGER [3- Objectives if this accelerator Frame description Structure of frame queues Active and suspended frame queues Frame queue descriptor, frame queue descriptor cache Frame queue state machine Multiway resource arbiter Work queues and channels Enqueue and dequeue portals Sequences to understand how frames a enqueued / dequeued Class and intra-class scheduling rules Utilization of rings Dequeue dispatcher operation Message ring Software interface, management Command register, Management Response registers Stash transaction flow control and scheduling Congestion avoidance, Weighted Random Early Discard Order definition point implementation CoreNet initiator scheduling and priority Error management and recovery 18. BUFFER MANAGER [2- Objectives if this accelerator Central resource pool management function External linked list LIFO Per-pool stockpile CoreNET software portals Direct connect portals Software interface, Command register, Management Response registers Buffer Pool State Change Notifications Buffer pool size programming Performance Monitor 19. FRAME MANAGER [6- Objectives if this accelerator, parsing, classifying and distributing in-line/off-line packet FMAN submodules Interface with QMan, enqueue, dequeue operation Interface with BMan, supporting dynamic FIFO buffers User defined conditions to generate pause frame on depletion status of BMan pools Arbitration between ports, configuring weights Generate statistic information about external buffers - Rx BMI features Hardware assist for IEEE 1588 compliant timestamping Programmable discard mask Programmable error mask - Tx BMI features Configurable update of TCP/UDP checksum and IPv4 header checksum Traffic shaping Congestion, rejection handling Configurable Tx pipeline - Offline parsing, host command features Programmable parsing start offset from beginning of frame rate limiter, traffic shaping Programmable default FQID Maximum number frames/sec per each offline parsing/host command channel Policing functionality based on classification results Port virtualization

4 Host commands DMA, emergency levels - Frame processing manager Distributing tasks between the various processing elements Assigning task numbers, task status Timestamp and prescale Supports order restoration per PORT_ID - FMan controller Coarse classification Look up using a key generated from fields present in the received frame Action descriptor Specifying the matching table parameters on which the lookup is performed: table descriptor, new classification result, keep classification results Support for nested lookups dynamic updating of coarse classification tables Matching table structure Ethernet Independent mode, using legacy BD structures Host commands - Parser Parser inputs and outputs Parse tree Hard-coded parser function, header examination sequences User programmed parse functions, examine instructions pre-positioned in a dedicated internal RAM Dispatch and command buses Parse array organization Example, parsing of VLAN tagged IP / UDP / port 23 frames - Key generator Relationship between Key generator and FMan Key generation schemes using the Lineup Confirmation Vector and Classification Plan ID received from the parser Next Invoked Action, directed way, indirect way Key generation command description KRAM Hash function Port based partition Key generation codes Debug facilities - Policer Implementation of differentiated services at line speed Protecting on chip cores from excessive traffic or packet rates Operating modes: pass-through, RFC2698, RFC4115 Color-aware vs color-blind mode Pre-coloring of the packet Profile RAM Profile context data Virtual MAC separation for up to 12 port-id numbers Traffic Metering and Marking Modes, token bucket Load spreading and policing traffic per core Profile concatenation for combined packet / byte based policing Profile concatenation for aggregating multiple streams Profile concatenation with per color aggregation Debug facilities 20. DATA PATH THREE-SPEED ETHERNET CONTROLLERS [ specification fundamentals: the 3 layers PHY, MAC and control Frame format with and without VLAN option IEEE 802.3, 802.3u, 820.3x, 802.3ac, 802.3ab compliance Connection to packet FIFO interface Physical interfaces: MII, GMII, RGMII, SGMII, TBI MAC address recognition Tuning inter-frame gap 256-entry hash table for unicast and multicast Accessing PHY registers Suspending the transmitter, handling pause packets RMON statistic counters, carry registers Client IEEE1588 timers Interrupt management Error handling procedure GIGABIT MAC [1- Overview of 10-gigabit standard, indicating the possible media XAUI interface to PHY Multicast address filtering with 512-bit hash code lookup Dynamic inter packet gap (IPG) calculation for WAN applications MAC address insertion Support for VLAN Deficit Idle Counter (DIC) for optimized performance with minimum IPG for LAN applications IEEE 1588 timestamping 22. RAPIDIO MESSAGE MANAGER [1- Type5 6 and Type 8 11 support 2 inbox/outbox mailboxes (queues) for data and one doorbell message structure Multicasting Outbound segmentation units

5 23. SECURITY ENGINE [3- Overview of the encryption mechanism Introduction to DES, 3DES and AES algorithms Job management using QMan interface Input / output rings Cryptographic operations Job descriptor parsing Sharing descriptors Data movement, FIFOs Scatter / gather DMA Selecting the authentication / cryptographic algorithm Hardware implementation, top-level controller Run Time Integrity Checking Protocol processing Export and Import of cryptographic Blobs Public Key Hardware Accelerator (PKHA) SNOW 3G Accelerator Data Encryption Standard Accelerator (DES) Cyclic Redundancy Check Accelerator (CRCA) Message Digest Hardware Accelerator (MDHA) Elliptic Curve Cryptographic Functions Example, implementing IPSec 24. PATTERN MATCHER [4- Objective of this unit, identifying signatures in incoming gigabit streams Connection to QMan and BMan QMan bypass mechanism Ability to track stateful relationships between patterns found in the data it scans Support for wildcarding with no pattern explosion Updating the pattern database Definition of a regular expression Comparing the string under inspection with the programmed patterns Detecting patterns across packet boundaries Processing pipeline, work units Pattern Matcher Frame Agent Pattern description, pattern description memory space Pattern description block caching Key Element Scanner, trigger stage, confidence stage Data Examination Engine Stateful Rule Engine, Stateful Rule Physical Structure, SRE instruction set Format of reports Pattern Matcher Table Configuration Commands Exclusive Frame Queue Control Mechanism Internal Caching of System Memory Data Cache awareness Error handling Debug, Performance Monitor Event Interface GLOBAL FUNCTIONS, DEVELOPMENT AND DEBUG [4-25. PERFORMANCE MONITOR AND DEBUG FEATURES [4- Introduction to NEXUS specification - NEXUS Aurora link - Event processing unit - Threshold events - Chaining, triggering - Watchpoint facility - Trace buffer - Event Combining for the Creation of Advanced Triggers - Cross-Functional Debug Components - Datapath debug - CoreNet debug - OCeaN debug - DDR SDRAM interface debug, measuring permaster bandwidth - Core level debug - Debug scenarii

FCQ2 - P2020 QorIQ implementation

Formation P2020 QorIQ implementation: This course covers NXP QorIQ P2010 and P2020 - Processeurs PowerPC: NXP Power CPUs FCQ2 - P2020 QorIQ implementation This course covers NXP QorIQ P2010 and P2020 Objectives