CMSC 313 Lecture 26 DigSim Assignment 3 Cache Memory Virtual Memory + Cache Memory I/O Architecture

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1 CMSC 313 Lecture 26 DigSim Assignment 3 Cache Memory Virtual Memory + Cache Memory I/O Architecture UMBC, CMSC313, Richard Chang <chang@umbc.edu>

2 CMSC 313, Computer Organization & Assembly Language Programming Section 0101 Fall 2004 DigSim Assignment 3: Finite State Machine Simplifications Due: Tuesday, December 14, 2004 Objective The objective is to design and simplify a moderately complex a finite state machine. Assignment You have already completed the design and simplification steps in Homework 5. Your assignment here is to implement the finite state machine you designed in Question #5 of Homework 5. You should use the state assignment and flip-flop selection that uses the smallest total number of gates. Note that the gates used for the output z might be different for different state assignments. What to submit 1) If the finite state machine you implemented differs significantly from the one you turned in for Homework 5, then submit the transition diagram, truth tables and formulas you used to implement this finite state machine in class on Tuesday, December 14. 2) Save your circuit as you did in DigSim Assignment 1. Submit the circuit file using the Unix submit command as in previous assignments. The submission name for this assignment is: digsim3. The UNIX command to do this should look something like: submit cs313_0101 digsim3 d3.sim

3 Memory Organization Last Time Technological advances in DRAM SDRAM allows quick access to successive memory locations in the same row. Why is this helpful?? UMBC, CMSC313, Richard Chang

4 7-3 Chapter 7: Memory The Memory Hierarchy Fast and expensive Registers Increasing performance and increasing cost Cache Main memory Secondary storage (disks) Off-line storage (tape) Slow and inexpensive

5 7-14 Chapter 7: Memory Placement of Cache in a Computer System CPU 400 MHz Main Memory 10 MHz CPU 400 MHz Cache Main Memory 10 MHz Bus 66 MHz Without cache Bus 66 MHz With cache The locality principle: a recently referenced memory location is likely to be referenced again (temporal locality); a neighbor of a recently referenced memory location is likely to be referenced (spatial locality).

6 7-15 Chapter 7: Memory An Associative Mapping Scheme for a Cache Memory Valid Dirty Tag 27 Slot 0 Block 0 32 words per block Slot 1 Block 1 Slot 2.. Block 128 Slot Block 129 Cache Memory. Block Main Memory

7 7-16 Associative Mapping Example Chapter 7: Memory Consider how an access to memory location (A035F014) 16 is mapped to the cache for a 2 32 word memory. The memory is divided into 2 27 blocks of 2 5 = 32 words per block, and the cache consists of 2 14 slots: Tag Word 27 bits 5 bits If the addressed word is in the cache, it will be found in word (14) 16 of a slot that has tag (501AF80) 16, which is made up of the 27 most significant bits of the address. If the addressed word is not in the cache, then the block corresponding to tag field (501AF80) 16 is brought into an available slot in the cache from the main memory, and the memory reference is then satisfied from the cache. Tag Word

8 7-17 Replacement Policies Chapter 7: Memory When there are no available slots in which to place a block, a replacement policy is implemented. The replacement policy governs the choice of which slot is freed up for the new block. Replacement policies are used for associative and set-associative mapping schemes, and also for virtual memory. Least recently used (LRU) First-in/first-out (FIFO) Least frequently used (LFU) Random Optimal (used for analysis only look backward in time and reverse-engineer the best possible strategy for a particular sequence of memory references.)

9 7-18 Chapter 7: Memory A Direct Mapping Scheme for Cache Memory Valid Dirty Tag 13 Slot 0 Block 0 32 words per block Slot 1 Block 1 Slot 2.. Block 2 14 Slot Block Cache Memory. Block 2 27 Main Memory

10 7-19 Direct Mapping Example Chapter 7: Memory For a direct mapped cache, each main memory block can be mapped to only one slot, but each slot can receive more than one block. Consider how an access to memory location (A035F014) 16 is mapped to the cache for a 2 32 word memory. The memory is divided into 2 27 blocks of 2 5 = 32 words per block, and the cache consists of 2 14 slots: Tag Slot Word 13 bits 14 bits 5 bits If the addressed word is in the cache, it will be found in word (14) 16 of slot (2F80) 16, which will have a tag of (1406) 16. Tag Slot Word

11 7-20 Chapter 7: Memory A Set Associative Mapping Scheme for a Cache Memory Valid Dirty Tag Set 0 14 Slot 0 Slot 1 Block 0 Block 1 32 words per block Set 1 Slot 2.. Block 2 13 Set Slot Block Cache. Block Main Memory

12 7-21 Chapter 7: Memory Set-Associative Mapping Example Consider how an access to memory location (A035F014) 16 is mapped to the cache for a 2 32 word memory. The memory is divided into 2 27 blocks of 2 5 = 32 words per block, there are two blocks per set, and the cache consists of 2 14 slots: Tag Set Word 14 bits 13 bits 5 bits The leftmost 14 bits form the tag field, followed by 13 bits for the set field, followed by five bits for the word field: Tag Set Word

13 7-22 Chapter 7: Memory Cache Read and Write Policies Cache Read Cache Write Data is in the cache Data is not in the cache Data is in the cache Data is not in the cache Forward to CPU. Load Through: Forward the word as cache line is filled, -or- Fill cache line and then forward word. Write Through: Write data to both cache and main memory, -or- Write Back: Write data to cache only. Defer main memory write until block is flushed. Write Allocate: Bring line into cache, then update it, -or- Write No-Allocat Update main memory only.

14 Virtual Memory + Cache Memory 1. CPU instruction generates a virtual address. 2. Translation Lookaside Buffer (TLB) used to locate recently accessed page frames. 3. In case of a TLB miss, use page table(s) to find page frame for virtual address. TLB updated. Note: page frame may have been swapped to disk! 4. Virtual address is now converted into a physical address. 5. Search cache for recently accessed physical addresses. 6. In case of a cache miss, use main memory. Cache updated. UMBC, CMSC313, Richard Chang <chang@umbc.edu>

15 UMBC, CMSC313, Richard Chang Input/Output

16 Basic Issues in I/O Allow many components to communicate. Do not want to have n 2 /2 connections to connect n components together. Devices communicate a different speeds. Some devices transfer lots of data, others very few. UMBC, CMSC313, Richard Chang <chang@umbc.edu>

17 8-18 Chapter 8: Input and Output A Magnetic Disk with Three Platters Top surface not used Spindle Comb Head Surface 3 Surface 2 Surface 1 Surface 0 Air cushion Read/write head (1 per surface) 5 µm Surface Bottom surface not used Platter Direction of arm (comb) motion

18 8-22 Chapter 8: Input and Output Magnetic Tape A portion of a magnetic tape (adapted from [Hamacher, 1990]). File mark Frames Inter-record gap Record Record Record File

19 8-28 Chapter 8: Input and Output Mouse and Trackball A three-button mouse (left) and a three-button trackball (right). To host To host Buttons Mouse Mousepad (improves traction) Buttons Trackball

20 System Bus Issues Only n connections needed for n components. Bus can become a performance bottleneck. Synchronous vs asynchronous Bus arbitration. UMBC, CMSC313, Richard Chang <chang@umbc.edu>

21 8-3 Chapter 8: Input and Output Simple Bus Architecture A simplified motherboard of a personal computer (top view): Plug-in card I/O bus connector Integrated Circuits Memory CPU Motherboard Board traces (wires) I/O Bus Connectors for plug-in cards

22 8-4 Chapter 8: Input and Output Simplified Illustration of a Bus CPU Memory Disk Control (C 0 C 9 ) Address (A 0 A 31 ) Data (D 0 D 31 ) Power (GND, +5V, 15V)

23 8-5 Chapter 8: Input and Output 100 MHz Bus Clock Crystal Oscillator ns Logical 1 (+5V) Logical 0 (0V)

24 8-6 The Synchronous Bus Chapter 8: Input and Output Timing diagram for a synchronous memory read (adapted from [Tanenbaum, 1999]). Leading edge Φ Trailing edge T 1 T 2 T 3 Address Address valid Data Data valid MREQ RD Time

25 8-7 Chapter 8: Input and Output The Asynchronous Bus Timing diagram for asynchronous memory read (adapted from [Tanenbaum, 1999]). Address Memory address to be read MREQ RD MSYN Data Data valid SSYN Time

26 SCSI Bus 40 MB/sec 8-9 Bridge Based Bus Architecture 400-MHz Core AGP 2X Graphics 3200 MB/sec 3200 MB/sec 100-MHz System Bus AGP 512KB-2MB Cache 800 MB/sec Intel 440GX AGPset (Host Bridge) 400-MHz Core 533 MB/sec 800 MB/sec Chapter 8: Input and Output 512KB-2MB Cache 100 MHz 133 MB/sec 33-MHz PCI Bus 2GB 100-MHz SDRAM Bridging with dual Pentium II Xeon processors on Slot 2. SCSI Interface Snapshot Camera 1.5 MB/sec 33 MB/sec Mouse USB #2 USB #1 IDE Bus #1 PCI to ISA Bridge IDE Bus #2 33 MB/sec CD-ROM (Source: Ethernet Interface Hard Disk Hard Disk Keyboard ISA Bus 16.7 MB/sec Audio

27 8-8 Bus Arbitration Bus request (a) Arbiter Bus grant Chapter 8: Input and Output (a)simple centralized bus arbitration; (b) centralized arbitration with priority levels; (c) decentralized bus arbitration. (Adapted from [Tanenbaum, 1999]). (b) (c) Arbiter Bus grant level 0 Bus grant level k Bus request Busy +5V Bus grant n Bus request level 0 Bus request level k n n

28 Types of I/O Control Programmed I/O = polling Interrupt driven. DMA = Direct Memory Access. Channel I/O: uses dedicated I/O processors. UMBC, CMSC313, Richard Chang <chang@umbc.edu>

29 8-10 Enter Chapter 8: Input and Output Programmed I/O Flowchart for a Disk Transfer No Check status of disk Disk ready? Yes Send data from memory to disk (when writing) or from disk to memory (when reading). No Done? Yes Continue

30 8-11 Enter Chapter 8: Input and Output Interrupt Driven I/O Flowchart for a Disk Transfer Issue read or write request to disk. Do other processing, until disk issues an interrupt. Interrupt causes current processing to stop. Transfer data between disk and memory. Return from interrupt. Normal processing resumes. No Done? Yes Continue

31 8-12 Chapter 8: Input and Output DMA Transfer from Disk to Memory Bypasses the CPU CPU Memory Disk Without DMA With DMA Bus

32 8-13 Chapter 8: Input and Output DMA Flowchart for a Disk Transfer Enter CPU sets up disk for DMA transfer DMA device begins transfer independent of CPU CPU executes another process DMA device interrupts CPU when finished Continue

33 Buffering Many I/O devices have on-board memory. Communication can be done at memory-tomemory speeds. More expensive, requires local controller. I/O becomes more like networking. UMBC, CMSC313, Richard Chang

34 Performance Metrics Trends Next Time UMBC, CMSC313, Richard Chang

Chapter 8: Input and Output. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V.

Chapter 8: Input and Output. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V. 8-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring 8-2 Chapter Contents 8.1 Simple Bus Architectures 8.2 Bridge-Based Bus Architectures 8.3 Communication Methodologies 8.4 Case