Computer Organization and Microprocessors SYLLABUS CHAPTER - 1 : BASIC STRUCTURE OF COMPUTERS CHAPTER - 3 : THE MEMORY SYSTEM

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1 i SYLLABUS UNIT - 1 CHAPTER - 1 : BASIC STRUCTURE OF COMPUTERS Computer Types, Functional Units, Basic Operational Concepts, Bus Structures, Software, Performance, Multiprocessors and Multicomputers, Historical Perspective. CHAPTER - 2 : INPUT/OUTPUT ORGANIZATION Accessing I/O Devices, Interrupts, Processor Examples, Direct Memory Access, Buses, Interface Circuits, Standard I/O Interfaces. UNIT - 2 CHAPTER - 3 : THE MEMORY SYSTEM Basic Concepts, Semi Conductor RAM Memories, Read Only Memories, Speed, Size and Cost, Cache Memories, Performance Considerations, Virtual Memories, Memory Management Requirements, Secondary Storage. UNIT - 3 CHAPTER - 4 : 8085 ARCHITECTURE Introduction to Microprocessors and Microcontrollers, 8085 Processor Architecture, Internal Operations. CHAPTER - 5 : PROGRAMMING THE 8085 Introduction to 8085 Instructions, Addressing Modes and Programming Techniques With Additional Instructions.

2 UNIT - 4 ii CHAPTER - 6 : STACKS AND SUBROUTINES Stacks and Subroutines, Interfacing Peripherals, Basic Interfacing Concepts, Interfacing Output Displays, Interfacing Input Keyborads, Interrupts 8085 Interrupts, Programmable Interrupt Controller (8259A), Direct Memory Access (DMA), DMA Controller (Intel 8257), Interfacing 8085 With Digital to Analog and Analog to Digital Converters. CHAPTER - 7 : INTERFACING PERIPHERALS Stacks and Subroutines, Interfacing Peripherals, Basic Interfacing Concepts, Interfacing Output Displays, Interfacing Input Keyborads, Interrupts : 8085 Interrupts, Programmable Interrupt Controller (8259A), Direct Memory Access (DMA), DMA Controller (Intel 8257), Interfacing 8085 With Digital to Analog and Analog to Digital Converters. UNIT - 5 CHAPTER - 8 : PROGRAMMABLE PERIPHERAL AND INTERACING DEVICES Progrmmable Pheripheral Interface (Intel 8255A) Programmable Communication Interface (Intel 8251), Programmable Interval Timer (Intel 8253 and 8254), Programmable Keyboard/Display Controller (Intel 8279), Serial and Parallel Bus Standards RS 232C, IEEE 488.

3 iii CONTENTS UNIT - 1 [CH. H. - 1] ] [BASIC STRUCTURE OF COMPUTERS] INTRODUCTION COMPUTER ORGANIZATION Definition of Computer Organization and Computer Architecture Necessity of Computer Organization COMPUTER TYPES FUNCTIONAL UNITS BASIC OPERATIONAL CONCEPTS BUS STRUCTURES SOFTWARE PERFORMANCE Processor Clock Basic Performance Equation Pipelining and Superscalar Operations Clock Rate Instruction Set : CISC and RISC Compiler Performance Measurement MULTIPROCESSOR AND MULTICOMPUTERS HISTORICAL PERSPECTIVE Expected University Questions with Solutions

4 iv UNIT - 1 [CH. H. - 2] ] [INPUT / OUTPUT ORGANIZATION] ACCESSING I/O DEVICES Memory Mapped I/O Isolated or I/O Mapped INTERRUPTS Interrupt Hardware Enabling and Disabling Interrupts Handling Multiple Devices Interrupt Priority Controlling Device Request Exceptions Use of Interrupts in Operating System PROCESSOR EXAMPLES ARM Interrupt Structure Interrupt Structure Pentium Interrupt Structure DIRECT MEMORY ACCESS Bus Arbitration BUSES Synchronous Bus Asychronous Bus INTERFACE CIRCUITS Parallel Port Serial Port

5 v 2.7 STAND ANDARD ARD I/O INTERFACES CES Peripheral Component Interconnect (PCI) Bus Different Types of Data Transfer Signals on the PCI Bus PCI Operation Small Computer System Interface SCSI Types Universal Serial Bus (USB) USB Connections USB Features USB Hub USB Power Supply USB Packet Formats USB Packet Formats Expected University Questions with Solutions UNIT - 2 [CH. - 3] ] [THE MEMORY SYSTEM] BASIC CONCEPTS SEMICONDUCTOR OR RAM MEMORIES Internal Organization of Memory Chips Static Memories Asynchronous DRAM Synchronous DRAM (SDRAM) Structure of Larger Memories Memory System Considerations RAMBUS Memory

6 vi 3.3 READ ONLY MEMORIES ROM PROM (Programmable Read Only Memory EPROM EEPROM Flash Memory SPEED,, SIZE AND COST CACHE MEMORIES Mapping Functions Replacement Algorithms PERFORMANCE CONSIDERATIONS Memory Interleaving Hit Rate ate and Miss Penalty Caches on Processor Chip Other Enhancements VIRTUAL MEMORIES Address Translation ranslation Page Table Implementation Using TLB Address Translation Procedure MEMORY MANAGEMENT REQUIREMENTS SECONDAR ARY STORA ORAGE Magnetic Hard Disk Optical Disks CD Technology CD-ROM and Audio CD

7 vii CD-R (CD-Recordable) CD-RW (CD-Rewritable) DVD (Digital Versatile Disks) Magnetic Tapes apes Expected University Questions with Solutions UNIT - 3 [CH. H. - 4] ] [8085 ARCHITECTURE] INTRODUCTION TO MICROPROCESSORS AND MICRO CONTROLLERS Microprocessors Microcontrollers Difference Between Microprocessor and Microcontrollers PROCESSOR ARCHITECTURE Address Buffer Address/Data Buffer AD AD Registers Increment/Decrement Address Latch Instruction Register Arithmetic and Logical Unit (ALU) Instruction Decoder Timing and Control Unit Interrupt Control Serial I/O (Control) INTERNAL OPERATIONS Expected University Questions with Solutions

8 viii UNIT - 3 [CH. H. - 5] ] [PROGRAMMING THE 8085] INTRODUCTION TO 8085 INSTRUCTIONS Data Transfer Instructions Arithmetic Operations Logical Instructions Branch Instruction Jump Instructions Call and Return Instructions Restart Instruction ADDRESSING MODES AND PROGRAMMING TECHNIQUES WITH ADDITIONAL INSTRUCTIONS Addressing Modes Programming Techniques ADDITIONAL DATA A TRANSFER AND 16-BIT ARITHMETIC INSTRUCTIONS Loading the 16bit Data Into the Register Pair air Transferring the Data from Memory to Microprocessor Transferring the Data from Microprocessor to Memory or Directly into Memory Arithmetic Operations Related to Register Pairs Arithmetic Operations Related to Memory Logic Operations : Rotate Logic Operations : Compare INSTRUCTIONS AND TIMING Expected University Questions with Solutions

9 ix UNIT - 4 [CH. H. - 6] ] [STACKS AND SUBROUTINES] STACK SUBROUTINES Subroutine Documentation and Parameter Passing RESTAR ART,, CONDITIONAL CALL AND RETURN INSTRUCTIONS ADVANCED SUBROUTINE CONCEPTS Nesting Multiple Ending Subroutine Expected University Questions with Solutions UNIT - 4 [CH. - 7] ] [INTERFACING PERIPHERALS] BASIC INTERFACING CONCEPTS Peripheral or I/O Instruction (I/O Mapped I/O) I/O Execution Device Selection and Data Transfer Absolute Vs. Partial Decoding Input Interfacing Interfacing I/O s Using Decoders INTERFACING OUTPUT DISPLAYS YS INTERFACING INPUT KEYBOARD ARD INTERRUPTS RST (Restart) Instructions Multiple Interrupts and Priorities PROGRAMMABLE INTERRUPT CONTROLLER (8259A) Pin Diagram of 8259A Block Diagram of PIC (8259A) Interrupt Sequence in IC

10 x Priority Modes of IC Programming the 8259A Initialization Command Words (ICWs) Operational Command Words (OCWs) DIRECT MEMORY ACCESS (DMA) DMA Controller (Intel 8257) INTERFACING 8085 WITH DIGITAL TO ANALOG AND ANALOG TO DIGITAL CONVERTERS Digital to Analog Converter R/2R Ladder D/A Converter Analog to Digital Converter Types of ADC Expected University Questions with Solutions UNIT - 5 [CH. - 8] ] [PROGRAMMABLE PERIPHERAL AND INTERFACING DEVICES] PROGRAMMABLE PERIPHERAL INTERFACE CE (INTEL 8255 A) Architecture of 8255A Pin Diagram of 8255A Various Modes of Operations of 8255A Bit Set/Reset (BSR) Mode I/O Modes PROGRAMMABLE COMMUNICATION INTERFACE (INTEL 8251) Features of Pin Diagram of Internal Architecture of Read/Write Control Logic Data Bus Buffer

11 xi Modem Control Transmitter Section Receiver Section Programming of USART Mode Word Command Word Status Word PROGRAMMABLE INTERVAL TIMER (INTEL 8253 AND 8254) Signal Description of 8253/ Architecture of 8253/ Reading While Counting Operation of Mode O/Interrupt on Terminal Count Mode 1 / Programmable One-shot Mode 2 / Rate Generator Mode 3 / Square Wave Generator Mode 4 /Software Triggered Strobe Mode 5 / Hardware Triggered Strobe PROGRAMMABLE KEYBOARD/DISPLA ARD/DISPLAY Y CONTROLLER (INTEL 8279) Pin Diagram of Block Diagram of Keyboard Section Scan Section Display Section CPU Interface Section

12 xii Operating Modes Keyboard Modes Display Modes Timing Parameters Operation Overview Programing Formats and Description of Control Words Format and Description of Status Word ord SERIAL AND PARALLEL BUS STAND ANDARDS ARDS RS-232C IEEE Expected University Questions with Solutions

BASIC INTERFACING CONCEPTS

BASIC INTERFACING CONCEPTS Contents i SYLLABUS UNIT - I 8085 ARCHITECTURE Introduction to Microprocessors and Microcontrollers, 8085 Processor Architecture, Internal Operations, Instructions and Timings, Programming the 8085-Introduction