Chapter 8: Input and Output. Principles of Computer Architecture. Principles of Computer Architecture by M. Murdocca and V.

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1 8-1 Principles of Computer Architecture Miles Murdocca and Vincent Heuring

2 8-2 Chapter Contents 8.1 Simple Bus Architectures 8.2 Bridge-Based Bus Architectures 8.3 Communication Methodologies 8.4 Case Study: Communication on the Intel Pentium Architecture 8.5 Mass Storage 8.6 Input Devices 8.7 Output Devices

3 8-3 Simple Bus Architecture A simplified motherboard of a personal computer (top view): Plug-in card I/O bus connector Integrated Circuits Memory CPU Motherboard Board traces (wires) I/O Bus Connectors for plug-in cards

4 8-4 Simplified Illustration of a Bus CPU Memory Disk Control (C 0 C 9 ) Address (A 0 A 31 ) Data (D 0 D 31 ) Power (GND, +5V, 15V)

5 MHz Bus Clock Crystal Oscillator ns Logical 1 (+5V) Logical 0 (0V)

6 8-6 The Synchronous Bus Timing diagram for a synchronous memory read (adapted from [Tanenbaum, 1999]). Leading edge Φ Trailing edge T 1 T 2 T 3 Address Address valid Data Data valid MREQ RD Time

7 8-7 The Asynchronous Bus Timing diagram for asynchronous memory read (adapted from [Tanenbaum, 1999]). Address Memory address to be read MREQ RD MSYN Data Data valid SSYN Time

8 8-8 Bus Arbitration Bus request (a) Arbiter Bus grant (a)simple centralized bus arbitration; (b) centralized arbitration with priority levels; (c) decentralized bus arbitration. (Adapted from [Tanenbaum, 1999]). (b) (c) Arbiter Bus grant level 0 Bus grant level k Bus request Busy +5V Bus grant n Bus request level 0 Bus request level k n n

9 SCSI Bus 40 MB/sec 8-9 Bridge Based Bus Architecture 400-MHz Core AGP 2X Graphics 3200 MB/sec 3200 MB/sec 100-MHz System Bus AGP 512KB-2MB Cache 800 MB/sec Intel 440GX AGPset (Host Bridge) 400-MHz Core 533 MB/sec 800 MB/sec 512KB-2MB Cache 100 MHz 133 MB/sec 33-MHz PCI Bus 2GB 100-MHz SDRAM Bridging with dual Pentium II Xeon processors on Slot 2. SCSI Interface Snapshot Camera 1.5 MB/sec 33 MB/sec Mouse USB #2 USB #1 IDE Bus #1 PCI to ISA Bridge IDE Bus #2 33 MB/sec CD-ROM (Source: Ethernet Interface Hard Disk Hard Disk Keyboard ISA Bus 16.7 MB/sec Audio

10 8-10 Enter Programmed I/O Flowchart for a Disk Transfer No Check status of disk Disk ready? Yes Send data from memory to disk (when writing) or from disk to memory (when reading). No Done? Yes Continue

11 8-11 Enter Interrupt Driven I/O Flowchart for a Disk Transfer Issue read or write request to disk. Do other processing, until disk issues an interrupt. Interrupt causes current processing to stop. Transfer data between disk and memory. Return from interrupt. Normal processing resumes. No Done? Yes Continue

12 8-12 DMA Transfer from Disk to Memory Bypasses the CPU CPU Memory Disk Without DMA With DMA Bus

13 8-13 DMA Flowchart for a Disk Transfer Enter CPU sets up disk for DMA transfer DMA device begins transfer independent of CPU CPU executes another process DMA device interrupts CPU when finished Continue

14 8-14 Intel Memory and I/O Address Spaces Address FFFFFFFF Memory Space Address FFFF 0000 I/O Space

15 8-15 Standard Intel Pentium Read and Write Bus Cycles T1 T2 Ti T1 T2 Ti T1 CLK ADDR Valid Invalid Valid Invalid ADS# CACHE# W/R# Read Write BRDY# DATA TO CPU FROM CPU READ CYCLE IDLE WRITE CYCLE IDLE

16 8-16 Intel Pentium Burst Read Bus Cycle CLK T1 T2 T2 T2 T2 Ti ADDR Valid Invalid ADS# CACHE# W/R# Read BRDY# DATA TO CPU TO CPU TO CPU TO CPU READ READ READ READ

17 8-17 Intel Pentium Hold-Hold Acknowledge Bus Cycle CLK ADDR ADS# CACHE# W/R# T1 T2 Ti Ti Ti Ti T1 Valid Read BRDY# DATA TO CPU HOLD BUS REQ. HLDA READ CYCLE NEW BUS MASTER

18 8-18 A Magnetic Disk with Three Platters Top surface not used Spindle Comb Head Surface 3 Surface 2 Surface 1 Surface 0 Air cushion Read/write head (1 per surface) 5 µm Surface Bottom surface not used Platter Direction of arm (comb) motion

19 Voltage Voltage 8-19 Manchester Encoding (a) Straight amplitude (NRZ) encoding of ASCII F ; (b) Manchester encoding of ASCII F = F (a) Time = F (b) Time

20 8-20 Organization of a Disk Platter with a 1:2 Interleave Factor Sector Inter-sector gap Interleave factor 1: Track Inter-track gap Track

21 Bad blocks Free blocks Files Preamble 8-21 Master Control Block No. surfaces on disk = 4 No. tracks/surface = 814 No. sectors/track = 32 No. bytes/sector = 512 Interleave factor = 1:3 Filename Starting sector, or sector list Surface Track Sector xyz.p ab.c Creation Date Last Modified Owner Protections 11/14/93 11/14/93 16 RWX by 10:30:57 19:30:57 Owner 8/18/93 1/21/94 20 RX - All 16:03:12 14:45:03 W-Owner R = Read W = Write X = Execute

22 8-22 Magnetic Tape A portion of a magnetic tape (adapted from [Hamacher, 1990]). File mark Frames Inter-record gap Record Record Record File

23 8-23 Magnetic Drum Sector Tracks Fixed read/write heads (1 per track)

24 8-24 Spiral Format for Compact Disk

25 8-25 ECMA-23 Keyboard Layout Keyboard layout for the ECMA-23 Standard (2nd ed.). Shift keys are frequently placed in the B row. F E D C B A Z \ 1! 2 " 3 # 4 5 % 6 & 7 ' 8 ( 9 ) 0. = ^ Q W E R T Y U I O P + A S D F G H J K L ; < > Z X C V B N M,.? ' { [ * : } ] SP

26 8-26 The Dvorak Keyboard Layout " ',,.. P Y F G C R L? / } { A O E U I D H T N S - : ; Q J K X B M W V Z

27 8-27 Bit Pad with Puck Cable to host computer Puck Coil Buttons

28 8-28 Mouse and Trackball A three-button mouse (left) and a three-button trackball (right). To host To host Buttons Mouse Mousepad (improves traction) Buttons Trackball

29 8-29 Lightpen A user selects an object with a lightpen.

30 8-30 Touchscreen A user selects an object on a touchscreen. LEDs (sources) User breaks beams Detector

31 8-31 Joystick A joystick with a selection button and a rotatable rod:

32 8-32 Laser Printer Schematic of a laser printer (adapted from [Tanenbaum, 1999]). Page description from host computer Page composing circuitry Charged pattern Toner cartridge Stationary laser source Paper input The quick brown fox jumps Cleaner and discharger Rotating mirror Heated rollers Paper output

33 8-33 Cathode Ray Tube A CRT with a single electron gun: Horizontal deflection plate Electron gun Vertical deflection plate Grid Vacuum Phosphor coated screen Horizontal control Vertical control Intensity control

34 To electron gun (grid) control Output Address Output Input 8-34 Display Controller Display controller for a color monitor (adapted from [Hamacher et al., 1990]). Clock To horizontal deflection plate control Column counter (mod 640) One output pulse per 640 columns Row counter (mod 480) To vertical deflection plate control 10 9 Red Green Blue RAM LUT Input 8 Address RAM frame buffer Screen image loaded by computer LUT loaded from computer

CMSC 313 Lecture 26 DigSim Assignment 3 Cache Memory Virtual Memory + Cache Memory I/O Architecture

CMSC 313 Lecture 26 DigSim Assignment 3 Cache Memory Virtual Memory + Cache Memory I/O Architecture UMBC, CMSC313, Richard Chang CMSC 313, Computer Organization & Assembly Language Programming