x86 Architectures; Assembly Language Basics of Assembly language for the x86 and x86_64 architectures

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1 x86 Architectures; Assembly Language Basics of Assembly language for the x86 and x86_64 architectures

2 topics Preliminary material a look at what Assembly Language works with - How processors work»a moment of history - Programming model»the registers»the memory

3 The Processor and The System Unit

4 Computer Organization Programmer's View Fundamental components: - CPU - Memory - I/O ( everything else ) Possible connection schemes: - Single Controller (right) - Direct Memory Access (DMA) (below)

5 the Von Neumann Central Processing Unit a.k.a. CPU or Processor - (or microprocessor) Control unit interprets program instructions ALU performs numerical and logical operations Registers access program data von Neumann model: single connection to memory - the "Von Neumann Bottleneck" Control Unit Arithmetic Logic Unit Registers to/from memory

6 John von Neumann s IAS Machine Built at the Institute for Advanced Studies, Princeton, NJ Program instructions and data in single shared memory - ~5 Kilobytes

7 Data Flow 1. Instructions move from memory (through cache) into Control Unit 2. Operands move between memory and data registers 3. Instruction execution causes data movement from/to memory (sometimes) - Computations carry operands from registers (or memory) to ALU, FPU, then back to registers (or memory) - Input/Output operations move values between devices and registers, or between devices and memory locations

8 Modern CPU elements ALU, FPU, GPU - Do the computations General-Purpose Registers - Hold data for ALU, FPU Specialized Registers - Control Program Flow Control Unit - Controls everything Internal busses - Connect things Cache Data Registers Specialized Registers Control Unit - Alleviates Von Neumann bottleneck - Generally not visible to programmer cache GPU Arithmetic- Logic Units Floating- Point Units Memory (a.k.a. Store, Storage, or RAM)

9 Multi-core Processors Each "core" is a CPU One chip holds 2, 4, 8,... cores Cores share memory Cores may have local L1 cache, may share L2 and L3 cache A CPU plus a GPU forms a heterogeneous multicore processor

10 A 48-Core "System on a Chip"

11 SoC Building Blocks Based on ARMv8

12 The Falkor ARMv8 Processor

13 the Fetch-Execute Cycle The Control Unit's pulse: 1. Instruction address to Memory 2. Start read; increment instruction address 3. Decode instruction 4. Fetch operands 5. Command operation 6. Retire instruction» Write any results to registers/memory 7. Repeat with next instruction address

14 The Fetch-Execute Cycle, expanded

15 phase 1 Fetch

16 phase 2 Decode

17 phase 3 Execute

18 phase 4 Retire

19 Next Cycle: phase 1 Fetch

20 Pipelined Designs Separate circuits perform each stage of the fetch-execute cycle In a pipelined design the separate circuits work simultaneously, on sequential instructions

21 16 / 32 / 64-bit x86 Architectures Intel - 1 st microprocessors 1971: 4-bit : 8-bit 8008 (1974: 8080) 1978: 16-bit 8086 (1979: 8088) origin of the x86 architecture 1985: 32-bit basis of the IA-32 family 1989: (renamed i486) (Family 4) 1993: Pentium (P5 / Family 5) 1995: Pentium Pro (P6 / Family 6) 1999: Pentium III 2000: Pentium 4 (Family 15) 2005: 64-bit Pentium 4F, dual-core Pentium D compatible with x : Core Duo (Family 6) 2007: Core 2 Quad etc. AMD developed x86- compatible processors 1982: AMD contracted as second-source for 8086 & : Am386, clone of : K5, Pentium competitor 1997: K6 1999: Athlon (K7) Not socket-compatible with Intel processors 2003: 64-bit Opteron, Athlon 64 (K8) 1st x86-64 processors backwards-compatible with IA : dual-core Athlon 64 X2 2007: quad-core Opteron (K10) 2010: Fusion APU (CPU/GPU on shared chip) demonstrated

22 8086 Registers the direct ancestor

23 x86 (IA-32) Registers 32-bit Words

24 x86_64 Registers

25 Memory - the processor's primary storage RAM - Random Access Memory is an array of data-storage locations. - Each location is called a word.

26 Memory Organization The memory subsystem is a 1-dimensional array of storage locations - Each location has a unique address (or "array index") - Each location is made up of m bits (m >= 1) - Location's contents is any one of 2 m bit patterns Memory can hold: - Programs: bit patterns represent instructions - Data: bit patterns represent numbers, characters, etc. Volatile contents: R/W memory, or RAM - DRAM is common for main memory Nonvolatile (unchangeable): Read-Only, or ROM - PROM, EEPROM, Flash erasable/reprogrammable ROM

27 Overall Memory Usage - Linux

28 How a program occupies memory When a program runs it occupies a block of RAM The block is divided into instructions, data, and stack segments, each in part of the memory

29 Dividing up the program memory Each function, including main(), has its own unchanging portion of the instruction memory - Any global variables occupy memory similar to instruction memory. Function-local variables exist in the stack only while the function is executing

30 Memory Usage: the IBM PC s Memory Map The IBM PC design designated various ranges within the 8088's 1MB memory address space for specific uses. Some of the ranges are "populated", some are empty i.e., there is no physical memory at those addresses. This is all justified by 640K should be enough for anyone.

80x86 Memory Spaces 80386 and later - 32 Address bits - 2 32 addresses: 0000 0000h.

31 80x86 Memory Spaces and later - 32 Address bits addresses: h.. FFFF FFFFh Address bits addresses: h.. FF FFFFh Original 8086, etc Address bits addresses: h.. F FFFFh

32 the 80x86 / MS-DOS Interrupt Vector Table

33 What uses the Interrupt Vector Table? DOS originally was dependent on the IVT for basic services such as Disk access As DOS became more sophisticated, it added its own DOS services for higher-level operations - Based on Interrupt 0x21, a.k.a. 21h Modern operating systems largely bypass the IVT - The first few interrupts are Hardware Interrupts, and must be handled - Linux uses Interrupt 0x80 for system calls

Processing Unit CS206T

Processing Unit CS206T Microprocessors The density of elements on processor chips continued to rise More and more elements were placed on each chip so that fewer and fewer chips were needed to construct