The von Neumann Architecture. IT 3123 Hardware and Software Concepts. The Instruction Cycle. Registers. LMC Executes a Store.

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1 IT 3123 Hardware and Software Concepts February 11 and Memory II Copyright 2005 by Bob Brown The von Neumann Architecture PC IR Control Unit Command Memory ALU Notice: This session is being recorded. The Instruction Cycle The von Neumann Instruction Cycle Fetch: Get an instruction from the memory location pointed by the program counter and advance the program counter Decode: Determine what operation code is present, and what data to use Execute: Perform the commanded operation Registers : receives results of arithmetic operations (calculator display) (If there s more than one, they re called general registers.) Program counter: address of the next instruction Instruction register: instruction currently being executed Registers Memory address register (): address to read from or write to in memory Memory data register (): holds data To be written to memory. That is read from memory. LMC Executes a Store 1

2 The LMC Executes a Store 01 Command Fetch the Instruction The PC (01) is copied to the by the control unit. The control unit commands the memory to read; it knows what to read from the ; it reads from location 01 Wait for memory to complete. (CU commands PC to increment while waiting.) Memory delivers contents of 01 (399) to The Fetch Phase 01+1 Read Decode Instruction The contents of the (399) are copied to the Instruction Register The 399 is split up in the IR into an operation code (3) and an address (99) The Decode Phase The control unit is hard-wired to recognize 3 as the store operation. The control unit copies the contents of the accumulator to the The control unit copies the address portion of the IR to the The control unit commands the memory to write, and waits for the write operation to complete. 2

3 99 Write The memory unit uses the address in the (99) and the data in the () to update memory The Cycle Continues: Fetch The program counter now contains 02 (because it was updated while we were waiting for memory in the previous fetch) The control unit copies the contents of the program counter to the. The control unit commands the memory to read, fetching the next instruction. The CU commands the PC to increment while waiting for memory to complete its cycle. The Cycle Continues 02 Read 99 Instructions Direction given to a computer Causes electrical signals to be sent through specific circuits for processing Instruction Set: The collection of instructions a given computer can perform. (LMC has ten instructions; the list of them is its instruction set.) 3

4 Instruction Set Design defines functions performed by the processor Differentiates computer architecture by the Number of instructions Complexity of operations performed by individual instructions Data types supported Format (layout, fixed vs. variable length) Use of registers Addressing (size, modes) Elements of an Instruction Operation Code (op-code): Commands the control unit and the ALU what to do Operands: tell the location of the data to be used in the instruction. Source operand: where to get the data Result operand: where to put the result (Also called the destination operand.) The operands are (usually) addresses. Operand Addresses Addresses may be explicit or implicit Explicit: encoded in the instruction. (The LMC memory address is explicit.) Implicit: implied by the nature of the operand. (The LMC uses the calculator display implicitly.) Addresses may refer to memory or to registers. General Form of an Instruction OP-CODE Source Operand 4 bits 20 bits Result Operand Instruction Format Specific to a particular family of computers (architecture) Specifies the length of the op-code And the size and number of operand fields A single computer may have several different instruction formats. Complex Instruction-Set Computers Many different kinds of instructions Many different instruction formats Several different instruction lengths A few different operation code lengths Often things done in high-level languages can be performed in one instruction. Emphasis is on flexibility 4

5 CISC Instruction Formats Reduced Instruction-Set Computers A few kinds of instructions A small number of formats All instructions are the same length All operation codes are the same length High-level language statements generally require several instructions Emphasis is on speed RISC Instruction Formats Categories of Instructions Data transfer instructions Arithmetic instructions Logical operations Program control Stack manipulation and machine control Multiple-data instructions Data Transfer Instructions Move data between registers in Transfer data from memory to a register (load) Transfer data from a register to memory (store) Size of a single transfer: generally the size of a data register; a word Words are 8, 16, 32, 64, or 128 bits 32-bit words are currently most common Arithmetic Instructions The usual suspects: + / * Separate instructions for integer and floating point operands. Shift and rotate instructions One bit shift left multiplies by two One bit shift right divides by two Rotate: Bits shifted out one end are used for replacement bits at the other end. Increment, complement, etc. 5

6 Shift and Rotate Instructions Logical Operations Logical AND and or of two operands Sometimes others: XOR, NOR, NOT Relational operations: > < = Testing for zero, positive, negative Program Control Branch instructions; conditional and unconditional Call instructions (save program counter someplace) Stack Manipulation Special instructions for dealing with LIFO data structures. (A stack is a good place to store program counters for subroutine linkage!) Push Pop and Machine Control Transfers from registers to devices Direct memory access (DMA) The device communicates with memory independent of the Machine state switching (protected instructions) Interrupt control State saving Halt Multiple-Data Instructions Perform the same operation on multiple data items simultaneously (Example: Intel MMX) Commonly used in vector and array processing SIMD: Single-instruction, multiple data 6

7 Multiple Data Instructions Questions 7