2. Recommended Design Flow

Transcription

1 2. Recommended Design Flow This chapter describes the Altera-recommended design low or successully implementing external memory interaces in Altera devices. Altera recommends that you create an example top-level ile with the desired pin outs and all interace IP instantiated, which enables the Quartus II sotware to validate your design and resource allocation beore PCB and schematic sign o. Use the on page 2 6, to veriy whether you have perormed all the recommended steps in creating a working and robust external memory interace. Figure 2 1 shows the design low to provide the astest out-o-the-box experience with external memory interaces in Altera devices. This topic directs you where to ind inormation on how to perorm each step o the recommended design low. The low assumes that you are using Altera IP to implement the external memory interace. For design examples that ollow the recommended design low in this chapter, reer to Volume 6: Design Flow Tutorials o the External Memory Interace Handbook. July 2010 Altera Corporation About This Handbook

2 2 2 Chapter 2: Recommended Design Flow Figure 2 1. External Memory Interaces Design Flowchart Start Design Select Device Instantiate PHY and Controller Determine Board Layout UniPHY-Based Designs Only on Arria II GX and Stratix IV Devices Perorm Board Level Simulations SOPC Builder Flow Speciy Parameters MegaWizard Flow Speciy Parameters Adjust Termination and Drive Strength No Do Signals Meet Electrical Requirements? Complete SOPC Builder System Yes Optional Perorm Functional Simulation Yes Add Constraints and Compile Design Does Simulation Give Expected Results? Veriy Timing No Debug Design Does the Design Have Positive Margin? No Adjust Constraints Optional Yes Perorm Timing Simulation Yes Veriy Design Functionality on Board Does Simulation Give Expected Results? Is Design Working? No Debug Design No Yes Debug Design Design Done About This Handbook July 2010 Altera Corporation

3 Chapter 2: Recommended Design Flow 2 3 Select a Device Select a Device For more inormation on selecting a device, reer to the Device and Pin Planning section in volume 2 o the External Memory Interace Handbook. Determine Board Layout Altera recommends prelayout SI simulations (line simulations) should take place beore board layout and that you use these parameters and rules during the initial design development cycle. Advanced I/O timing and board trace models now directly impact device timing closure. In addition, the termination scheme that you use, the drive strength setting on the FPGA, and the loading seen by the driver can directly aect the signal integrity. You must understand the tradeos between the dierent types o termination schemes and the eects o output drive strengths and loading, to choose the best possible settings or your designs. For more inormation, reer to the Board Layout Guidelines section in volume 2 o the External Memory Interace Handbook. Perorm Board-Level Simulations To determine the correct board constraints, perorm board-level simulations to see i the settings provide the optimal signal quality. With many variables that can aect the signal integrity o the memory interace, simulating the memory interace provides an initial indication o how well the memory interace perorms. There are various EDA simulation tools available to perorm board-level simulations. The simulations should be perormed on the data, data strobe, control, command, and address signals. I the memory interace does not have good signal integrity, adjust the settings, such as drive strength setting, termination scheme or termination values to improve the signal integrity (realize that changing these settings aects the timing and it may be necessary to go back to the timing closure i these change). For detailed inormation about understanding the dierent eects on signal integrity design, reer to the Board Layout Guidelines section in volume 2 o the External Memory Interace Handbook. Enter topology inormation rom your board-level simulations into the Quartus II board trace model inormation. The typical inormation required includes, but is not limited to, the ollowing values: Near and ar trace lengths Near and ar trace distributed inductance Near and ar trace distributed capacitance Near end deration capacitor values (i itted) Far end capacitive (IC) load Far end termination values July 2010 Altera Corporation About This Handbook

4 2 4 Chapter 2: Recommended Design Flow Adjust Termination and Drive Strength Device-Side Termination Memory-Side Termination Many Altera devices support both series and parallel OCT resistors to improve signal integrity. OCT eliminates the need or external termination resistors on the FPGA side, which simpliies board design and reduces overall board cost. You can dynamically switch between the series and parallel OCT resistor depending on whether the FPGA devices are perorming a write or a read operation. The OCT eatures oer user-mode calibration to compensate or any variation in VT during normal operation to ensure that the OCT values remain constant. The parallel and series OCT eatures are available in either 25 or 50 Ω settings. The DDR2, DDR3 SDRAM, and QDR II SRAM have a dynamic parallel ODT eature that you can turn on when the FPGA is writing to the memory and turn o when the FPGA is reading rom the memory. To urther improve signal integrity, DDR2 SDRAM supports output drive strength control so that the driver can better match the transmission line. DDR3 SDRAM devices additionally support calibrated output impedances. For more inormation on available settings o the ODT, the output drive strength eatures, and the timing requirements or driving the ODT pin, reer to your DDR2 or DDR3 SDRAM datasheet. Adjust Termination and Drive Strength Although the recommended terminations are based on the simulations and experimental results, you must perorm simulations, either using I/O buer inormation speciication (IBIS) or HSPICE models, to determine the quality o signal integrity on your designs. 1 Any changes made to the board should also be made in the board trace model in the Quartus II sotware. For inormation on Altera-recommended terminations or memory interaces, reer to the Board Layout Guidelines section in volume 2 o the External Memory Interace Handbook. Instantiate PHY and Controller Ater selecting the appropriate device and memory type, create a project in the Quartus II sotware that targets the device and memory type. When implementing external memory interaces, Altera recommends that you use Altera memory interace IP, which includes a PHY that you can use with the Altera high-perormance controller or with your own custom controller. Instantiating the PHY and controller includes the ollowing steps: Speciy parameters Perorm unctional simulation Add constraints and compile design About This Handbook July 2010 Altera Corporation

5 Chapter 2: Recommended Design Flow 2 5 Veriy Timing For more inormation about speciying parameters, adding constraints, and compiling, reer to the DDR and DDR2 SDRAM High-Perormance Controller and ALTMEMPHY IP User Guide section and the DDR3 SDRAM High-Perormance Controller and ALTMEMPHY IP User Guide section in volume 3 o the External Memory Interace Handbook. For more inormation about simulation, reer to the Simulation section in volume 4 o the External Memory Interace Handbook. Veriy Timing For more inormation about veriying timing, reer to the Timing Analysis section in volume 4 o the External Memory Interace Handbook. Adjust Constraints In the timing report o the design, you can see the worst case setup and hold margin or the dierent paths in the design. I the setup and hold margin are unbalanced, achieve a balanced setup and hold margin by adjusting the phase setting o the clocks associated with these paths. For example, or the address and command margin, the address and command outputs are clocked by an address and command clock that can be dierent with respect to the system clock, which is 30. The system clock controls the clock outputs going to the memory. I the report timing script indicates that using the deault phase setting or the address and command clock results in more hold time than setup time, adjust the address and command clock to be less negative than the deault phase setting with respect to the system clock, so that there is less hold margin. Similarly, adjust the address and command clock to be more negative than the deault phase setting with respect to the system clock i there is more setup margin. For more inormation on adjusting constraints, reer to the Timing Analysis section in volume 4 o the External Memory Interace Handbook. Perorm Timing Simulation This step is optional, but recommended to ensure that the IP is working properly. This step only applies to UniPHY-based interaces (on Arria II GX and Stratix IV devices only), as ALTMEMPHY-based interaces do not support timing simulation. For more inormation about simulating, reer to the Simulation section in volume 4 o the External Memory Interace Handbook. Veriy Design Functionality Perorm system level veriication to correlate the system against your design targets, using the Altera SignalTap II logic analyzer. For more inormation about using the SignalTap II analyzer, reer to the Debugging section in volume 4 o the External Memory Interace Handbook. July 2010 Altera Corporation About This Handbook

6 2 6 Chapter 2: Recommended Design Flow This topic contains a design checklist that you can use when implementing external memory interaces in Altera devices. Done Select Device 1. Select the memory interace requency o operation and bus width. For inormation about selecting memory, reer to the Memory Standard Overview section in volume 1 o the External Memory Interace Handbook. 2. Select the FPGA device density and package combination that you want to target. For inormation about selecting an Altera device, reer to the Device and Pin Planning section in volume 2 o the External Memory Interace Handbook. 3. Ensure that the target FPGA device supports the desired clock rate and memory bus width. Also the FPGA must have suicient I/O pins or the DQ/DQS read and write groups. For detailed device resource inormation, reer to the relevant device handbook chapter on external memory interace support. For inormation about supported clock rates or external memory interaces, reer to the External Memory Interace System Speciications section in volume 1 o the External Memory Interace Handbook. Determine Board Layout 4. Select the termination scheme and drive strength settings or all the memory interace signals on the memory side and the FPGA side. 5. Ensure you apply appropriate termination and drive strength settings on all the memory interace signals, and veriy using board level simulations. 6. Use board level simulations to pick the optimal setting or best signal integrity. On the memory side, Altera recommends the use o external parallel termination on input signals to the memory (write data, address, command, and clock signals). For inormation, reer to the Board Layout Guidelines section in volume 2 o the External Memory Interace Handbook. Perorm Board Level Simulations 7. Perorm board level simulations, to ensure electrical and timing margins or your memory interace 8. Ensure you have a suicient eye opening using simulations. Use the latest FPGA and memory IBIS models, board trace characteristics, drive strength, and termination settings in your simulation. Any timing uncertainties at the board level that you calculate using simulations must be used to adjust the input timing constraints to ensure the accuracy o Quartus II timing margin reports. For example crosstalk, ISI, and slew rate deration. For inormation, reer to the Board Layout Guidelines section in volume 2 o the External Memory Interace Handbook. Instantiate PHY and Controller About This Handbook July 2010 Altera Corporation

7 Chapter 2: Recommended Design Flow 2 7 Done 9. Parameterize and instantiate the Altera external memory IP or your target memory interace. You have the ollowing three choices in implementing a memory interace in the Quartus II sotware: Using the Altera memory controller and PHY. For inormation about how to implement a speciic memory interace, reer to Volume 3: Implementing Altera Memory Interace IP o the External Memory Interace Handbook. The Parameter Settings chapter o each section describes the IP supported eatures page by page. Using the Altera PHY with your own custom controller. For inormation about how to implement a speciic memory interace, reer to Volume 3: Implementing Altera Memory Interace IP o the External Memory Interace Handbook. The Parameter Settings chapter o each section describes the IP supported eatures page by page. The Functional Description chapter describes the workings o the PHY and how you can connect a custom controller to the PHY. Implement a custom PHY and custom controller. For inormation about creating custom IP, reer to Volume 5: Implementing CustomMemory Interace PHY o the External Memory Interace Handbook. 10. Ensure that you perorm the ollowing actions: Pick the correct memory interace data rates, width, and conigurations. For DDR, DDR2, and DDR3 SDRAM interaces, ensure that you derate the tis, tih, tds, and tdh parameters, as necessary. Include the board skew parameter or your board. 11. Connect the PHY's local signals to your driver logic and the PHY's memory interace signals to top-level pins. Ensure that the local interace signals o the PHY are appropriately connected to your own logic. I the ALTMEMPHY megaunction is compiled without these local interace connections, you may encounter compilation problems, when the number o signals exceeds the pins available on your target device. For more inormation about the example top-level ile, reer to the Functional Description chapter or the relevant memory controller. You may also use the example top-level ile as an example on how to connect your own custom controller to the Altera memory PHY. Perorm Functional Simulation 12. Simulate your design using the RTL unctional model. Use the IP unctional simulation model with your own driver logic, testbench, and a memory model, to ensure correct read and write transactions to the memory. You may need to prepare the memory unctional model by setting the speed grade and device bus mode. For more inormation about simulation, reer to the Simulation section in volume 4 o the External Memory Interace Handbook. Add Contraints July 2010 Altera Corporation About This Handbook

8 2 8 Chapter 2: Recommended Design Flow Done 13. Add timing constraints. The wizard-generated.sdc ile adds timing constraints to the interace. However, you may need to adjust these settings to best it your memory interace coniguration. 14. Add pin settings and DQ group assignments. The wizard-generated.tcl ile includes I/O standard and pin loading constraints to your design. 15. Ensure that generic pin names used in the constraint scripts are modiied to match your top-level pin names. The loading on memory interace pins is dependent on your board topology (memory components). 16. Add pin location assignments. However, you need to assign the pin location assignments manually using the Pin Planner. 17. Ensure that the example top-level ile or your top-level logic is set as top-level entity. 18. Adjust optimization techniques, to ensure the remaining unconstrained paths are routed with the highest speed and eiciency: a. On the Assignments menu click Settings. b. Select Analysis & Synthesis Settings. c. Select Speed under Optimization Technique. d. Expand Fitter Settings. e. Turn on Optimize Hold Timing and select All Paths.. Turn on Optimize Fast Corner Timing. g. Select Standard Fit under Fitter Eort. 19. Provide board trace delay model. For accurate I/O timing analysis, you speciy the board trace and loading inormation in the Quartus II sotware. This inormation should be derived and reined during your board development process o prelayout (line) simulation and inally post-layout (board) simulation. Provide the board trace inormation or the output and bidirectional pins through the board trace model in the Quartus II sotware. For more inormation, reer to the Add Constraints chapter or the relevant memory standard in volume 3 o the External Memory Interace Handbook or reer to Volume 6: Design Flow Tutorials. Compile Design and Veriy Timing 20. Compile your design and veriy timing closure using all available models. 21. Run the wizard-generated <variation_name>_report_timing.tcl ile, to generate a custom timing report or each o your IP instances. Run this process across all device timing models (slow 0 C, slow 85 C, ast 0 C). 22. I there are timing violations, adjust your constraints to optimize timing 23. As required, adjust PLL clock phase shit settings or appropriate timing and location assignments margins or the various timing paths within the IP. For inormation, reer to the Timing Analysis section in volume 4 o the External Memory Interace Handbook. Perorm Timing Simulation About This Handbook July 2010 Altera Corporation

9 Chapter 2: Recommended Design Flow 2 9 Done 24. Perorm gate-level or timing simulation to ensure that all the memory transactions meet the timing speciications with the vendor's memory model. Timing simulation is only supported with UniPHY-based memory interaces. For more inormation about simulation, reer to the Simulation section in volume 4 o the External Memory Interace Handbook. Veriy Design Functionality 25. Veriy the unctionality o your memory interace in the system For more inormation, reer to Volume 6: Design Flow Tutorials. in the External Memory Interace Handbook. July 2010 Altera Corporation About This Handbook

10 2 10 Chapter 2: Recommended Design Flow About This Handbook July 2010 Altera Corporation