Microtronix Streaming Multi-Port SDRAM Memory Controller

Transcription

1 Microtronix Streaming Multi-Port SDRAM Memory Controller User Manual V Meadowbrook Drive, London, Ontario N6L 1E3 CANADA

2 Document Revision History This user guide provides basic information about using the Microtronix Streaming Multi-port SDRAM Memory Controller IP Core (PN: 6248-xx-xx). The table below shows the revision history. Date Description April 2007 Initial Release Version 1.0 May 2007 August 2007 September 2007 November 2007 December 2007 May 2008 August 2008 March 2009 June 2009 July 2009 July 2009 February 2010 July 2010 August 2011 May 2012 October, 2013 Version 1.1 Added Cyclone III support Version 1.2 Added Quartus 7.1 patch info Version 1.3 Added 10 ports and byte enable support Version 1.4 Updated timing diagrams Version 1.5 Changed BUSY behavior Version 1.6 Added Mobile DDR deep power down support Version 1.7 Added support for Stratix III & Arria GX Version 1.8 Changed BUSY behavior Version 1.9 Clarified init address and burst length requirements for DDR2 Version 2.0 Added SDC file creation Version 2.1 Updated write port description Version 2.2 Added Cyclone IV support Version 2.3 Added Arria II GX support Version 2.4 Added Stratix IV support Version 2.5 Added SystemVerilog version Version 4.2 Add Cyclone V support Page 2 of 30

3 How to Contact Microtronix Sales Information: Support Information: Website General Website: FTP Upload Site: Phone Numbers General: (001) Fax: (001) Typographic Conventions Path/Filename [SOPC Builder]$ <cmd> Code A path/filename A command that should be run from within the Cygwin Environment. Sample code. Indicates that there is no break between the current line and the next line. Page 3 of 30

4 Table of Contents Document Revision History... 2 How to Contact Microtronix Website... 3 Phone Numbers... 3 Typographic Conventions... 3 Features... 5 Introduction... 6 Local Ports... 8 Write Port... 8 Read Port Design Flow DQ/DQS Pin Assignments SDR SDRAM DDR, DDR2 and Mobile SDRAM Timing Performance Resource Requirements Simulation Verification Installation License FAQ Page 4 of 30

5 Features Support for Single Data-Rate, Double Data-Rate DDR & DDR2 and Mobile DDR SDRAM Memory Devices Unique DDR/DDR2 Round Trip Independent Capture Scheme Advanced Performance Architecture o o o o Optimized for streaming transfers Up to 10 port interfaces User configurable FIFO for each system port Operates with Memory clock independent of system clock speed Support for OpenCore Plus evaluation Quartus reference designs Simulation Model TimeQuest Timing Analyzer support for DDR, DDR2 and Mobile DDR devices Supported devices: o o o Cyclone II, III, IV, V Stratix II, III and IV Arria GX, Arria II GX Page 5 of 30

6 Introduction The Microtronix Streaming Multi-port SDRAM Controller IP-Core (PN: 6248-xx-xx)) provides a complete, easy-to-use solution to interface with a wide variety of SDRAM memory devices. Both single data-rate (SDR) and double data-rate (DDR, DDR2 & Mobile DDR) devices are supported. The memory controller is designed to support high-performance multiport system configurations using a native RD/WR local bus interface. It is optimized for Altera Stratix and Cyclone family of programmable logic devices. The SDRAM Memory Controller handles all memory tasks, including refresh and device initialization cycles. The IP Core is designed to operate asynchronous to the system clock. Clocking the IP-Core at the same frequency as the SDRAM memory maximizes system performance. The DDR Memory Controller IP uses a unique source-synchronous design architecture to capture the high-speed double-data rate data from the memory device independent of the memory round-trip. This proprietary technology simplifies memory interface design by removing the need for extra resynchronization clocks and maximizes the performance of the memory system. Figure 1: Block Diagram of Streaming Multi-port SDRAM IP Core Page 6 of 30

7 Figure 2: SDR IP Core Signal Connections Figure 3: DDR / DDR2 IP Core Signal Connections Page 7 of 30

8 Local Ports The SDRAM memory controller has up to ten local ports. Each port can be configured as a read or write port. The ports are optimized for streaming transfers. An internal FIFO acts as a bridge between the local interface and the SDRAM memory. In single-data-rate mode the ports have the same width as the memory data path. For all doubledata-rate modes the data width is twice the width of the SDRAM memory data bus. Arbitration between ports occurs in a round-robin manner in the SDRAM clock domain. Write Port Figure 4 shows the beginning of a write transfer. The write clock is unrelated to the SDRAM memory clock. On the rising edge of the INIT signal the starting address is latched. Any remaining data in the FIFO is flushed to the SDRAM memory. Data can be written by activating the write enable (WE). The write enable can be deasserted and reasserted as needed. The byte enable (BE) is active high. Figure 4: Write Initialization Transfers are not limited to the size of the internal FIFO. The write port will transfer data to the SDRAM as needed in blocks of half the FIFO size. When the write port is unable to accept more data into its FIFO, the BUSY signal is asserted. Once more data has been moved from the FIFO into the SDRAM, BUSY is deasserted. Writing data while BUSY is asserted can overrun the FIFO and cause undefined behavior. Note that BUSY will be asserted one cycle ahead of the FIFO being full, allowing WE to be deasserted on the following cycle (Figure 5). Page 8 of 30

9 Figure 5: Write Busy Figure 6 shows how to force a flush of the write FIFO by asserting INIT after completing a write transfer. Once the INIT is signaled, the port will write out all data remaining to SDRAM. It is not necessary to perform this flush cycle as the data will be flushed the next time INIT is asserted, but it may be useful for coordinating between multiple ports. If BUSY is still asserted from the previous writes, the flush should be deferred until BUSY is deasserted. Figure 6: Write Flush The write port has minimum delays between events that must be ensured for proper operation. These delays are listed in Table 1. Page 9 of 30

10 Table 1: Write Port Timing Parameter Description Delay Ti-w INIT to WE delay 1 clock cycle Tw-i WE to INIT delay 2 clock cycles Tb-i BUSY to INIT delay 1 clock cycle DDR2 Limitations When the memory architecture is DDR2, each write must start on an even address and contain an even number of words. This is due to DDR2 s minimum burst size of four. Read Port Figure 7 shows a read transfer. The read port clock is independent of the SDRAM memory clock domain. Upon a rising edge of the INIT signal the starting address is latched and the read port starts prefetching the data from the SDRAM memory. This is indicated by the BUSY signal. There is a delay between the rising edge of INIT and the rising edge of BUSY, see Table 2 below. After the BUSY signal is de-asserted by the read port, data can read by activating the read enable (RE). The read port will assert the data enable (DE) to indicate valid read data. DE assertion will be delayed from RE (see Table 2). DE will be asserted for the same number of clock cycles that RE is asserted. The read enable can be deasserted and reasserted as needed. Figure 7: Read Initialization Transfers are not limited to the size of the internal FIFO. After the initial prefetch, the read port will fetch data from the SDRAM as needed in blocks of half the FIFO size. The BUSY signal is asserted when data Page 10 of 30

11 is no longer available in the FIFO. Once more data is read from the SDRAM, BUSY will be deasserted. Reading while BUSY is asserted can underrun the FIFO and produce undefined behavior. Figure 8: Read Busy Once the last word of data is read from the read port, a new transfer can begin immediately by asserting INIT. If BUSY is still asserted from the previous read transfer, the INIT sequence should be deferred until BUSY is deasserted. Figure 9: Read Complete The UNDERRUN signal is activated when the FIFO has been read empty and is still waiting on data from SDRAM. An INIT will clear the UNDERRUN condition. Page 11 of 30

12 Table 2: Read Port Timing Parameter Description Delay Ti-b INIT to BUSY delay 2 clock cycles Tr-d RE to DE delay 3 clock cycles DDR2 Limitations When the memory architecture is DDR2, each read must start on an even address and contain an even number of words. This is due to DDR2 s minimum burst size of four. Design Flow The following steps describe how to integrate the SDRAM controller in a Quartus project. Open a windows command prompt or linux terminal window. Browse to the SDRAM wizard directory <install_dir>/wizard Start the wizard by typing java jar mtx_sdram_gui.jar Figure 10: Wizard Overview Page 12 of 30

13 Click on the Project tab. Use the browse button to select a new project or load an existing project. Select Device, Speed Grade and Language Figure 11: Project Tab Page 13 of 30

14 Click on the Memory tab to select the SDRAM memory properties. All of the properties should match those of the SDRAM devices on the board. Figure 12: Memory Tab The data width should be selected to reflect the total width of the memory data path. The total devices parameter is the number of SDRAM chips in parallel that make up the memory bank. The DQS signals per device parameter must be set to the number of DQS signals on one memory chip on the board. The most common configuration is one DQS signal per eight bits of data width. For example, a board with two 16-bit memory chips in Page 14 of 30

15 parallel would have a data width of 32, a total devices count of 2 and a DQS per device count of 2. The number of clock pairs indicates the total number of differential clock pairs (CLK_P/CLK_N) connected to all memory devices. It will depend on the board s memory architecture. A single memory device would only have one clock pair whereas a standard DDR2 DIMM would have three clock pairs. The Reduced Drive Strength option is used to reduce the memory output drive strength. This option is used in light load memory configurations. The Deep Power Down Support option is used to enable support for the deep power down mode of Mobile DDR. This option adds two additional signals to the top-level SOPC block. A high level on the CONTROL_DPD input is used to signal the memory controller to put the Mobile DDR into deep power down mode. The CONTROL_POWER_STATE output indicates when the SDRAM device is powered and initialized. When the device is in deep power down mode the CONTROL_POWER_STATE output will be low. After deasserting CONTROL_DPD to return to normal power mode, the user must wait until CONTROL_POWER_STATE returns to a high level before attempting to access SDRAM. Note: Mobile DDR does not retain data in deep power down mode. The On-Die Termination Support option is used to support DDR memory devices incorporating on-die termination. The available termination options are 50, 75 or 150 ohms. The SDRAM GUI uses a prefix (e.g. sdram_) for the names of all memory interface pins and it expects that these pins have a fixed name as shown in Table 3. The pin prefix can be modified on the Memory tab in the GUI. Page 15 of 30

16 Table 3: SDRAM Pins SDRAM Pin Function SDRAM Pin Name (without prefix) Direction Polarity Clock Enable cke Output Active High Bank Address ba Output Active High Address a Output Active High Chip Select cs Output Active Low Row Address Strobe ras Output Active Low Column Address Strobe cas Output Active Low Write Enable we Output Active Low Data dq Bidirectional Active High Data Mask dm Output Active High Data Strobe dqs Bidirectional Active High SDR Clock Out clk_out Output Active High DDR Clock Out Positive clk_out_p Output Active High DDR Clock Out Negative clk_out_n Output Active Low On Die Termination odt Output Active High DQ/DQS Pin Assignments Unlike most SDRAM cores, the Microtronix memory controller is more flexible in the use of IO for the memory interface. For Stratix and Arria devices, the dedicated DQ / DQS pins must be used and all Quartus DQ-group rules must be obliged. For Cyclone only the dedicated DQS pins must be used. In this device family, the dedicated FPGA DQ IO pins are not required for the data, address and chip select signals. NOTE: On Cyclone devices the DQS signal requires the use of the DDL for a delay element. Therefore, use only the pins in the dataset labeled DQS / DPCLK as these have a delay element. Page 16 of 30

17 Click the Timing tab. Enter the SDRAM memory timing parameters. All timing parameters are found in the SDRAM memory datasheet. Figure 13: Timing Tab Page 17 of 30

18 The Local Ports tab configures the local bus interface. Up to ten ports can be selected. The buffer size selects the number of words that can be temporary held in the FIFO. A bigger buffer size gives more performance, but will also consume more memory resources and the duration of the busy state will be longer. Figure 14: Local Ports Tab Page 18 of 30

19 The SDC tab is used to enter the memory device specific timing parameters found in the datasheet supplied by the vendor of the memory device. This tab is an extension to the timing tab. The information entered under this tab is used in the Synopsys Design Constraint (SDC) script required by TimeQuest. The SDC script defines the timing constraints and specifications to validate the timing performance of the memory controller logic in the FPGA. The script is written in TCL command language and will be automatically generated when the SDRAM controller is added to the SOPC Builder system. SDC file creation is not supported for SDR memory. If desired, check the Enable SDC File Creation option (not supported for SDR memory). Enter the values for the SDC-specific parameters. Most values will come from the memory device data sheet. Clock cycle time is the period of the memory clock. PLL input clock period is the period of the clock used as input to the PLL that generates the memory clock. Figure 15: SDC File Tab Page 19 of 30

20 Click on Generate to start the SDRAM generation. The wizard writes a top level SDRAM entity. The wizard also generates a TCL script (<project>_assignments.tcl), which sets the Quartus II SDRAM assignments. If using a Cyclone II device and the DDR(2) architecture is chosen, a second TCL script (<project>_ddr_locations.tcl) is generated. This TCL script places the important DDR cells at the correct location in the device. It is automatically run after the first compilation. Start Quartus II and open the project. Add the SDRAM component to the project and connect the signals. If the selected language is VHDL, add the mtx_streaming_sdram_package to the project files (Assignments -> Settings -> Files). The mtx_streaming_sdram_package is located in the directory <install_dir>/synthesis Add the directory <install_dir>/synthesis to the Quartus project libraries for VHDL. Add the directory <install_dir>/synthesis/systemverilog for SystemVerilog (Assignments -> Settings -> Libraries) Run the TCL script <project>_assignments.tcl (Tools -> TCL Scripts ) If the design is using TimeQuest, the generated SDC file must be customized to match your project. At the minimum the following lines must be modified. create_clock -name clk1 -period $pll_ref_clk [get_ports CLK] set system_clk {inst1 altpll_component auto_generated pll1 clk[2]} set sdram_clk {inst1 altpll_component auto_generated pll1 clk[0]} set sdram_write_clk {inst1 altpll_component auto_generated pll1 clk[1]} Replace CLK with the clock input pin name. Replace inst1 with the instance name of the PLL generating the memory clock. See the comments in the SDC file for more information. Start the compilation. Page 20 of 30

21 SDR SDRAM In a single-data rate SDRAM system, a PLL is used to generate the various SDRAM clocks. The first PLL output generates the SDRAM clock and it runs at the maximum SDRAM frequency (depending on the speed grade of the programmable logic and SDRAM device). The capture clock is connected to the second PLL output and it is used to correctly read the high-speed data from the SDRAM device. It runs at the same frequency as the SDRAM clock, but it is shifted in phase. The third PLL output drives the clock off-chip to the SDRAM device. Again this clock runs at the same frequency as the SDRAM clock, but it is phase shifted. Figure 16: SDR Top Level Page 21 of 30

22 Use the MegaWizard Plug-in Manager in Quartus to generate the SDRAM PLL. For the first compile select no phase shift for each PLL output and compensate for the SDRAM clock (c0). After the first compilation, the SDRAM script calculates the required phase shifts automatically. Add the PLL to the top level and start the compilation (don t forget to assign the SDRAM pin locations and I/O standards before starting the compilation). After a successful compilation edit the SDRAM PLL using the MegaWizard and update the phase shift according to the settings found in the Quartus compilation report > Microtronix SDRAM Controller. Recompile the design to apply the new PLL settings and the SDRAM controller is ready to be used. Figure 17: SDR SDRAM PLL Settings Page 22 of 30

23 DDR, DDR2 and Mobile SDRAM In a double-data rate system the SDRAM clocks are generated by a PLL. The first PLL output drives the SDRAM clock and it runs at the maximum SDRAM frequency. The second PLL output is connected to the SDRAM write clock and it runs at the same SDRAM frequency. Use the Altera MegaWizard to generate the SDRAM PLL. The SDRAM clock is not phase shifted and the SDRAM write clock is phase shifted 90 degrees. Add the PLL to the top level and start compilation (don t forget to assign the SDRAM pin locations before starting the compilation). After the first compilation an automatic generated script locates the most critical DDR cells and moves them to fixed locations close to the SDRAM pins. This ensures the maximum performance and best timing. Recompile the design to apply the new DDR locations and the SDRAM controller is ready for use. Figure 18: DDR Top Level Page 23 of 30

24 Timing The SDRAM controller is a fully synchronous design and covers multiple clock domains. All signal crossing from different clock domains are guaranteed by the core design. If the Quartus timings analyzer reports a timing violation between two clock domains, then this path must be flagged as a false timing path. Performance Table 4 shows the maximum performance results for the SDRAM controller. Actual performance may be affected by the system LE count, memory width, FPGA pin assignments and memory device. Table 4: Maximum SDRAM Performance Device Speed Grade (Commercial) System Fmax (MHz) SDR DDR DDR2 Mobile DDR Arria II GX Arria GX Stratix III Stratix II Cyclone V Cyclone IV E -8L L Cyclone IV GX Cyclone III Page 24 of 30

25 Cyclone II Resource Requirements Table 5 shows the typical size in logic elements (LE) for the various SDRAM Controller modules. The actual number of logic elements may vary depending on the device family and Quartus settings. The table shows the minimal M4K RAM blocks usage. If a large buffer size is selected, the number of M4K RAM blocks may increase. Table 5: FPGA Resource Requirements Module LE * M4K RAM Blocks * SDRAM Controller Write Port Read Port *Note: The number of logic element resources depends on the memory architecture, data width and cache settings. The numbers shown in the table are for a 16-bit DDR SDRAM implementation with the default FIFO size. Simulation A precompiled simulation library is provided for performing simulations using ModelSim. The library is located in the <install_dir>/simulation directory. Perform the following steps to simulate your design with the SDRAM memory controller. 1. Launch ModelSim 2. Map the SDRAM memory controller library. At the ModelSim prompt type: VHDL: vmap mtx_streaming_sdram <install_dir>/simulation/mtx_streaming_sdram SystemVerilog: vmap mtx_streaming_sdram <install_dir>/simulation/mtx_streaming_sdram_sv If you use a newer version of ModelSim, you must refresh the precompiled library. At the Modelsim prompt type; VHDL: vcom refresh work mtx_streaming_sdram Page 25 of 30

26 SystemVerilog: vlog sv suppress 2583 refresh work mtx_streaming_sdram 3. Compile the sdram top level. Eg. If the sdram controller was named sdram in the SOPC Builder, then type; VHDL: vcom 93 sdram.vhd SystemVerilog: vlog sv suppress 2583 sdram.sv 4. Compile all of the design files 5. Start the ModelSim simulation by typing; vsim t ps L mtx_streaming_sdram <top_level> Verification The SDRAM controller has been verified on Altera and other FPGA development boards. Table 6 shows the hardware platforms on which the IP core has been tested and the memory devices contained on each board. Table 6: Supported Platforms and Memory Devices Development Board Altera Device SDRAM Device Terasic DE4 EP4SGX230KF40C2 DSL DDR GB CL5 module Altera Arria II GX FPGA Development Board Altera Arria GX Development Kit Altera Stratix III FPGA Development Kit ViClaro III ViClaro II Altera Cyclone III Starter Kit ViClaro FireFly II Sendero Sendero EP2AGX125EF35 EP1AGX60DF780 EP3SL150F1152C2 EP3C128F780C7 EP2C35F484C6 EP3C25F324C8 EP2C20F256C7 EP2C20F484C8 EP2C35F672C6 EP2C35F672C6 Micron MT8HTF12864HZ-800H1 (DDR2) Micron MT47H32M16 (DDR2) Micron MT47H32M8BP-3 (DDR2) Micron MT47H32M16BN-3 (DDR2) Micron MT47H16M16BG-3 (DDR2) PowerChip A2S56D40CTP-G5 (DDR) ISSI IS42S16800B-7TL (SDR) Micron MT48LC8M32B2B5-7 (SDR) ISSI IS43R16160A-6T (DDR) Infineon HYB25D256160CE-5 (DDR) Page 26 of 30

27 Vivien EP2C5T144C6 ISSI IS42S16100C1-6TL (SDR) Page 27 of 30

28 Altera Nios Board Cyclone II Edition Sasco Holz Pablo EP2C35F672C8 EP2C20F484C6 Micron MT46V16M16-6T (DDR) Micron MT46H8M32LFB5-6 (Mobile DDR) Installation Follow these steps to install the Microtronix Streaming Multi-Port SDRAM Controller on your computer. 1. Insert the Microtronix Streaming Multi-Port SDRAM Controller Installation CD into your CD-ROM (or equivalent) 2. The setup program for the package should start. If it doesn t, browse to the CD using Windows Explorer and double-click on the setup icon. 3. Follow all the prompts. License A valid IP core license is required from Microtronix to generate program files incorporating the SDRAM IP core. These licenses are generated based on a NIC or Guard ID supplied by the user. They can be either server or workstation based. After purchasing a license you receive your license file. Copy the license file (license.dat) to your current Quartus license file and the SDRAM controller (CC21_6248) will show in the Quartus License Setup. With the free OpenCore Plus feature the SDRAM controller can be evaluated in real hardware. The OpenCore Plus feature requires an evaluation license from Microtronix. Please contact Microtronix for licensing details. Page 28 of 30

29 FAQ Q. Why does Quartus report the error Error: DQS I/O pin does not feed a Clock Delay Control block? A. For Cyclone II devices the DQS signals must be assigned to the dedicated DQS pins. If the dedicated pins are used, then open the assignment editor and remove the assignment DQS Frequency. Q. Do you have any recommendations for layout of my SDRAM memory board? A. Microtronix does not have specific layout recommendations. Please follow the layout guidelines of your SDRAM manufacturer. For example, Micron s recommendations for DDR/DDR2 design can be found at ox.aspx Q. My DDR / DDR2 SDRAM memory board layout includes external parallel termination resistors. Is this supported? A. During idle the parallel termination resistor pulls the DQ/DQS signal to the VTT voltage level, which is the same level as the VREF voltage. The SSTL input buffer is a comparator and this causes unwanted glitches inside the programmable device. For DDR2 memory architectures using On-Die Termination (ODT) is preferable and this feature gives better SI results than external parallel termination. To support external parallel termination one of the following steps must be applied to the board. 1. In designs using a point-to-point memory architecture (short DQ/DQS traces) and single parallel termination resistors, remove the resistor connected to DQS0. 2. In designs incorporating a more complex memory architecture (longer traces, DIMM sockets) or resistors packages, adjust the VREF voltage by using the voltage divider. Page 29 of 30

30 DDR POWER SUPPLY DDR / R1 = 1.5K DDR2 / R1 = 1.27K VREF R2 = 1K Page 30 of 30