Computer Architecture

Transcription

1 IWKS 3300: NAND to Tetris Spring 2018 John K. Bennett Computer Architecture Foundations of Global Networked Computing: Building a Modern Computer From First Principles This course is based upon the work of Noam Nisan and Shimon Schocken. More information can be found at (

2 A Brief History of Computer Architecture

3 Abacus ( BC; Sumeria) Sexagesimal (base-60) number system

4 Blaise Pascal ( )

5 Jacquard Loom (1801)

6 AVL Jacquard Loom (2016)

7 Atanasoff Berry Computer ( ; vacuum tubes)

8 Zuse Z3 ( ; relays)

9 Eniac ( ; vacuum tubes)

10 Eniac

11 Eniac

12 Eniac

13 Illiac I / OrdVac (1951) Ordnance Discrete Variable Automatic Computer

14 R1- Rice Research Computer (1959)

15 IBM 360 (1964)

16 Hexadecimal Calculator

17 Cray 1 (1975)

18 Cray 1 (1975)

19 Cray 2 (1985)

20 The Xerox Alto, 1973 First personal workstation; first wide deployment of: Bit-map graphics Mouse WYSIWYG editing Hosted the invention of: Local-area networking Laser printing All of modern client / server distributed computing

21 MITS Altair 8800 (1975)

22 Basic on an 8-bit Computer

23 Apple I (1975-6)

24 Apple II (1977)

25 TRS 80 (1977)

26 Apple Lisa (1979)

27 IBM PC (1981)

28 UW Eden Node Machine (1982)

29 IBM PC XT (1983)

30 Apple Macintosh (1984)

31 Sun 1-3 Workstations ( )

32 iphone (2007)

33 Amazon Kindle (2007)

34 ipad (2009)

35 Von Neumann Machine (circa 1940) Memory CPU Arithmetic Logic Unit (ALU) Input device (data + instructions) Registers Control Output device Keyboard John Von Neumann (and others)... made it possible Gordon Moore, Andy Grove (and others)... made it small and fast.

36 Harvard Mark 1 (circa 1940) Howard Aiken

37 Processing logic: fetch-execute cycle Memory CPU Arithmetic Logic Unit (ALU) Input device (data + instructions) Registers Control Output device Executing the current instruction involves one or more of the following tasks: Have the ALU compute some function out = f (register values) Write the ALU output to selected registers As a side-effect of this computation, Keyboard determine what instruction to fetch and execute next.

38 The Hack chip-set and hardware platform Elementary Gates Combinatorial Chips Sequential Chips Computer Architecture Nand Not And done HalfAdder FullAdder Add16 DFF Bit Register Memory CPU Computer Or Xor Inc16 ALU RAM8 RAM64 this lecture Mux Dmux done RAM512 RAM4K Not16 RAM16K And16 PC Or16 Mux16 done Or8Way Mux4Way16 Mux8Way16 DMux4Way DMux8Way

39 The Hack Computer A 16-bit Harvard platform (data and instructions are separate) The instruction memory and the data memory are physically separate Screen: 512 rows by 256 columns, black and white Keyboard: standard (memory-mapped to a specific RAM address) Designed to execute programs written in the Hack machine language Can be easily built from the chip-set that we have built so far in the course Main parts of the Hack computer: Instruction memory (ROM) Memory (RAM): Data memory Screen (memory map) Keyboard (memory map) CPU Computer (the framework that holds everything together).

40 Where We Are Headed inm writem Instruction Memory instruction CPU outm addressm Data Memory (ROM32K) pc (Memory) CHIP Computer { reset IN reset; PARTS: // implementation missing }

41 Instruction Memory address ROM32K out Function: The ROM is pre-loaded with a program written in the Hack machine language The ROM chip always emits a 16-bit number: out = ROM32K[address] This number is interpreted as the current instruction. ROM[2 n ] is implemented using 8 ROM[2 n-3 ] s, an 8:1 multiplexor, and a 1:8 demultiplexor.

42 Data Memory load in 16 RAM16K out 16 address 15 Function: When read, the RAM16K chip always emits a 16-bit value: out = RAM16K[address] A 16 bit value is required to write to the RAM16K chip: RAM16K[address] = in & load & clock RAM[2 n ] is implemented using 4 or 8 RAM[2 n-3 ] s, an 8:1 multiplexor, and a 1:8 demultiplexor.

43 Data Memory Low-level (hardware) read/write logic: load To read RAM[k]: set address to k, probe out To write RAM[k]=x: set address to k, set in to x, set load to 1, run the clock in 16 address RAM16K out 16 High-level (OS) read/write logic: 15 To read RAM[k]: use the OS command out = peek(k) To write RAM[k]=x: use the OS command poke(k,x) peek and poke are OS commands whose implementation should effect the same behavior as the low-level commands More about peek and poke this later in the course, when we write the OS.

44 Screen in load The bit contents of the Screen chip are called the screen memory map 16 address Screen out 16 Simulated screen: 15 Physical Screen The Screen chip emulates basic RAM chip functionality: read logic: out = Screen[address] write logic: if load then Screen[address] = in Side effect: Continuously refreshes a 256 by 512 black-and-white screen device The simulated 256 by 512 B&W screen When loaded into the hardware simulator, the built-in Screen.hdl chip opens up a screen window; the simulator then refreshes this window from the screen memory map several times each second.

45 LogicCircuit Configuration for the Hack Screen The Screen chip emulates basic RAM chip functionality: read logic: out = Screen[address] write logic: if load then Screen[address] = in Side effect: Continuously refreshes a 256 by 512 black-and-white screen device

46 Screen Memory Map (0x4000) In the Hack platform, the row screen is implemented as an 8K 16-bit RAM chip row Screen row refresh several times each second How to set the (row,col) pixel of the screen to black or to white: Low-level (machine language): Set the col%16 bit of the word found at Screen[row*32+col/16] to 1 or to 0 (col/16 is integer division) High-level: Use the OS command drawpixel(row,col) (effects the same operation, discussed later in the course, when we write the OS).

47 Keyboard Keyboard Keyboard out 16 Simulated keyboard: Keyboard chip: a single memory-mapped 16-bit register Input: Output: scan-code (16-bit value) of the currently pressed key, or 0 if no key is pressed same The simulated keyboard enabler button Special keys: Keyboard How to read the keyboard: The keyboard is implemented as a built-in Keyboard.hdl chip. When this java chip is loaded into the simulator, it connects to the regular keyboard and pipes the scan-code of the currently pressed key to the keyboard memory map. Low-level (hardware): probe the contents of the Keyboard chip at RAM location: (0x6000) High-level: use the OS command keypressed() (effects the same operation, discussed later in the course, when we write the OS).

48 LogicCircuit Keyboard Configuration How to read the keyboard: Low-level (hardware): probe the contents of the Keyboard chip at RAM location: (0x6000) High-level: use the OS command keypressed() (effects the same operation, discussed later in the course, when we write the OS).

49 Memory: Programmer s View Memory Data Screen memory map Keyboard map Screen Using the memory: Keyboard To record or recall values (e.g. variables, objects, arrays), use the first 16K words of the memory: (0x0000-3FFF) To write to the screen (or read the screen), use the next 8K words of the memory: (0x4000-5FFF) To read which key is currently pressed, use the next word of the memory: (0x6000).

50 Memory Physical Implementation in 16 Memory 0 load RAM16K (16K mem. chip) out The Memory chip is essentially a package that integrates the three chip-parts RAM16K, Screen, and Keyboard into a single, contiguous address space. This packaging effects the programmer s view of the memory, as well as the necessary I/O side-effects. address Screen (8K mem. chip) Keyboard (one register) 16 Screen Keyboard Access logic: Access to any address from 0 to 16,383 results in accessing the RAM16K chip-part Access to any address from 16,384 to 24,575 results in accessing the Screen chip-part Access to address 24,576 results in accessing the keyboard chip-part Access to any other address is invalid.

51 LogicCircuit Configuration of the Hack Instruction Memory Access logic: Access to any address from 0 to 16,383 results in accessing the RAM16K chip-part Access to any address from 16,384 to 24,575 results in accessing the Screen chip-part Access to address 24,576 results in accessing the keyboard chip-part Access to any other address is invalid.

52 LogicCircuit Configuration of the Hack Data Memory. Access logic: Access to any address from 0 to 16,383 results in accessing the RAM16K chip-part Access to any address from 16,384 to 24,575 results in accessing the Screen chip-part Access to address 24,576 results in accessing the keyboard chip-part Access to any other address is invalid.

53 CPU Operation from data memory from instruction memory a Hack machine language instruction like M=D+M, represented as a 16-bit value inm instruction reset 16 outm 16 1 CPU writem addressm pc to data memory to instruction memory CPU internal components (invisible in this chip diagram): ALU and 3 registers: A, D & PC CPU execute logic: The CPU executes the instruction according to the Hack language specification: The D and A values, if they appear in the instruction, are read from (or written to) the respective CPU-resident registers The M value, if there is one in the instruction operand, is read from inm If the instruction s result includes M, then the ALU output is placed in outm, the value of the CPU-resident A register is placed in addressm, and writem is asserted.

54 CPU Operation from data memory from instruction memory a Hack machine language instruction like M=D+M, represented as a 16-bit value inm instruction reset 16 outm 16 1 CPU writem addressm pc to data memory to instruction memory CPU internal components (invisible in this chip diagram): ALU and 3 registers: A, D, PC CPU fetch logic: Recall that: 1. the instruction may include a jump directive (if the jump bits are non-zero) 2. the ALU emits two control bits, indicating if the ALU output is zero or less than zero If reset==0: the CPU uses this information (the jump bits and the ALU control bits) as follows: If there should be a jump, the PC is set to the value of A; else, PC is set to PC+1 If reset==1: the PC is set to 0. (thus restarting the computer)

55 The C-instruction Revisited dest = comp; jump comp dest jump binary: a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3

56 CPU Implementation Mux Mux ALU CPU Schematic: Includes most of the CPU s execution logic The CPU s control logic is hinted: each circled c represents one or more control bits, taken from the instruction The decode bar does not represent a chip, but rather indicates that the instruction bits are decoded (somehow). instruction inm reset dest = comp; jump comp dest jump binary: a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 ALU output C C C decode C C A D A M A C D A/M C C C outm writem addressm A PC pc Cycle: Execute logic: Fetch logic: Resetting the computer: Execute Fetch Decode Execute If there should be a jump, set PC to A else set PC to PC+1 Set reset to 1, then set it to 0.

57 CPU Implementation Issue #1: How to interpret instructions like A=A+1;JMP or A=M;JMP? Mux Mux ALU The CPU as diagrammed in the book uses the initial value of the A-register for the jump address, which is perhaps counterintuitive. dest = comp; jump comp dest jump binary: a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 ALU output An alternative implementation would use the new value of A or M to load A. C decode C C C D D C outm One could implement this alternative by adding a multiplexor that selects the A-register input value for the jump address during instructions that change the A-register. instruction inm reset A x A M A A C PC A/M C C C writem addressm pc HDL Implementation of this alternative: c // If A is changing, use its new value for the target address Mux16 (sel=loada, a=areg, b=ain, out=jmpaddr); PC (in=jmpaddr, reset=reset, inc=true, load=jmp, out[0..14]=pc);

58 CPU Implementation Issue #2: How to handle potential instruction execution asynchrony? Mux Mux ALU The CPU as diagrammed in the book glosses over the order in which the A, D, and PC registers, and memory, change. dest = comp; jump comp dest jump binary: a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 An as-described implementation of the Hack architecture using a simulator (or hardware) that notices this asynchrony can create problems, e.g., if the PC changes as the result of a jump before the instruction has completely finished executing. instruction One way to address this issue would be to add an instruction register that would remain stable throughout the instruction execution cycle. inm reset C decode C C Instruction Register A ALU output A M A A C D C PC D A/M C C C C outm writem addressm pc

59 Computer Interface reset Computer Screen Keyboard Keyboard

60 Computer Implementation inm writem Instruction Memory instruction CPU outm addressm Data Memory (ROM32K) pc (Memory) CHIP Computer { IN reset; PARTS: // implementation missing } reset Implementation: Simple, the chip-parts do all the work.

61 LogicCircuit Implementation of the Hack Computer

62 Perspective: What We Have Left Out Caching Instruction pipelining More I/O units Special-purpose processors (I/O, graphics, communications, ) Multi-core / parallelism Efficiency considerations Energy consumption considerations And a bunch of other stuff (take a good computer architecture course!)