Computer Architecture

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Lester Butler
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org Elements of omputing Systems, Nisan & Schocken,

1 omputer Architecture Building a Modern omputer From First Principles Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 1

John Von Neumann (and others)... made it possible Andy Grove (and others).

2 Von Neumann machine (circa 1940) Memory PU Arithmetic Logic Unit (ALU) Input device (data + instructions) Registers ontrol Output device Stored program concept! John Von Neumann (and others)... made it possible Andy Grove (and others)... made it small and fast. Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 2

3 Processing logic: the instruction cycle Memory PU Arithmetic Logic Unit (ALU) Input device (data + instructions) Registers ontrol Output device Executing the current instruction involves one or more of the following micro-tasks: Fetch the next instruction Decode the instruction Read source operands Perform ALU operation Store the result Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 3

4 The Hack computer A 16-bit Von Neumann platform The instruction memory and the data memory are physically separate Screen: 512 columns by 256 rows, black and white Keyboard: standard Designed to execute programs written in the Hack machine language an be easily built from the chip-set that we built so far in the course Main parts of the Hack computer: Instruction memory (ROM) Memory (RAM): Data memory Screen (memory map) Keyboard (memory map) PU omputer (the logic that holds everything together). Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 4

5 Memory: conceptual / programmer s view Memory Data Screen memory map Keyboard map Screen Keyboard Using the memory: To record or recall values (e.g. variables, objects, arrays), use the first 16K words of the memory To write to the screen (or read the screen), use the next 8K words of the memory To read which key is currently pressed, use the next word of the memory. Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 5

6 Memory: physical implementation in 16 Memory 0 load RAM16K (16K mem. chip) out The Memory chip is essentially a package that integrates the three chipparts RAM16K, Screen, and Keyboard into a single, contiguous address space. This packaging effects the programmer s view of the memory, as well as the necessary I/O side-effects. address Screen (8K mem. chip) Keyboard (one register) 16 Screen Keyboard Access logic: Access to any address from 0 to 16,383 results in accessing the RAM16K chip-part Access to any address from 16,384 to 24,575 results in accessing the Screen chip-part Access to address 24,576 results in accessing the keyboard chip-part Access to any other address is invalid. Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 6

7 PU from data memory from instruction memory a Hack machine language instruction like M=D+M, stated as a 16-bit value inm instruction reset 16 outm 16 1 PU writem addressm pc to data memory to instruction memory PU internal components (invisible in this chip diagram): ALU and 3 registers: A, D, P PU fetch logic: Recall that: 1. the instruction may include a jump directive (expressed as non-zero jump bits) 2.the ALU emits two control bits, indicating if the ALU output is zero or less than zero If reset==0: the PU uses this information (the jump bits and the ALU control bits) as follows: If there should be a jump, the P is set to the value of A; else, P is set to P+1 If reset==1: the P is set to 0. (restarting the computer) Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 7

8 The -instruction revisited dest = comp; jump comp dest jump binary: a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 8

9 PU implementation dest = comp; jump comp dest jump hip diagram: Includes most of the PU s execution logic The PU s control logic is hinted: each circled c represents one or more control bits, taken from the instruction The decode bar does not represent a chip, but rather indicates that the instruction bits are decoded somehow. instruction inm reset binary: decode a c1 c2 c3 c4 c5 c6 d1 d2 d3 j1 j2 j3 Mux ALU output A A M D D outm Mux A/M ALU A addressm writem A P pc ycle: Execute logic: Fetch logic: Resetting the computer: Execute Fetch Decode Execute If there should be a jump, set P to A else set P to P+1 Set reset to 1, then set it to 0. Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 9

10 Perspective: from here to a real computer Pipelining aching More I/O units Special-purpose processors (I/O, graphics, communications, ) Multi-core / parallelism; GPUs Efficiency Energy consumption considerations And more... Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 10

11 Perspective: some issues we haven t discussed (among many) IS / RIS (hardware / software trade-off) Hardware diversity: desktop, laptop, mobile, game machines, General-purpose vs. embedded computers Elements of omputing Systems, Nisan & Schocken, MIT Press, hapter 5: omputer Architecture slide 11

EP1200 Introduction to Computing Systems Engineering. Computer Architecture

EP1200 Introduction to Computing Systems Engineering. Computer Architecture EP1200 Introduction to omputing Systems Engineering omputer Architecture Perspective on Machine and Assembly Languages Hack is a simple machine language Designed for the simple Hack computer architecture