Jacinto 6 Entry Low-Cost Infotainment Head Unit System Reference Design Overview

Transcription

1 Jacinto 6 Entry Low-Cost Infotainment Head Unit System Reference Design Overview TIDEP-0097 Reference Design Overview ( ) Thomas Shelburne Digital Field Applications (MGTS, System) Todd Toporski Analog Field Applications (SMTS, Power and Analog) Bill McCracken Auto Processor Hardware Applications (MGTS, PCB Design) 1

2 Detailed agenda System Design Goals / Challenges (Thomas Shelburne, 10 minutes) System Solution Overview (Thomas Shelburne, 15 minutes) System Power and Signal Chain Overview (Todd Toporski, 25 minutes) Low Cost PCB Design (Bill McCracken, 25 minutes) Questions, Reference Design Documentation, and Videos (15 minutes) 2

3 Systems Design Challenges and Goals (1) Problem Statement: TI had performed very well securing mid/high end infotainment system designs with Jacinto6 / Jacinto6-Eco family devices (DRA74x / DRA72x) with many OEM / Tier-1 customers. TI had been much less successful at winning traditional low cost infotainment system designs using Jacinto6- Eco (DRA72x) devices for many reasons. The availability of a more cost competitive Jacinto6-Entry (DRA71X) device family in 2H2016 solved some but not all of the cost issues in these systems. 3

4 Systems Design Challenges and Goals (2) Problem Statement: TI needed to create a low cost infotainment reference design integrating state of the art cost saving and feature integration techniques to demonstrate our best in class low cost infotainment system solutions. We also needed to demonstrate the unique advantage TI has in offering complete system solutions to customers including automotive grade power, analog, wired/wireless connectivity, signal chain, and even third party building blocks. 4

5 Systems Design Challenges and Goals (1) Compiled Key System Goals and Requirements: Demonstrate lower cost 6 layer PCB design guidelines for J6-Entry (vs. 8 layer design guidelines previously) on a typical 16cm x 16cm form factor board. Develop an automotive start/stop power supply and complete system power solution. Demonstrate third party AM/FM tuner and DSP based Software Defined Radio integration for single/dual tuner HD/DAB/DRM radio use cases. Demonstrate DSP based digital rear view camera integration with LDC processing. Demonstrate method for SW based EMC / EMI control and AM/FM avoidance using clock synchronization of power supply and other switching components. 5

6 Systems Design Challenges and Goals (2) Compiled Key System Goals and Requirements: Demonstrate a 4 channel small form factor Class-D Amplifier (both digital input TAS6424 and analog input TPA6404 solutions). Show wired/wireless connectivity and GPS / GNSS / Gallileo / BeiDei satellite navigation. Show optional wake-up MCU integration with CAN / LIN support. Support expansion of audio channel inputs/outputs as well evaluation of A2B technology. Support Rear View Camera redundancy without using Intersil Techwell devices. 6

7 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 7

8 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 8

9 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 9

10 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 10

11 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 11

12 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 12

13 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 13

14 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 14

15 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 15

16 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 16

17 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 17

18 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 18

19 Jacinto6 Entry low-cost infotainment head unit Stop-Start Front End Power Supply Synchronous HDMI Output & Level Translation / Protection USB-SS / USB-HS & Charging/Protect IVI SoC AM57xx / J6-Entry TAS6424/ TPA W x 4Channel Class D Tuners Tuner + Codec Wake MCU A2B / Audio Expansion BT / WiFi / GPS / GNSS WL1873 ublox Gen 8 GPS/GNSS/Gallileo/BeiDei FPD-Link Out (IVI / DM) DS90UB921 FPD-Link In (Digital RVC) DS90UB934 Ethernet AVB / CAN / LIN 19

20 Jacinto6 Entry System Block Diagram

21 System Power & Signal Chain 22

22 Input Power Protection & Filtering

23 Main System Power Architecture

24 Power for Jacinto6 Entry

25 J6/PMIC PDN Diagram

26 USB Power & Charging

27 Tuner Power Supplies

28 Power Requirements, Estimates

29 Budget for Standby Iq

30 Power Sequencing, Enable Mapping

31 Power Measurements & Analysis A full test report of system power devices was performed by PDS (J. Mandelcorn), and details are found in: J6_Entry_Low_Cost_Ref_Des_Power_Test_Report2.doc * Ask your local AFA or TSR to obtain report from PDS.

32 Class D Audio Amp: 4 x 25W, 4-Ohm speakers

33 FPD Link - Display

34 FPD Link Rear View Camera

35 Low-Cost PCB Design 36

36 PCB design parameters Defining PCB design parameters begins with understanding: End product features, uses, environment, and lifetime goals PCB performance, manufacturing, and yield concerns IPC-2221 Generic Standard on Printed Board Design which defines how to establish design principles and recommendations for producing PCB designs across three (3) end product classifications and three (3) levels of PCB produce ability. Customers must select final PCB design parameters that meet: End product form, fit, and functional needs while meeting reliability targets PCB routing requirements and fabrication costs: Layer count, via type and size, trace width and space, number of interface signals, controlled impedance stack-up and routing, signal and power integrity Key PCB parameters to define for each PCB design: PCB stack-up and routing plan Controlled impedance plan SoC breakout scheme Cost target 37

37 PCB design parameters Recommendations for TI New Fine-Pitch (nfbga) packages documented: Application Report nfbga Packaging (SPRAA99B-March2008-Revised November 2015) Key SoC breakout scheme item: BGA s Package Ball Via [a.k.a., Solder Mask Opening (SMO)] diameter vs PCB land diameter Pkg SMO to PCB Land Dia Aspect Ratio (AR) recommendation = 1:1 Optimal solder joint reliability over thermal cycling Best robustness under mechanical stresses 38

38 BGA vs VCA package types Package design seeks to maximize balls for supported features while minimizing total cost of an electronic system (die, package, PCB, and components). Removing balls from a full Ball Grid Array (BGA) pattern creates a Via Channel Array (VCA). VCA packages and footprints: Enable routing channels to escape innermost BGA positions. Reduce number of routing layers for 100% signal breakout. Minimize package outline dimensions by using smaller ball pitch. Allow larger breakout via land and drill diameters: Lowers PCB manufacturing costs Improves PCB reliability performance Improve power integrity of power and ground plane layers: Lower impedance vs frequency response that minimizes transient switching noise Maintain current density/carrying capacity to innermost BGA positions 39

39 J6Entry Info PCB design PCB design breakout scheme: Pkg SMO to PCB Land diameters, aspect ratio = / 0.300, 1:0.86 Same BLR performance as AR = 1:1 after 1600 temp cycles IPC Class 2 16/8 Breakout Via Via Pad/Land diameter = 0.457mm / 16mil Via Drill diameter = 0.203mm / 8mil Allows 90 Partial Via Breakout Via drill edge can extend beyond via land edge by ~1.2mil Only a few drill holes affected by max PCB manufacturing tolerance build-up Center Location Optimally places 16mil via land within SoC footprint Improves PCB power and ground routing, which improves power integrity Z vs F performance by 20MHz Removes Via fill process step, which reduces PCB costs by 9-18% 40

40 16/8 Center Via Placement breakout scheme 41

41 J6Entry Info: PCB design rules, IPC Class 2 Items Values [mm] (mil = 1/1000inch) BGA Ball Pitch (25.6) BGA SMO to PCB Land Dia, Aspect Ratio 0.350/0.300 (11.8), 1:0.86 BGA Pad to Solder Mask Clearance, min (2.0) Trace/Line Width, min (4.0) Space, Conductor to Conductor (different net),min (Conductor = any Cu surface, i.e. Trace, Pad, Via, Plane ) (4.0) Space, Conductor to Via Drill Edge, min (9.0) Via, Plated Through-Hole (PTH) Drill dia, min (8.0) Via, PTH Land dia, min (16.0) Via, PTH Anti-Pad (Plane Clearance) dia, min (38.0) Via, PTH Annular Ring Width, typ (4.0) Via, PTH Hole Hole Pitch, min (22.0) PCB Thickness, Aspect Ratio = Thickness/Via dia (Volume PCB production desires max AR = 8:1) 1.58 (62.0), 7.75

42 J6Entry VCA Pattern (17x17, 0.65mm, 538 Ball, VCA) Bottom-View Ball Map Summary Pkg Outline = 17x17mm BGA Pitch = 0.65mm BGA Grid (25x25) = 625 Ball Voids for VCA = 87 Total Balls =

43 J6Entry Info RevB: Breakout (17x17, 0.65mm, 538 Ball, VCA) PCB Layer = Top BGA Ball Summary Signal Balls = 325 Power Balls = 122 Gnd Balls = 88 No Connects = 3 Total Balls 538 Power & GND Ball/Net Legend: GND VDD_CORE_AVS VDD_DSP_AVS VDD_DDR_1V35 VDDR_VREFSTL VDDS_1V8 VIO_3V3 VDA_xxx VDA_SDIO_DV VCAP_VDDRAM_xxx Signal Breakout Vias - 16/8 (Land/Drill dias [mil]) BGA Land Pad 44

44 J6Entry VCA: Deeper breakout in less layers PCB Layer 3 Signal #2 VCA concentrates breakout vias to be into specific areas allowing routing channels. Routing channels provide easy access to signal balls located in deeper into the SoC footprint. End result is less PCB signal layers needed to breakout all signal balls vs a full BGA footprint. 45

45 Min Via Land Size Visual Models 46

46 PCB technology vs cost impacts Key Items Min Trace Width & Conductor Space (Cu weight dependent) Max Aspect Ratio (PCB thickness / Drill dia) dependent upon Drill size, for 8mil Standard PCB Tech [mm] (mil) (4.0) Min Via, Mechanical/Through-Hole Drill Dia (8.0) for AR 8:1 Min, Blind Via Mechanical (may add Lam Cycle) Min, Blind Via Laser Drilled μ-vias Sequential Lamination Via Fill, Non-Conductive (could be used with Via-In-Pad) Advanced PCB Tech [mm] (mil) (3.0) < 3mil Approximate Cost Increase # NOTE: * Dependent upon PCB size, layer count & count per panel x 1.5x 8:1 > 8:1 1.2x NA (5mil offset, single Lam Cycle) NA (6.0) plus AR 10: (6.0) (4.0), Cu filled µvia Additional Lamination Cycles 1.2x (drill cost) 1.2x (AR cost) 1.5x (per Lam Cycle) x* 1.5x (per Lam Cycle) NA 10mil (preferred min drill) x* Via Fill, Conductive NA Not Recommended Embedded Capacitance 2mil core BC2000 TM, HK-04, FaradFlex TM x* Embedded Resistance NA Ohmega ply, Ticer 2 3x*

47 TI Reference Design links and videos TIDEP-0097 Reference Design: Reference Design User Guide Schematics (CPU board and display board) BOM (Bill of Materials) PCB Design Files FAE Summit Presentations FAE Summit Presentation Video Recordings System Overview and QNX Demo Video: QNX Demos Jacinto Power Estimates, Schematic/PCB Review, and PDN Analysis Requests: Jacinto6-Entry Reference Design on CDDS:

48 BACKUP 49

49 J6Entry Reference Design System Specifications Capable of running any Automotive OS (QNX, Linux, or Android) Features planned Jacinto6-Entry platform can support Primary FPDLink Display 10.1 (1280x800) WXGA60fps QNX Car Infotainment UI Secondary HDMI Display emulating 720p60 Instrument Cluster Crank or QNX instrument cluster 60fps render rate supported Full automotive Stop/Start Power Supply that operates continuously at 5-6 volts TAS6424/TPA6404 Class-D Amplifier (4 channels) with working audio WiLink8 Bluetooth Audio and Phonebook Access operational 2D/3D Navigation Voice Recognition for Media/Navigation Up to 3 USB ports accessible Apple Car Play and Google Automotive Link Support FPDLink 913/934 Digital Rear Camera in < 2 seconds (Omnivision) Integration of tuners for basic AM/FM/HD/DAB/DRM digital radio Integration of WiLink8 dual band WiFi and GPS-GNSS Prepare for full LCPD support for Linux/Android SDK s Additional DSP features: Audio Post-Processing/ANC-EOC, RVC LDC/Redundancy (remove Intersil Techwell devices for cost savings), and SDR running concurrently. Add HS support and boot/runtime security Up to 6310 DMIPs: 1.5GHz ARM Cortex-A15 Performance + 4x 212 MHz Cortex M4 s Up to 750MHz C66x DSP performance (for multiple digital radio + audio + camera concurrencies) SGX544-MP1 GPU performance of up to 13.5 GFLOPs 50

50 TI Information Selective Disclosure