QorIQ P4080 Software Development Kit
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1 July 2009 QorIQ P4080 Software Development Kit Kelly Johnson Applications Engineering service names are the property of their respective owners. Freescale Semiconductor, Inc
2 QorIQ P4080 Software Development Kit The Software Bundle Hypervisor w/ partition manager U-Boot Linux kernel BMan, QMan, FMan, SEC, PME, SRIO, PCIE drivers Linux applications Standard Open Source Applications FSL Specific Applications Frame Manager Config Tool PME Config Tool Light Weight Executive (LWE) LWE applications LTIB build system GNU tool chain Simulator Functional model - Virtutech Performance model Analysis & visualization Hybrid API CodeWarrior PA10 Multicore debugger Multicore trace and performance analysis tools CodeWarrior Run-Control and Trace Probe service names are the property of their respective owners. Freescale Semiconductor, Inc
3 QorIQ P4080 Software Development Kit (SDK) SDK is delivered in a Linux Target Image Builder Framework (LTIB) LTIB is a tools framework Common to all PowerQUICC and QorIQ development systems Manages, configures, extends and builds Linux software elements Installs P4080 development tools, including GNU tool suite service names are the property of their respective owners. Freescale Semiconductor, Inc
4 QorIQ P4080 Multicore Programming Paradigm Support a variety of customer use-cases Multiple operating systems utilized across cores on a single Proprietary, 3 rd party and Open Source multicore operating systems Symmetric Multi-Processing (SMP) and Asymmetric Multi-Processing (AMP), often running concurrently Often bare-metal, or engineered light-os, used on forwarding/data plane cores Freescale has developed a reference development platform: Freescale Embedded Hypervisor Freescale boot standards, including u-boot Leverage open boot protocol and API standards (e.g. Power.org ) Freescale Light Weight Executive (LWE) for run to completion data plane processing Demonstrate performance and provide reference example for customers Services Forwarding/ Data Plane Control Plane Linux Linux Light Weight Executive (Light RTOS) 3 rd Party AMP AMP SMP L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache L2 Cache Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core Power Architecture Core D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache service names are the property of their respective owners. Freescale Semiconductor, Inc
5 Control Plane cores Linux User Space Data Plane cores LWE Reference Apps Linux Kernel Linux Networking Drivers Light Weight Executive FMan Driver BMan/QMan Driver Hypervisor Bootloader (u-boot) FMan MAC/Port Library Platform trust (secure boot) Execution targets (boards, simulators) Tools Software CodeWarrior GNU Tools service names are the property of their respective owners. Freescale Semiconductor, Inc
6 Freescale Embedded Hypervisor service names are the property of their respective owners. Freescale Semiconductor, Inc
7 Freescale Embedded Hypervisor A small hypervisor for embedded systems, featuring : Static partitioning of hardware resources into logical partitions CPUs Memory IO s Partitions protection and isolation MMU PAMU Sharing Virtualization Configuration is fixed until a reconfigure and system reboot, relying on the approach defined in the Power.org epapr specification. service names are the property of their respective owners. Freescale Semiconductor, Inc
8 guest operating system Hypervisor Interfaces instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
9 Hypervisor Interfaces : Boot Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
10 Hypervisor Interfaces : Boot Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) Boot runtime Specified by the Power.org epapr standard which describes: entry point conditions gdb stub boot Hypervisor # of CPU cores Memory (amount and location) Devices console (including virtual s) vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
11 Hypervisor Interfaces : Virtual CPU guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
12 Hypervisor Interfaces : Virtual CPU guest operating system instruction emulation hypercalls direct I/O Virtual virtual CPU core runtime 100% compatible with e500mc core (e500vcpu) (minus the hypervisor extensions) supervisor mode software runs unchanged Very similar to an e500v2. Hypervisor Key areas: MMU management Privileged SPRs gdb stub console boot vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
13 Hypervisor Interfaces : Runtime Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
14 Hypervisor Interfaces : Runtime Services guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) gdb stub Runtime runtime via hypercalls : a special version of the sc instruction (LEVEL=1) Key areas: Interrupt controller Hypervisor hardware boot vterm (character I/O console, debug) Partition management Other shared console platform resources vterm(gpio, timers, perfmon,etc) service names are the property of their respective owners. Freescale Semiconductor, Inc
15 Hypervisor Interfaces : gdb stub guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
16 Hypervisor Interfaces : gdb stub guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime gdb stub provides interface to debug guest operating systems uses e500mc core debug resources Hypervisor provides run control and access to virtual CPU state uses gdb standard stub gdb interface console protocol boot vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
17 Hypervisor Interfaces : Debug Console guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
18 Hypervisor Interfaces : Debug Console guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot gdb stub Hypervisor Debug console Simple command line for console status of hypervisor vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
19 Hypervisor Interfaces : vterm guest operating system instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot Hypervisor gdb stub console vterm hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
20 guest operating system Hypervisor Interfaces : vterm instruction emulation hypercalls direct I/O virtual core (e500vcpu) runtime boot gdb stub Hypervisor vterm Output for byte channels Allows debug consoles for each vterm partition hardware service names are the property of their respective owners. Freescale Semiconductor, Inc
21 Linux Kernel and Linux Drivers Linux kernel (Beta 1.1) supports both SMP and non-smp same kernel binary images can run with and without hypervisor Linux Ethernet driver that makes use of Frame Manager, Buffer Manager and Queue Manager Frame Manager Driver Buffer Manager/Queue Manager driver SEC 4.0 Driver Support for 10G Ethernet ports Support for Frame Manager Configuration Tool service names are the property of their respective owners. Freescale Semiconductor, Inc
22 Light Weight Executive service names are the property of their respective owners. Freescale Semiconductor, Inc
23 Light Weight Executive Concept Set of C-libraries needed to support data plane applications (C++ planned) Run-to-completion software model Processes do not pre-empt each other - the process must run to completion before other processes get a chance to run, as scheduled by the QMan (= implicit work scheduler) IRQs are supported, software responsibility to postpone actual processing using SWI or implement proper protection/sharing mechanism Dependency on Hypervisor Device Trees for LWE configuration Runs in supervisor state Hypercalls used to access Hypervisor functionality Ingress Channel Egress Channel FQ FQ FQ FQ priority FQ Function FQ FQ FQ FQ priority service names are the property of their respective owners. Freescale Semiconductor, Inc
24 Light Weight Executive Scope Application (Hello World, Simple queuing, Bridging, IP and IPSec forwarding) SWI std func Net/ Frame PME SEC IPC Hypervisor Timer Perf. mon FDT read BMan portal Driver QMan Portal driver libc e500mc core DPAA portals service names are the property of their respective owners. Freescale Semiconductor, Inc
25 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux LWE LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
26 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux stopped App LWE App LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
27 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux stopped App LWE stopped App App LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
28 LWE Hypervisor interaction Boot partman tool for partition start / stop / reset and image download Device address passing Access control MMU and PAMU (peripheral access control) Runtime Peripheral virtualization (e.g. UART, MPIC, GPIO) partition partition partition running App App Linux running App LWE running App App LWE Hypervisor Multicore System Hardware Shared Cache I/O Interrupt Controller CPU CPU CPU CPU Memory Memory Memory I/O I/O I/O I/O Memory service names are the property of their respective owners. Freescale Semiconductor, Inc
29 QorIQ P4080 Simics Hybrid Virtual Platform service names are the property of their respective owners. Freescale Semiconductor, Inc
30 Simulation Terminology Primer: A Functional Model A functional model presents an architecturally correct view of the core and system to executing software A functional model is instruction accurate and contains an instruction set simulator (ISS) plus models of all system s A functional model contains no timing or cycle-accurate behaviors CPU0 Memory Map CPUn Memory A functional model can consume application binaries I/O, DMA Data Path Typical speed of a functional model is in the hundreds of millions of instructions per second Network service names are the property of their respective owners. Freescale Semiconductor, Inc
31 Simulation Terminology Primer: A Performance Model A performance model is a model that simulates the exact functionality and performance of a hardware CPU0 Exe Units/BIU CPU0 Exe Units/BIU Performance models are referred to as cycle-accurate or timing models Performance models typically consume application binaries or traces Coherency Module DDRC0 DDRC1 Depending on level of detail and complexity of model part, simulator speed can be between hundreds to hundreds of thousands of instructions per second I/O, DMA Network Data Path Acceleration service names are the property of their respective owners. Freescale Semiconductor, Inc
32 Performance vs. Functional Model Differences Performance model models coherency Out of order execution and speculative misbehavior can be caught Performance issues related to locks and semaphores can be identified and fixed Performance model models caches and cache operations L1 instruction and data, backside L2, and platform (L3) Models cache locking, flushing, and stashing Performance Model provides increased accuracy with respect to deadlocks and race conditions Asynchronous clock domains are modeled bringing controlled and reproducible indeterminism to an application service names are the property of their respective owners. Freescale Semiconductor, Inc
33 Simics P4080 Hybrid Model Definition A hybrid model is a simulator that combines both a functional model with a performance model within the same environment. Users switch from the functional model to the performance model to analyze specific areas of interest in the application lifetime: Workload Phase Functional data for debug Init Boot Warm-up Steady-state Problem Area Functional Model Performance Model CP CP t 0 Performance data for debug t n service names are the property of their respective owners. Freescale Semiconductor, Inc
34 Timing + Function P4080 Modeling Scope Function Only Not modeled Power Architecture 128KB e500-mc Core Backside L2 Cache 32KB 32KB D-Cache I-Cache 1024KB Frontside L3 Cache 1024KB Frontside L3 Cache 64-bit DDR-2 / 3 Memory Controller 64-bit DDR-2 / 3 Memory Controller eopenpic Pre Boot Loader Security Monitor Internal BootROM PAMU CoreNet Coherency Fabric PAMU PAMU PAMU PAMU Peripheral Access Mgmt Unit Power Mgmt SD/MMC SPI 2x DUART 4x I 2C 2x USB 2.0/ULPI elbc Test Port/ SAP Security 4.0 Pattern Match Engine 2.0 Queue Mgr. Buffer Mgr. Frame Manager Frame Manager RapidIO Message Unit (RMU) 2x DMA PCIe PCIe SRIO PCIe SRIO Real Time Debug Watchpoint Cross Trigger Perf CoreNet Monitor Trace Aurora Clocks/Reset GPIO CCSR 18-Lane 5GHz SERDES service names are the property of their respective owners. Freescale Semiconductor, Inc
35 CodeWarrior service names are the property of their respective owners. Freescale Semiconductor, Inc
36 QorIQ P4080 Dedicated Debug Logic Using Nexus QorIQ 4080 Processor Power Architecture 128 KB e500-mc Core Backside L2 Cache 32 KB 32 KB D-Cache I-Cache 1024 KB Frontside L3 Cache 1024 KB Frontside L3 Cache 64-bit DDR-2 / 3 Memory Controller 64-bit DDR-2 / 3 Memory Controller eopenpic PreBoot Loader Security Monitor Internal BootROM CoreNet Coherency Fabric PAMU PAMU PAMU PAMU PAMU Peripheral Access Mgmt Unit Power Mgmt SD/MMC SPI elbiu Security 4.0 Queue Mgr. Frame Manager Parse, Classify, Distribute Frame Manager Parse, Classify, Distribute SRIO Message Unit DMA Real Time Debug Watchpoint Cross Trigger DUART 2x I 2C 2x USB 2.0/ULPI Test Port/ SAP Pattern Match Engine 2.0 Buffer Mgr. 10GE Buffer 1GE 1GE 1GE 1GE 10GE Buffer 1GE 1GE 1GE 1GE PCIe PCIe SRIO PCIe srio Perf CoreNet Monitor Trace Aurora Clocks/Reset GPIO CCSR 18-Lane 5 GHz SerDes service names are the property of their respective owners. Freescale Semiconductor, Inc
37 QorIQ P4080 / P4040 Debug Architecture Overview Instruction Debug Jamming Instruction Registers Debug Jamming Instruction Registers Debug MBIST Jamming Instruction Monitor Registers Debug MBIST Jamming Monitor Registers MBIST CPU Monitor Nexus MBIST CPU Monitor Nexus CPU Nexus CPU Nexus SkyBlue Interface SkyBlue Interface SkyBlue Interface SkyBlue Interface Events SBX Event Processing Unit (EPU) Select Unit OCEAN Debug Interface (OCDI) Sequence Unit Perfmon Counters Action Unit DDR Debug Interface (DDDI) Triggers JTAG S A P CoreNet Coherency Manager (CCM) NXC T A P Data Path (QM/FM) CoreNet Trace (CNDC) DataPath Trace (DPDC) NTC Nexus Port Controller (NPC) Control/ Arbitration NTC 16K Trace Buffer Aurora Interface Aurora Link Layer (NAL) HBDP (SerDeS) Run control is performed via Aurora or JTAG Nexus Port Controller (NPC) manages trace buffer and Nexus trace port Event Processing Unit (EPU) monitors events and generates cross-triggers CoreNet Debug Client, DataPath Debug Client, DDR Client monitor peripherals and memory service names are the property of their respective owners. Freescale Semiconductor, Inc
38 CodeWarrior : Core-based Software Performance Analysis Trace-Based Performance Monitors real time capture and presentation of core function profile service names are the property of their respective owners. Freescale Semiconductor, Inc
39 Example: CodeWarrior DDR Profiling & Performance Analysis service names are the property of their respective owners. Freescale Semiconductor, Inc
40 Q&A Thank you for attending this presentation. We ll now take a few moments for the audience s questions and then we ll begin the question and answer session. service names are the property of their respective owners. Freescale Semiconductor, Inc
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