QorIQ P4080 Processor Pre-Boot Loader Image Tool

Transcription

1 June 23, 2010 QorIQ P4080 Processor Pre-Boot Loader Image Tool FTF-NET-F0402 Kelley Oswalt Applications Engineer

2 Objective Introduce the PBL Image Tool and describe it s features and use in assisting the user in creating a complete PBL Image for the P4080 device. 2

3 Agenda 1. P4080 introduction 2. Introduction to PBL interface 3. Pre-boot Initialization (PBI) 4. PBL Image 5. Overview of PBL tool capability 6. Details about the Tools tab Encode PBL image Decode PBL image Calculate clock frequencies and data rates 7. Details on PBI tab How to load a binary image via PBI commands 8. Examples 3

4 Introduction Why does the P4080 implement a Reset Configuration Word (RCW)? The P4080 requires a significant amount of power-on-reset (POR) configuration (over 60 parameters) for proper operation. This would require more than 200 configuration pins. Instead, the P4080 reads the PBL image, which includes the RCW, from an external memory device. The pre-boot loader (PBL) image is the memory-based configuration data that includes both the RCW and PBI commands. The browser-based PBL image tool helps the user create a complete PBL image for use with a P4080 device. 4

5 QorIQ P4080 5

6 Reset Configuration Pins RCW source location cfg_rcw_src[0:4] General purpose input Cfg_gpinput[0:15] elbc FCM ECC control Cfg_elbc_ecc DRAM type select Cfg_dram_type 6

7 The pre-boot loader (PBL): Introduction: P4080 Pre-Boot Loader (PBL) Performs configuration register read and write to initialize the I2C, elbc FCM (NAND Flash), esdhc, or SPI interface chosen by RCW source config pins Loads PBL image from chosen source Loads RCW from external memory device waits for PLLs to lock Loads pre-boot initialization (PBI) commands optional PBL block diagram showing interface command modules 7

8 What is purpose of the PBI? PBI Commands Allows configuration of various interfaces before allowing the cores to boot Similar to bootsequencer on previous devices Write to CCSR space (ACS = 0) Write to alternative space such DDR or CPC SRAM (ACS = 1) Commands Flush Ensure previous write has taken effect CRC Check performs CRC check on all data since last CRC check Jump provide next address to jump to Wait - can t poll registers but can set a number of sysclks to wait 8

9 Preamble (required) PBL Image RCW (required) 1 st Pre-boot Command (optional)... Last Pre-boot Command (optional) End Command (required) 9

10 Overview of PBL Tool Capability Support for Rev 1.0 and Rev 2.0 silicon PBL tool creates entire PBL Image RCW (Reset Configuration Word) configuration PBI (Pre-Boot Initialization) commands Opens in HL browser that supports JavaScript Allows for portability User must save data and create file to load into their system Tool does not check validity of selections User must make sure selections adhere to P4080RM, P4080EC and P4080CE documents 10

11 Overview of PBL Tool Usage First 9 tabs represent the RCW components Organized according to the categories in the P4080RM (i) symbol provides additional information on each field Checkpoint can be saved as a browser cookie only for RCW field selections Tools tab Encode or decode of PBL images Calculate clock frequencies and data rates PBI tab Allows user to include PBI commands in power-on reset configuration 11

12 PBL Image Tool 12

13 Tools Tab - Encode 13

14 Encoding a PBL image PBL data formats XXD object dump (default) S-record Source code Tools Tab - Encode U-boot commands commands to type in U-boot to write PBL image to memory edink commands commands to type in edink to write PBL image to memory HEX string RCW data formats - RCW only without preamble and CRC CodeWarrior JTAG Configuration File HEX string Text table 14

15 Tools Tab - Decode 15

16 Decoding a PBL image PBL data formats XXD object dump (default) S-record Source code U-boot memory dump PBL image found in RCW source location edink memory dump PBL image found in RCW source location HEX string RCW data formats Tools Tab - Decode U-boot CCSR dump RCW only settings found in RCW status registers edink CCSR dump RCW only settings found in RCW status registers Code Warrior JTAG Configuration File HEX string Text table RCW hard-coded settings 16

17 Tools tab - Clocking Calculate System Clocks Inputs System clock SRDS Refclk 1/2/3 Push Calculate Clocks button Displays PLL and Clock frequencies within P

18 PBI Tab 18

19 PBI Tab PBI data CCSR address space CCSR data (4 byte) memory mapped register write CCSR data (1 byte) memory mapped register write PBL commands Flush CRC check Jump currently not implemented Wait ACS address space ACS data (4 byte) write to alternate configuration space such as DDR ACS file (XXD object file) 19

20 1. CCSR writes to configure DDR controller PBI Tab Loading an ACS File into DDR 2. CCSR writes to ALTCBARH/L and ALTCAR registers to set up base address and target of alternative configuration space for DDR 3. Flush command to ensure write to ACS registers takes affect 4. Place ACS.xxd file into the same folder where the PBL image tool resides 5. Select ACS File (XXD Object File) from the drop-down list 6. Enter the offset of the DDR address space where you want the file to be downloaded 7. Browse for the file 8. Click Add PBI Data button 20

21 Demo - Examples 21

22 Decoding a PBL image example Tools Tab Decode Example Common reset configuration file might be.bin (which is not decodable by the PLB image tool) 1. Use xxd to create an object dump of the.bin file 2. Paste the object dump into the decode field 3. Select PBL XXD Object Dump from the pulldown menu 4. Click the Decode PBL button 5. Now all RCW and PBI fields have been updated to reflect the decoded image 22

23 Tools Tab Encode Example Encoding a PBL image example 1. Select PBL XXD Object Dump from the pull down menu 2. Select address offset value for the start of the image (default is 0) 3. Click Encode PBL button 4. Copy and paste data into a vi editor and save file as.xxd 5. Use xxd r command to reverse the file into a.bin file 6. The.bin file can then be transferred to the preferred RCW source 23

24 PBI Tab Example Issuing PBI commands 1. Select CCSR Data (4 Byte) from the drop down list, fill in Offset and Data for register write 2. Select Flush from the drop down list and notice the Offset is set for you 3. Select ACS Data (4 Byte) from the drop down list, fill in Offset and Data for the address in Alternate Configuration Space you would like to write to 4. Select ACS File (XXD Object Dump) from the drop down list, fill in Offset and Browse for the file to load 5. Encode new PBL image and see PBI data added to image 24

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26 Notes 26

27 PLL Tab - RCW[0-127] SYSCLK to platform clock frequency settings DDR PLL frequency settings SYSCLK to core cluster PLL settings 4 core cluster PLLs Core complex 0-3 and core complex 4-7 must select a core cluster PLL to be used 27

28 SerDes PLL Tab RCW[ ] SerDes bank/lane assignments SRDS_PRTCL Bank 1 10 lanes PCIe, SRIO and Aurora (few SGMII exceptions) Bank 2 4 lanes FM2 XAUI and SGMII (few PCIe exceptions) Bank 3 4 lanes FM1 XAUI and SGMII SerDes reference clock to SerDes PLL frequency settings Lane power down per-bank SerDes enable 28

29 Misc PLL Tab RCW[ ] Selects DDR mode for both controllers Synchronous mode Memory controller complex PLL reference clock is platform clock Asynchronous mode Memory controller complex PLL reference clock is SYSCLK 29

30 Boot Tab RCW[ ] PBI source settings PBI addr/data commands are to be used for CCSR and/or local memory space PBI source must be same as RCW source Boot location PCIe, SRIO, DDR or elbc Can be different from RCW and PBI source, with the exception that only one elbc option can be chosen as the source of RCW, PBI and boot location Boot holdoff mode All cores except core0 or all cores are held in boot holdoff mode at out of reset Secure boot enable 30

31 Clocking Tab RCW[ ] Pattern match engine clock select Platform clock /2 Core cluster CC3 PLL /2 (PME will run asynchronous to the platform) Frame manager 1 and 2 clock select Platform clock /2 Core cluster CC3 PLL /2 (FMan will run asynchronous to the platform) 31

32 RCW[ ] Memory I/O tab RapidIO device ID Agent and Host mode selections General purpose tab GPIO pin selections 32

33 Pin Muxing Tabs RCW[ ] Pin muxing A tab 1588 clock settings RGMII / USB enabling UART I 2 C IRQ SPI Pin muxing B tab DMA 33

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