Macro in a Generic Logic Process with No Boosted Supplies

Transcription

1 A 700MHz 2T1C Embedded DRAM Macro in a Generic Logic Process with No Boosted Supplies Ki Chul Chun, Wei Zhang, Pulkit Jain, and Chris H. Kim University of Minnesota, Minneapolis, MN

2 Outline Motivation Proposed Fully Logic-compatible EDRAM 2T1C Gain Cell with No Boosted Supplies Enhancement of EDRAM Retention Time Single-ended 7T SRAM Repair Scheme Storage Monitor for PVT-aware Refresh Control 65nm EDRAM Chip Measurements Summary 2

3 Embedded Memory Options 65nm CMOS Cell Schematic Process Boosted supplies Cell size (ratio) Data storage Cell access Random cycle BL WL 6T SRAM [1] WL BLB Logic-compatible No required 1T1C edram [2] Gain cell edram [3] WL BL VP WWL RBL WBL Logic compatible Logic compatible +2 (FEOL)+3 (Cap) (+2 FEOL) Required (High & Low) Required (High & Low) 135F 2 (1X) 30F 2 (0.22X) 65F 2 (0.48X) [4] Latch (Static) Capacitor (20fF) MOS gate (<1fF) (+) Differential read (-) Destructive read (+) Decoupled read and (-) Ratioed operation (-) Refresh write, (-) Refresh 1GHz 500MHz 667MHz Static power 1X 0.2X RWL [1] K. Zhang et al., VLSI Symp. 2004, [2] J. Barth et al., ISSCC 2007, [3] K. Chun et al., VLSI Symp. 2010, [4] D. Somasekhar et al., ISSCC 2008 Gain cell considered as a strong contender for future embedded memories 3

4 Boosted Supplies in EDRAM Asymmetric 2T gain cell, K. Chun et al., VLSI Symp DRAMs require boosted high and low voltages Special thick T OX devices needed for reliability Focus of this work: Eliminating boosted supplies for a fully logic-compatible (single T OX ) design 4

5 Gain Cell with No Boosted Supplies WWL RWLB RWL PCOU Asymmetric 2T gain cell + Coupling device (PC) 5

6 Retention with No Boosted Supplies Conventional 2T Proposed 2T1C 1.Low data 1 level 2.Data 0 write-back 3.Narrow window between 1 and 0 1. Beneficial couple-up during read (PC) 2. Preferential couple-down during write-back (PC) 3. Circuit techniques to enhance retention time 1) Repair scheme utilizing single-ended 7T SRAM 2) Storage monitor for PVT-aware refresh control 6

7 Read and Write-back Timing Conventional 2T Proposed 2T1C ltage (V) Vol Cell voltag ge (V) A 0.2V beneficial couple-up read and a 0.28V preferential couple-down write-back [1] Regulated Write Bit-line, K. Chun et al., VLSI Symp

8 Single-ended 7T SRAM Repair Cell QB (V) Voltage (V V) Decoupled read and local differential write Shares control signals (WL s and BL s) with the 2T1C array allowing seamless integration 8

9 Tail Cell Repair Scheme 1.1V, 85ºC, t CYCLE =1.4ns >10 65nm LP, 1.1V, 85ºC >10 Retention time (msec) Word-line # (msec) 1-BL repair case with a target retention of 500µs 2T1C repair: 6.25% failure (left) 7T SRAM repair: No failure with 1.2% (4.8%) array overhead at 1-repair BL per 128 BL s (32 BL s) 9

10 Storage Voltage Monitor SCAN f RET V BIAS1 t CLK *PG CNT-1 VCO-1 4 WBL WWL PCOU RWL Mer rged Stor rage Voltage Φ Thick Tox device Φ 2 Φ Sampled voltage VCO-2 CNT-2 *PG: Cell Access Pattern Generator (Self-Repetitive) 2T1C Gain Cell Array (256cells) V CAL f VCELL Storage Voltage Sampling and Calibration Storage voltage monitor with varying retention time and under PVT variations Gain cell specific retention sensor including leakages and coupling effects for PVT-aware refresh control 10

11 EDRAM Test Chip Microphotograph C. PU UMP & DECA AP Y L L CONV 3T KBIT ARRAY 6 CELLS/BL 8 CELLS/WL WL DRIVER COL. DEC C. 64K COL. DEC. 7T SRAM 2T1C 64KBIT ARRAY 256 CELLS/BL 128 CELLS/WL WL DRIVER TEST INTERFACE STORAGE MONITOR STORAGE MON. CTRL Process 65nm LP CMOS Ckt dimension 556x345µm 2 Array size 2x64kbits (Conv. 3T & Prop. 2T1C) Cell size 58% of 6T SRAM Retention time 1.1V, 85ºC Random cycle time 1.40ns 1.1V VMIN 10µs retention *Refresh power 161.8µW per Mb (**0.28X of 6T SRAM) *@ 1.1V, 85ºC, 500µsec refresh rate **@ Retention voltage of 0.6V 714MHz random cycle at a 500μsec retention time with 1-BL repair per 32 BL s 72% lower data retention power compared with a power-gated 6T SRAM 11

12 Measured Retention Statistics 65nm LP CMOS, 1.1V, 85ºC Decreasing VBB CYCLE =2.0ns Propopsed 2T1C Asymmetric 2T (VPP=1.6V) Conventional 3T (VBB=-0.5V) Conventional 3T (VBB=-0.4V) Conventional 3T (VBB=-0.3V) Conventional 3T (VBB=-0.2V) 0.10 CYCLE =1.5ns Proposed 2T1C: 256cells/BL Conventional 3T: 256cells/BL No boosted CYCLE =1.4ns Asymmetric 2T: 512cells/BL (K. Chun et al., VLSI Symp. 2010) E-04 1.E-03 1.E-02 The proposed 2T1C gain cell achieves practical retention ti time (>100µs) with no boosted supplies 12

13 Measured VDD Shmoo Ra andom cy ycle time (nsec) nm LP CMOS, 85ºC Random cycle Retention time 1.E-01 1.E-02 1.E-03 1.E E-05 VMIN of 2T1C gain cell 0 1.E VDD (V) Rete ention tim me (sec) Static cu urrent (µa A/Mb) % 65nm LP CMOS, 85ºC w/ device mismatches 99.9% bit yield 6T SRAM leakage 2T1C refresh Retention voltage (V) Wide operating voltage range of 0.7V ~ 1.4V (left) 72% smaller refresh current than SRAM leakage at a power-down retention ti voltage of 0.6V (right) 13

14 Summary Gain cell edram contender for future e-memory Logic-compatible, decoupled read and write paths 2X bit cell density, 0.3X static current than SRAM A fully logic-compatible edram proposed 2T1C gain cell with no boosted supplies Single-ended 7T SRAM repair scheme Storage monitor for PVT-aware refresh control A 1.1V, 65nm 64kb edram chip demonstrated DRAM implementation based on only thin T OX devices 1.4ns cycle time at a retention time of 500µs at 85 C 161.8μW per Mbit static power dissipation at 85 C 14

15 Acknowledgements 1. Broadcom foundation 2. IBM faculty partnership program (Dr. Pong-Fei Lu) 3. Intel corporation 4. Samsung scholarship