The DRAM Cell. EEC 581 Computer Architecture. Memory Hierarchy Design (III) 1T1C DRAM cell
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1 EEC 581 Computer Architecture Memory Hierarchy Design (III) Department of Electrical Engineering and Computer Science Cleveland State University The DRAM Cell Word Line (Control) Bit Line (Information) Why DRAMs Higher density than SRAMs Disadvantages Longer access times Leaky, needs to be refreshed Cannot be easily integrated with CMOS 2 1T1C DRAM cell Storage Capacitor Stack capacitor (vs. Trench capacitor) Source: Memory Arch Course, Insa. Toulouse 1
2 DRAM BANKS DRAM INTERFACE L2 CACHE 1 L2 CACHE 0 L2 CACHE 3 L2 CACHE 2 SHARED L3 CACHE Main Memory in the system Main Memory in the System CORE 0 CORE 1 DRAM MEMORY CONTROLLER CORE 2 CORE One DRAM Bank bitlines Address Row decoder wordline Column decoder Sense amps I/O gating Data out 4 2
3 Memory Bank Organization 5 Example: 512Mb 4-bank DRAM (x4) 2k BA[1:0] Address A[13:0] Row Row decoder Row decoder Row decoder decoder Bank x 2048 x 4 16K A[10:0] Column Column decoder decoder Column decoder Column decoder Sense amps I/O gating A DRAM page = 2kx4 = 1KB Address Multiplexing Data out D[3:0] 6 A x4 DRAM chip 3
4 SRAM (Static Random Access Memory) 7 SRAM vs DRAM 8 4
5 DRAM Cell Array Wordline0 Wordline1 Wordline2 Wordline3 Wordline1023 bitline0 bitline1 bitline2 bitline15 9 DRAM Sensing (Open Bitline Array) WL0 WL1 WL2 WL127 WL128 WL129 WL130 WL255 Sense Amp A DRAM Subarry 10 A DRAM Subarry 5
6 Basic DRAM Operations WL BL Vdd/2 Vdd Sense Amp Vdd/2 driver Vdd - Vth Write 1 WL BL Precharge to Vdd/2 Vdd/2 + V signal Sense Amp Vdd/2 C BL Cm Vdd - Vth V signal refresh Vdd Cm 2 C C m BL Amplified V signal Read 1 11 Memory Subsystem Organization 12 6
7 Memory'subsystem' Channel ' DIMM'(Dual'in2line'memory'module)' Processor' Memory'channel' Memory'channel' 13 Breaking Down a DIMM Breaking'down'a'DIMM' DIMM'(Dual'in2line'memory'module)' Side'view' Front'of'DIMM' Back'of'DIMM' 14 7
8 Breaking'down'a'DIMM' DIMM'(Dual'in2line'memory'module)' Side'view' Front'of'DIMM' Back'of'DIMM' Rank'0:'collec1on'of'8'chips' Rank'1' 15 Rank Rank' Rank'0'(Front)' Rank'1'(Back)' <0:63>' <0:63>' Addr/Cmd' CS'<0:1>' Data'<0:63>' Memory'channel' 16 8
9 DIMM'&'Rank'(from'JEDEC)' DIMM & Rank (from JEDEC) 17 Breaking down a Rank Breaking'down'a'Rank' Rank'0' Chip'0' Chip'1'.'.'.' Chip'7' <0:63>' <8:15>' <56:63>' Data'<0:63>' 18 9
10 ...' Breaking down a Chip Breaking'down'a'Chip' Chip'0' Bank'0'...' 19 Breaking down a Bank Breaking'down'a'Bank' 2kB' 1B'(column)' row'16km1' Bank'0' row'0' 1B' Row2buffer' 1B'...' 1B' 20 10
11 Transferring Cache Block Example:'Transferring'a'cache'block' Physical'memory'space' 0xFFFF F' Channel'0'...' DIMM'0' 0x40' 64B'' cache'block' Mapped'to' Rank'0' 0x00' 21 Transferring Cache Block Example:'Transferring'a'cache'block' Physical'memory'space' 0xFFFF F' Chip'0' Chip'1' Chip'7' Rank'0'.'.'.' <8:15>' <56:63>'...' 0x40' 64B'' cache'block' Data'<0:63>' 0x00' 22 11
12 Transferring Cache Block Example:'Transferring'a'cache'block' Physical'memory'space' 0xFFFF F'...' 0x40' 0x00' 64B'' cache'block' Row'0' Col'0' Chip'0' Chip'1' Chip'7' Rank'0' <8:15>'.'.'.' Data'<0:63>' <56:63>' 23 Transferring Cache Block Example:'Transferring'a'cache'block' Physical'memory'space' 0xFFFF F'...' 0x40' Row'0' Col'0' Chip'0' Chip'1' Chip'7' Rank'0' <8:15>'.'.'.' <56:63>' 0x00' 8B' 64B'' cache'block' 8B' Data'<0:63>' 24 12
13 Transferring Cache Block Example:'Transferring'a'cache'block' Physical'memory'space' 0xFFFF F'...' 0x40' Row'0' Col'1' Chip'0' Chip'1' Chip'7' Rank'0' <8:15>'.'.'.' <56:63>' 0x00' 8B' 64B'' cache'block' Data'<0:63>' 25 Transferring Cache Block Example:'Transferring'a'cache'block' Physical'memory'space' 0xFFFF F'...' 0x40' Row'0' Col'1' Chip'0' Chip'1' Chip'7' Rank'0' <8:15>'.'.'.' <56:63>' 0x00' 8B' 8B' 64B'' cache'block' Data'<0:63>' A'64B'cache'block'takes'8'I/O'cycles'to'transfer.' ' During'the'process,'8'columns'are'read'sequenUally.' 26 13
14 D0 D7 D8 D15 CB0 CB7 D16 D23 D24 D31 D32 D39 D40 D47 D48 D55 D56 D63 D0 D7 D8 D15 D16 D23 D24 D31 D32 D39 D40 D47 D48 D55 D56 D63 DRAM Basics Address multiplexing Send row address when RAS asserted Send column address when CAS asserted DRAM reads are self-destructive Rewrite after a read Memory array All bits within an array work in unison Memory bank Different banks can operate independently DRAM rank Chips inside the same rank are accessed simultaneously 27 Examples of DRAM DIMM Standards x64 (No ECC) 28 X72 (ECC) 14
15 D0 D7 D8 D15 D16 D23 D24 D31 D32 D39 D40 D47 D48 D55 D56 D63 Memory Controller DRAM Ranks CS0 Rank0 Rank1 CS1 29 DRAM Ranks 64b 8b 8b 8b 8b 8b 8b 8b 8b Single Rank 64b 4b 4b 4b 4b 4b 4b 4b 4b 4b 4b 4b 4b 4b 4b 4b 4b Single Rank 64b 8b 8b 8b 8b 8b 8b 8b 8b 8b 8b 8b 8b 8b 8b 8b 8b 30 Dual- Rank 64b 15
16 DRAM Organization Source: Memory 31 Systems Architecture Course, B. Jacobs, Maryland Organization of DRAM Modules Addr and Cmd Bus Memory Controller Channel Data Bus Multi-Banked DRAM Chip Source: Memory Systems Architecture Course Bruce Jacobs, University of Maryland 32 16
17 Memory Structure Generalized Memory Structure 33 DRAM Configuration Example Source: MICRON DDR3 DRAM 34 17
18 DRAM Access (Non Nibble Mode) RAS CAS ADDR Row Addr Col Addr Col Addr DATA Data Data Memory Controller WE RAS CAS Addr Bus Assert RAS Assert CAS Column Row Address DRAM Module Data Bus Row Opened 35 DRAM Refresh Leaky storage Periodic Refresh across DRAM rows Un-accessible when refreshing Read, and write the same data back Example: 4k rows in a DRAM 100ns read cycle Decay in 64ms 4096*100ns = 410 s to refresh once 410 s / 64ms = 0.64% unavailability 36 18
19 DRAM Refresh Styles Bursty 410 s =(100ns*4096) 410 s 64ms 64ms Distributed 15.6 s 100ns 64ms 64ms 37 DRAM Refresh Policies RAS-Only Refresh Memory Controller WE RAS CAS Addr Bus Assert RAS Row Address DRAM Module Refresh Row CAS-Before-RAS (CBR) Refresh 38 Memory Controller RAS CAS WE# Addr Bus Assert RAS Assert CAS WE High DRAM Module Addr counter Increment Refresh Row counter No address involved 19
20 Types of DRAM Asynchronous DRAM Normal: Responds to RAS and CAS signals (no clock) Fast Page Mode (FPM): Row remains open after RAS for multiple CAS commands Extended Data Out (EDO): Change output drivers to latches. Data can be held on bus for longer time Burst Extended Data Out: Internal counter drives address latch. Able to provide data in burst mode. Synchronous DRAM SDRAM: All of the above with clock. Adds predictability to DRAM operation DDR, DDR2, DDR3: Transfer data on both edges of the clock FB-DIMM: DIMMs connected using point to point connection instead of bus. Allows more DIMMs to be incorporated in server based systems RDRAM Low pin count 39 20
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