Memory Classification revisited. Slide 3

Transcription

1 Slide 1

2 Topics q Introduction to memory q SRAM : Basic memory element q Operations and modes of failure q Cell optimization q SRAM peripherals q Memory architecture and folding Slide 2

3 Memory Classification revisited Slide 3

4 Technology choices for memory hierarchy Chart: J.Barth Cost ~9F 2 NOR FLASH DRAM SRAM NAND FLASH ~4.5F 2 6-8F 2 ~120F 2 Hard Disk Tbits/in 2 Performance

5 Cache Sizes AMD Zen ISSCC kB L2$, 8MB L3$ PCIe Signaling SMP/Accelerator Signaling L2 L3 Region L3 Region PCIe L2 L3 Region L2 IBM POWER9 Hotchips kB L1 I$ and D$, 120MB e-dram L3$ L2 L3 Region L3 Region L2 L3 Region L2 SMP Interconnect & Off-Chip Accelerator Enablement Memory Signaling L2 L3 Region L3 Region L2 L3 Region L2 L2 L3 Region L3 Region L2 On-Chip Accel L3 Region L2 SMP Signaling SMP/Accelerator Signaling Memory Signaling

6 Cache size impacts cycles-per-instruction For a 5GHz processor, scale the numbers by 5x Several memory blocks in a typical processor core: I$, D$, Address translation tables, Branch history tables, all in the KB low MB range

7 Question 1 q SRAMs are preferred for L1 Cache over edrams a) Refresh operation of e DRAM causes undesirable performance penalty b) e-drams is too slow for high speed operation c) SRAMs are compact and can easily fit near functional blocks d) e-drams requires multiple supply voltages Slide 7

8 Topics q Introduction to memory q SRAM : Basic memory element q Operations and modes of failure q Cell optimization q SRAM peripherals q Memory architecture and folding Slide 8

9 Basic Memory Element Q Q 9

10 Access ways BL BR WL0 10

11 No Operation (Hold) WL0 BL BR BL BR WL1 1 Selected for WRITE COL0 COL1 11

12 12 Hold Margin

13 S. Mukhopadhyay, ITC 2010 Hold Failure WL=0 AXL L= 1 PL V DDH PR AXR Voltage WL V DDH V R V L NL NR R= 0 Time -> BL HF ( V ) P = P V > DDHmin HOLD BR Voltage WL V DDH V L V R Time -> Hold Failure => Flipping of cell data in the Hold mode with the application of a lower supply voltage.

14 Question 2 q Hold Margin for an SRAM cell a) Is always greater than read margin b) Can be improved by making the access transistor bigger c) Defines the minimum supply voltage required to perform a read operation d) Depends on the number of cells on the bit line Slide 14

15 Read Operation WL0 BL BR BL BR WL1 1 Selected for READ COL0 COL1 15

16 S. Mukhopadhyay, ITC 2010 Read Failure WL V TRIPR D AXL V L = 1 PL NL PR NR V R = 0 V READ AXR Voltage WL V L V R =V READ Time -> BL BR Voltage WL V R ( V ) P = P V > RF READ TRIPRD Read failure => Flipping of Cell Data while Reading V L Time ->

17 Hold vs Read Margin

18 Write Operation WL0 BL BR BL BR WL1 1 Selected for WRITE COL0 COL1 18

19 S. Mukhopadhyay, ITC 2010 Write Failure WL T WL AXL L= 1 PL PR AXR Voltage WL V R V L NL NR R= 0 Time -> BL WF ( T ) P = P T > WRITE WL BR WL V L V R Write Failure => Unsuccessful write to the cell. Voltage Time ->

20 1.000 Write Margin Q :READ / WRITE Q0 20

21 S. Mukhopadhyay, ITC 2010 Access Failure WL= 0 BL V L = 0 WL= 1 Voltage DMIN BR PL AXL V L = 1 PR NR V R = 0 AXR WL NL BL P = P T > AF ( ACCESS TMAX BR ) Time -> T MAX T AC >T MAX Access Failure : Time required to produce a pre-specified bit-differential is higher than a maximum allowed time.

22 Question 2b q Write Margin for an SRAM cell a) Is always greater than read margin b) Can be improved by making the access transistor bigger c) Defines the minimum supply voltage required to perform a read operation d) Depends on the number of cells on the bit line Slide 22

23 The Balancing Act AL PL PR AR NL NR Large N: Better READ performance. If too large, trip voltage of inverter becomes so low that cell becomes unstable. Large A: Better Performance. If too large, storage node voltage goes high during READ, causing cell flip Large P: Increase stability. If too large, hard to WRITE. Need to balance all : NR:XR:PR ~ 2:1:1

24 Workhorse 6T-Cell WRITE WL=VDD READ WL=VDD HOLD WL=0 1 -> 0 0->1 1 0 Iread 1 0 BL=GND BLb=VDD BL=VDD BLb=VDD BL=VDD BLb=VDD Pull Up Xr Pull down Xr Access Xr Access Xr: On Data driven on bit - lines Data Flipped by overcoming pull-up / pull down Xrs Acess Xr: On BL, Blb pre-conditioned, and then floated, one line discharges thru the cell (Iread), voltage sensed, Data Retained Access Xr : Off Data Retained, due to back-to-back inverters

25 Thin Cell (Litho-Friendly) Cell area vital for density Flip NMOS PMOS Flip R0 MX MY R180 Flip

26 Question 2c qdecreasing the size of only one side of NFET transistors will improve the cell a) Cell density b) Read margin c) Write margin d) Hold margin Slide 26

27 Topics q Introduction to memory q SRAM : Basic memory element q Operations and modes of failure q Cell optimization q SRAM peripherals q Memory architecture and folding Slide 27

28 Decoders and Drivers WL driver WL driver cell cell cell cell cell cell cell cell Word line driver layout needs to be pitch matched to SRAM cell WL driver WL driver cell cell cell cell cell cell cell cell Decoder and Control Column Circuitry

29 Column Circuitry for Read and Write READ WRITE

30 Sense Amplifiers bit bit_b sense_clk isolation transistors regenerative feedback sense sense_b Sense-amp provide necessary gain (small input à large output) for read If sense_clk arrives too early è False read may happen due to too small difference If sense_clk arrives too late è Too slow Isolation transistors: Disconnects sense amp to cutoff large bit line capacitance once sensing starts

31 Hierarchical Bit-lines Hierarchical Bit-lines

32 Pre-Conditioning Precharge bit bit_b Equalizer bit bit_b Pre-Conditioning

33 Question 3 qequalizer is required a) Both the bitlines are pre-charged at the same time b) To ensure that the bit-lines are conditioned suitably for write operation c) To minimize offset between the bitlines prior to read operation d) To improve the hold and read margin of the memory cells Slide 33

34 Topics q Introduction to memory q SRAM : Basic memory element q Operations and modes of failure q Cell optimization q SRAM peripherals q Memory architecture and folding Slide 34

35 Memory Architecture 2 n words of 2 m bits each, If n >> m, fold by 2 k into fewer rows of more columns wordlines bitline conditioning bitlines row decoder memory cells: 2 n-k rows x 2 m+k columns n-k n k column decoder 2 m bits column circuitry Good regularity easy to design Utilization = Cell Area / (Cell + Periphery Area)

36 Why memory is folded? To improve aspect ratio by column multiplexing E.g.: 2Kword x 16 can be arranged as 256 rows and 128 columns 8:1 MUX are used to read 16 desired columns out of 128 To improve soft-error immunity bits of a word are not placed next to each other Single-bit soft-error can be corrected by ECC 36

37 Column Select and Half-Select Issue WL selected column non-selected column Prevents multiple-bit soft error Better aspect ratio

38 Class Exercise q Build a schematic of a 6T SRAM cell with minimum sized PFETs, Pull down = 3*PFET size, and Access transistor = 2* PFET size. Simulate it and plot butterfly curve for margins q Change Pull down size to 4*PFET size and re-simulate q Change Access transistor size to 3*PFET size and re-simulate q Change pull up device size to 2 original size and re-simulate Slide 38

39 Next Class q Alternative Cell Types (6 to 10T), Asymmetric Cells, Subthreshold Cells, Low leakage cells Slide 39