Topic 11: Interrupts ISMAIL ARIFFIN FKE UTM SKUDAI JOHOR

Transcription

1 Topic 11: Interrupts ISMAIL ARIFFIN FKE UTM SKUDAI JOHOR

2 Objectives To become familiar with interrupts on the AVR Maskable and non-maskable Initialization Triggers To develop interrupt service routines (ISRs) to handle interrupts To understand the sequence of events that occur when an IRQ occurs

3 Interrupts Interrupts are asynchronous changes in program flow that occur as a result of events outside the running program. They are usually hardware related:examples: button press, timer expiration, peripheral device needs data, etc Interrupt conditions are independent of the program. Interrupts can happen at any time (asynchronous)

4 Maskable/Non-maskable Interrupts in general can be divided into two kindsmaskable and non-maskable. A maskable interrupt is an interrupt whose trigger event is not always important: The program can decide if the event should be recognized or ignored and can be disabled/enabled A non-maskable interrupt is so important that it should never be ignored The processor will always jump to this interrupt when it happens The reset button is an example.

5 Interrupts on the ATmega32 External interrupt inputs are pins INT2 -INT0 They are triggered by: A high-to-low transition (a falling edge) on one of these pins A low-to-high transition (a rising edge) on one of these pins A low level on one of these pins They are initialized by: MCUCSR Register for INT2:0.

6 AVR Operating Mode o Normal AVR perform main routine continuously. o Interrupt AVR perform special routine upon receiving input request (asynchronous). AVR receives input request from internal or external. Each interrupt has its own routine referred as interrupt service routine (in short ISR). AVR Atmega32 has allocated three inputs for external interrupts and many for internal interrupts. The interrupts are prioritized and vectored. Each interrupt has its vector number and orderly locates interrupt priority.

7 Interrupt versus Polling o AVR responded method to inputs: Interrupt o An asychronous event to make AVR deviating to a special program from the main program. The AVR run the special program after it is being triggered by an input. o Upon receiving the input signal, AVR stops its current main program, deviate to the special program, finish and back running the main program. o Special program that belongs to interrupt event is called an interrupt service routine (ISR) or aninterrupt handler. Polling o The AVR always inspects all input request routinely; when the status is received, AVR branches to the assigned program.

8 Interrupt vs Polling Efficient use of CPU Interrupts Can serve many devices, which each device get attention of the CPU based on the priority assigned to it. The CPU can ignore (mask) a device request for service. Avoid tying down the CPU, thus the waste time can be used to perform some useful tasks. Polling Not and efficient use of CPU Cannot assign priority, it checks all devices in a round-robin fashion. Cannot ignore device request. Wastes much CPU time by polling device that do not need service.

9 Interrupt Vector Table (AVR Atmega32 Interrupt List) 9

10 Interrupt Vector Table for ATmega32 (ATmega32A) 10

11 Interrupt Service Routine o For every interrupt, there must be ISR, since when an interrupt is invoked, AVR runs the ISR. o Generally, for every ISR there is a fixed location in memory that holds the address of its ISR. o The group of memory locations set aside to hold the addresses of ISRs s called interrupt vector table. o Vector interrupt is used to bridge between the triggering interrupt input and the interrupt s assigned (software) task. o All interrupts involved are vectorily initialized at the beginning of the AVR main program to provide link to its own interrupt service routine. ISR hasits own AVR task. ISR is located after the AVR main program and each ISR contains RETI as its last line.

12 Steps in executing an interrupt o Upon activation of an interrupt, the AVR goes through the following steps: 1. It finishes the instruction it s currently executing and saves the address of the next instruction (PC) on the stack. 2. Jumps to a fixed location in memory called the interrupt vector table. The interrupt vector table directs the AVR to the address of ISR. 3. AVR starts execute the ISR until reaches the last instruction of the subroutine, RETI. 4. Upon executing RETI, AVR returns to the place where it was interrupted gets the PC address from the stack.

13 Steps in executing an interrupt PB0 PB1 (INT2) PB2 (OC0/AIN0) PB3 (SS) PB4 (MOSI) PB5 (MISO) PB6 (SCK) PB7 RESET VCC GND XTAL2 XTAL1 (RXD) PD0 (TXD) PD1 (INT0) PD2 (INT1) PD3 (OC1B) PD4 (OC1A) PD5 (ICP) PD ATmega32 PC: 000D 000E 000A F 000C 000B SP Stack VCC PA0 (ADC0) PA1 (ADC1) PA2 (ADC2) PA3 (ADC3) PA4 (ADC4) PA5 (ADC5) PA6 (ADC6) PA7 (ADC7) AGND AVCC PC7 (TOSC2) PC6 (TOSC1) PC5 (TDI) PC4 (TDO) PC3 (TMS) PC2 (TCK) PC1 (SDA) PC0 (SCL) PD7 (OC2) Address A 000B 000C 000D 000E 000F Code #INCLUDE <avr/interrupt.h> void isr(into.vect) unsigned char int0data ; int0data=portc^0x08; PORTC = int0data; } int main () { DDRC = 1 << PC3 ; //PC.3 = output PORTD=1 << PD2 ;//pull-up activated GICR= 1<<INT0 ;//Enable INT0 SEI() ;//Set I (Enable Interrupts) num1= 3 ; num2 = 4 ; sum = num1 + num2 ; while (1); return 1; }

14 Interrupt Units in AVR

15 Enabling and Disabling An Interrupt o Upon reset, all interrupts are disabled (masked) none will be responded to by AVR if they are activated. o The interrupt must be enabled (unmasked) for AVR to respond to them. o How? The D7 bit of SREG responsible to enable and disable the interrupt globally. o Bit D7 (I) of SREG must be set HIGH to allow interrupt to happen by using SEI instruction, I = 1. To disable use CLI instruction, I = 0. o But there are some I/O registers holding interrupt enable bits even though I = 1, i.e. TIMSK register has interrupt enable bit for Timer0, Timer1 and Timer2.

16 Enabling and Disabling An Interrupt

17 External Interrupt Programming

18 Programming External Interrupt o There are three external hardware interrupt: o INT0 located on pin PD2, vector table location $2 o INT1 located on pin PD3, vector table location $4 o INT3 located on pin PB2, vector table location $6 o The hardware interrupts must be enabled before they can take effect. o This is done using INTx bit located in the GICR register.

19 Programming External Interrupt o Example: the following instruction enable INT0. GICR = 0x40 ; // Enable external interrupt INT0 (PD2 pin 16) o The INT0 is a low-level-triggered interrupt by default when a low signal is applied to pin PD2, the controller will be interrupted and jump to location $0002 in the vector table to service ISR.

20 o Example: Assume that the INT0 pin is connected to a switch that is normally high. Write a program that toggles PORTC.3, whenever the INT0 pin goes low. #include <avr/io.h> #include <avr/interrupt.h> void ISR(INT0_vect) { portc = ~portc ; //toggle PC3 } void initint(void ) { ddrd = ddrd ~ (1 << int0) ; // portd2 as input portd = portd 1 << int0 ; // pull-up portd2 gicr = 1 << int0 ; // enable int0 mcucr = 0b ;// low level input trigger sei () ; // enable global interrupt } int main (void) { ddrc = ddrc 1 << portc3 ; // portc3 as output portc = portc 1 << portc3 ; // initial PC3 high initint(); while (1) { // loop forever wait for INT0 interrupt What } happen by time micro-p execute RETI and return INT0 still 1 ; LOW? } Programming External Interrupt

21 Programming External Interrupt o Example: Assume that the INT0 pin is connected to a switch that is normally high. Write a program that toggles PORTC.3, whenever the INT0 pin goes low. What happen by time micro-p execute RETI and INT0 still LOW?

22 Programming External Interrupt: Edge vs Level Triggered o There are two types of activation for the external hardware interrupts: o Level triggered INT0 & INT1 o Edge triggered INT0, INT1 & INT2. o The ISC2 bit of the MCUCSR register indicate whether INT2 is active in the falling edge or rising edge.

23 Programming External Interrupt: Edge vs Level Triggered o The bits for the MCUCR register indicate the trigger option of INT0 and INT1.

24 Programming External Interrupt: Edge vs Level Triggered o Example: show the instruction (a) make INT0 falling edge triggered, (b) make INT1 triggered on any change, and (c) make INT2 rising edge triggered. a) MCUCR = 0X02 b) MCUCR = (1<<ISC10) ; //MCUCR = 0x04 c) MCUCR =(1<<ISC2) ; // MCUCR = 0x40

25 Programming External Interrupt: Edge vs Level Triggered o Example: Rewrite previous switch example, so that whenever INT0 goes low, it toggles PORTC.3 only once.

26 Example Assembly codes that initialised External Interrupt INT0 and INT1 only //Iniltialise STACK //Enable INT0 and INT1 ddrd = ddrd ~ (1<< Int0) ; //set INT0 pin as input portd = portd 1<< int0 ; //enable pull-up resistor on INT0 pin ddrd = ddrd ~ (1 << int1) ; //set INT1 pin as input portd = portd 1<<int1 ; //enable pull-up resistor on INT1 pin gicr = 0b ; //enable INT0 and INT1 // Set INT0 and INT1 to detect falling edge MCUCR = 0b ; // mcucr = 0x0A //Enable Global Interrupt sei() ; 26

27 Example C/C++ codes that initialised External Interrupt INT0 and INT1 only /*The codes to Initialise Stack by default will be generated by the C/C++ compiler. The following statements will only set DDRD2, PD2, INT0 and ISC01, and Clear ISC00. Other bits in respective registers are untouched so setting of other interrupts are not changed. DDRD=DDRD (~(1<<PD2)); // PortD2 as input PORTD=PORTD (~(1<<PD2)); // Pull-up PortD2 GICR=GICR 1<<INT0 ; // enable INT0 MCUCR = MCUCR 1<<ISC01; // INT0 input falling edge MCUCR = MCUCR&((1<<ISC00)^0xff); /*The following statements will only set DDRD3, PD3, INT1, ISC01 and ISC00. Other bits in respective registers are untouched so setting of other interrupts are not changed.*/ DDRD=DDRD ((1<<PD3)^0xff); //Using Ex-or to NOT (1<<PD3) PORTD=PORTD ((1<<PD3)^0xff); GICR=GICR 1<<INT1; MCUCR = MCUCR 1<<ISC11 1<<ISC10; 27

28 Timer Interrupt Programming

29 Programming Timer Interrupt o There are at two timer interrupts: o Overflow / Rollover timer flag o Compare match timer flag o Basically, in ATmega32 there are three timers: Timer0, Timer1, Timer2. o Timer0 and Timer2 are 8-bit, while Timer1 is 16-bit. (will cover more details on how to program timers on the next module)

30 Programming Timer Interrupt: Rollover Timer Flag o If the timer interrupt in the interrupt register is enabled, the timer over flow flag (TOVx) is raised whenever the timer rolls over and the micro-p jumps to the interrupt vector to service the ISR. o To enable the interrupt for a given timer, we must set the TOIEx bit that held by TIMSK register. o To enable (unmask) the Timer interrupt let says Timer0, we should write as follows: TIMSK = 1 << TOV0 S() ; // enable Timer 0 overflow interrupt ; // enable interrupt globally

31 Programming Timer Interrupt: Rollover Timer Flag o Example: Write a program to (a) enable (unmask) the Timer0 overflow interrupt, (b) disable (mask) the Timer0 overflow interrupt, and show how to disable (mask) all the interrupts with a single instruction. a) TIMSK = (1<<TOIE0) ; //set TOE0=1 SEI() ;//allow interrupt to come in b) TMASK = TIMSK ; // Read TIMSK TIMSK=(1<<TOIE0) ;//clear TOIE0=0 ->mask (disable) Timer0 //interrupt c) CLI () ;//mask all interrupt globally

32 Programming Timer Interrupt: Compare Match Timer Flag o Sometimes a task should be done periodically. o The program can be written using the CTC mode and compare match (OCF) flag. o To do so, load the OCR register with the proper value and initialize the number to the CTC mode. o When the content of TNCT matches with OCR, the OCF flag is set. Which cause the compare interrupt to occur. (See next module for detail)

33 Programming Timer Interrupt: Compare Match Timer Flag o Example: Using Timer0, write a program that toggles pin PORTB.5 every 40μs, while at the same time transferring data from PORTC to PORTD. Assume XTAL = 1MHz.

34 Interrupt Priority & Interrupt inside Interrupt

35 Interrupt Priority o What will happen when two interrupts are activated at same time? Which one will responds first? o Answer: Interrupt Priority! o If two interrupts are activated at the same time, the interrupt with the higher priority is served first. o The priority of interrupt is related to the address of that interrupt in the interrupt vector. o Example: Address of INT0 = $2 and INT2 = $6. thus INT0 has higher priority.

36 Interrupt inside Interrupt o What happen if AVR is executing an ISR belonging to an interrupt and another interrupt is activated? o Answer: When AVR begins to execute an ISR, it disables the I bit in SREG causing all the interrupts to be disabled, thus no other interrupt occurs while serving the interrupt. When RETI is executed, AVR enables I bit in SREG, causing the other interrupts to be served.

37 Context Saving in Task Switching o In multitasking system, the CPU serve one task at a time and then moves to the next one. For example: (1) Copying the contents of PORTC to PORTD (2) Toggling PORTC.2 every 5μs o To write a program of multitasking system, we should manage resource carefully so that its not conflict with each other.

38 o Example: thy system performs (1) increasing contents of PORTC continuously and (2) increasing content of PORTD once every 5μs. Context Saving in Task Switching o DOES THE PROGRAM WORKS? o Not working: they have resource conflict and they interfere with each other!!!

39 Context Saving in Task Switching o How to overcome such situation? 1) Using different registers for different tasks. 2) Context saving we can save the contents of registers on the stack before execution of each task, and reload the registers at the end of the task.

40 Saving Flag of SREG Register o The flags of SREG are important especially when there are conditional jumps in our program. o Thus, we should save the SREG register if the flags are changed in a task, especially those who involves with ISR.

41 Interrupt Programming In C : Refers AVR ebook for details. (Section 10.5, pg:385)

42 Atmel Studio C/C++ Interrupt Service Routine Keywords for the ATmega32/ATmega32A Vector Address Source ATmel Studio C/C++ No. Name Event Keywords 1 $000 Reset No needed since it is Changes from High by default assigned to Low at On Chip s by C/C++ compiler RESET Pin referencing to main() function 2 $002 INT0 Status at On Chip s INT0_vect INT0 Pin as defined by ISC01:ISC00 bits of the MCUCR register 3 $004 INT1 Status at On Chip s INT1_vect INT1 Pin as defined by ISC11:ISC10 bits of the MCUCR register Interrupt Definition External Pin, Power - on Reset, Brown -out Reset, Watchdog Reset, and JTAG AVR Reset External Interrupt Request 0 External Interrupt Request 1 45

43 Atmel Studio C/C++ Interrupt Service Routine Keywords for the ATmega32/ATmega32A Vector Address Source ATmel Studio No. Name Event C/C++ Keywords 4 $006 INT2 Status at on INT2_vect Chip s INT1 Pin as defined by ISC2 bit of the MCUCSR register 5 $008 TIMER1 OCF1A bit of TIMER1_COMPA_ve COMPA TIFR register is ct set 6 $00A TIMER2 OVF OCF2 bit of TIFR register is set 7 $00C TIMER1 CAPT ICF1 bit of TIFR register is set 8 $00E TIMER2 COMP OCF2 bit of TIFR register is set Interrupt Definition External Interrupt Request 2 Timer/Counter 1 Compare Match A TIMER2_OVF_vect Timer/Counter 2 Overflow TIMER1_CAPT_vect Timer/Counter 1 Capture Event TIMER2_COMP_vect Timer/Counter 2 Compare Match 46

44 Atmel Studio C/C++ Interrupt Service Routine Keywords for the ATmega32/ATmega32A Vector Address Source ATmel Studio C/C++ No. Name Event Keywords 9 $010 TIMER1 OCF1B bit of TIMER1_COMPB_vect COMPB TIFR register is set 10 $012 TIMER1 OVF T0V1 bit of TIMER1_OVF_vect TIFR register is set 11 $014 TIMER0 COMP OCF0 bit of TIMER0_COMP_vect TIFR register is set 12 $016 TIMER0 OVF T0V0 bit of TIMER0_OVF_vect TIFR register is set 13 $018 SPI, STC SPIF bit of SPSR SPI_STC_vect Register is set 14 $01A USART, RXC RXCIE of UCSRB bit is set USART_RXC_vect Interrupt Definition Timer/Counter 1 Compare Match B TIMER1 OVF Timer/Counter 1 Overflow Timer/Counter 0 Compare Match Timer/Counter 0 Overflow Serial Transfer Complete USART Rx Complete 47

45 Atmel Studio C/C++ Interrupt Service Routine Keywords for the ATmega32/ATmega32A Vector Address Source ATmel Studio Interrupt No. Name Event C/C++ Keywords Definition 15 $01C USART, UDRE UDRIE bit of UCSRB register is set USART_UDRE_vect USART Data Register Empty 16 $01E USART, TXC TXC bit of UCSRB register is set USART_TXC_vect USART, Tx Complete 17 $020 ADC ADC_vect ADC ACIE bit is ACSR Conversion register is set Complete 18 $022 EE_ RDY EEWE bit EECR register is cleared EE_RDY_vect EEPROM Ready 19 $024 ANA_COMP ACI bit is ACSR register is set 20 $026 TWI activated for as long as the TWINT Flag of TWCR is high 21 $028 SPM_ RDY executed as long as the SPMEN bit in the SPMCR Register is cleared. ANA_COMP_vect TWI_vect SPM_RDY_vect Analog Comparator Two -wire Serial Interface Store Program Memory Ready 48

46 Interrupt Vector Table Location of information to tell CPU where to find the service routine of the respective interrupt. When source of Interrupt is generated (after it has been enabled and Global Interrupt Enabled bit is set), PC (program Counter) will be initialised with value Vector Address defined under the Program Address column of the interrupt generated. The event of interrupt is given under the Interrupt Definition column. If RESET occur, PC will be initialised with $0000 (though the number is 3 hex digit under Program Address, a 4 hex digit number will be stored to PC because PC is a 16 bit register). If INT2 interrupt occurs, PC will be initialised with $0006. Except RESET that does not have a current instruction that it is executing, when an interrupt occur, the CPU will complete the current instruction that it is executing and save the address of PC (next instruction to be executed) to the STACK before PC is initialised with interrupt vector Address. 49

47 C Language Example in Setting Up INT0, INT1 and INT2 ISR //Interrupt Service Routine for trigger on Pin INT0 ISR(INT0_vect) { // Codes here; } //Interrupt Service Routine for trigger on Pin INT1 ISR(INT1_vect) { // Codes here; } //Interrupt Service Routine for trigger on Pin INT2 ISR(INT2_vect) { // Codes here; } In C language programming, when the Interrupt Service Routine Keywords is used as the name of the function, the RETI instruction will be inserted by default by the Atmel Studio C/C++ (GCC) compiler. 50

48 Interrupt Flags and Interrupt Enabled bits The interrupt flag bit is set whenever the interrupt event occurs, whether or not the interrupt is enabled. The interrupt enabled bit is used to enable or disable a specific interrupt. Basically is tells the microcontroller whether or not it should respond to the interrupt if it is triggered. 51

49 Global Interrupt Enabled Bit Tell CPU to service all interrupts are enabled Apart from the enabled bits for the specific interrupts the global interrupt enabled bit MUST be enabled for interrupts to be activated in the microcontroller. For the AVR 8-bits microcontroller this bit is located in the Status I/O Register (SREG). The Global Interrupt Enabled is bit 7, the I bit, in the SREG. In assembly language the SEI instruction set the I bit and the CLI instruction clear the bit. In C/C++ language the sei() function set the I bit and the cli() function clears the bit. The functions are declared in AVR/interrupt.h which must be included in the C program. 52

50 Interrupt Request sources provided with the AVR microcontroller The AVR 8-bits microcontroller provides both internal and external interrupt sources. The internal interrupts are associated with the microcontroller's peripherals which are the Timer/Counter, Analog Comparator, etc. The external interrupts are triggered via external pins. When an Interrupt is triggered, the CPU will execute its service routine whose starting address is defined in the Interrupt vector table. On ATmega32/ATmega32A microcontroller there are four (4) external interrupts: The RESET interrupt - Triggered from pin 9 (executed like an interrupt but does not operate as an interrupt because RETI instruction cannot be used in RESET Interrupt service routine. External Interrupt 0 (INT0) - Triggered from pin 16. External Interrupt 1 (INT1) - Triggered from pin 17. External Interrupt 2 (INT2) - Triggered from pin 3. 53

51 Location of External Interrupt pins in ATmega32/ATmega32A 54

52 Writing Assembly Codes Utilizing the Interrupt Feature The Global Interrupt bit in the General Interrupt Control Register (GICR), the I bit, in the microcontroller's status register (SREG) MUST also be enabled by using the SEI instruction. The stack MUST be initialized (Normally at the beginning of the Main Program). When an interrupt is being service the microcontroller needs to store critical information on the stack. The Triggering Condition (in MCUCR for INT0 and INT1 and in MCUSCR for INT2) must be specifically set to suit hardware wiring configuration of the interrupt pin. Enable internal pull-up resistor if external pull-up resistor is not wired for active low interrupt input. The Interrupt Service Routine (ISR) MUST end with the RETI instruction, which indicates the end of the ISR. The microcontroller needs to know when it reaches the end of the ISR so it can return to its previous task. RETI will also set I bit is so that Global interrupt is enabled because I bit is cleared when CPU service any interrupt. 55

53 Writing C Codes Utilizing the Interrupt Feature The Global Interrupt bit, the I bit, in the microcontroller's status register (SREG) MUST also be enabled by using the sei() function. The stack NEED NOT be initialized (C compiler initialised stack by default). NEED NOT store critical information on the stack when an interrupt is being service the microcontroller needs to (C compiler does this by default). The Triggering Condition (in MCUCR for INT0 and INT1 and in MCUSCR for INT2) must be specifically set to suit hardware wiring configuration of the interrupt pin. Switch ON internal pull-up resistor if external pull-up resistor is not wired for active low interrupt input. NEED NOT end The Interrupt Service Routine (ISR) the RETI instruction (C compiler does this by default). 56

54 The ATMEga32/ATMEga32A External Interrupts Pins The INT2, INT1 and INT3 can be programmed to generate external interrupt for the ATmega32 The interrupts can detect four different types of pin changes: 1. pin goes low 2. any logical change in pin 3. falling edge (pin goes from high to low) 4. rising edge (pin goes from low to high) these interrupts are controlled by the following registers. 1. GICR 2. MCUCR (INT1 and INT2) 3. MCUCSR (INT2 only) 57

55 GICR To enable INTn we need to set the INTn bit of the GICR register. 58

56 MCUCR and MCUCSR To set detection (interrupt sense control) of pin changes we need to set the MCUCR (for INT1 and INT0) or MCUCSR (for INT1) ICS2 Description 0 A falling edge on INT2 activates the interrupt 1 A rising edge on INT2 activates the interrupt 59

57 General Interrupt Flag Register (GIFR) INTF1: When 1 on this bit trigger INT1 Interrupt when INT1 bit of GICR and I bit of SREG is one. INTF0: When 1 on this bit trigger INT0 Interrupt when INT0 bit of GICR and I bit of SREG is one. INTF2: When 1 on this bit trigger INT2 Interrupt when INT2 bit of GICR and I bit of SREG is one. 60

58 Example C/C++ codes that initialised External Interrupt INT0 and INT1 only /*The codes to Initialise Stack by default will be generated by the C/C++ compiler. The following statements will only set DDRD2, PD2, INT0 and ISC01, and Clear ISC00. Other bits in respective registers are untouched so setting of other interrupts are not changed. DDRD=DDRD (~(1<<PD2)); PORTD=PORTD (~(1<<PD2)); GICR=GICR 1<<INT0; MCUCR = MCUCR 1<<ISC01; MCUCR = MCUCR&((1<<ISC00)^0xff); /*The following statements will only set DDRD3, PD3, INT1, ISC01 and ISC00. Other bits in respective registers are untouched so setting of other interrupts are not changed.*/ DDRD=DDRD ((1<<PD3)^0xff); //Using Ex-or to NOT (1<<PD3) PORTD=PORTD ((1<<PD3)^0xff); GICR=GICR 1<<INT1; MCUCR = MCUCR 1<<ISC11 1<<ISC10; 61

59 #include <avr/io.h> #include <avr/interrupt.h> ISR(INT0_vect) { PORTB =~PORTB; } void initinterrupt(void) { cli(); GICR=0x40; MCUCR=0x03; sei(); } C Interrupt Sample int main(void) { initinterrupt(); DDRB=0xff; PORTB=0x55; while(1) { /*If interrupt INT0 is triggered, here PORTB will be complemented in background when INT0 is serviced*/ } } ISMAIL FKE UTM 2017 ISMAIL FKE UTM