ILI9342C. a-si TFT LCD Single Chip Driver 320RGBx240 Resolution and 262K color. Datasheet

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a-si TFT LCD Single Chip Driver Datasheet Version: V101 Document No.: _DTS_V101_20111214 ILI TECHNOLOGY CORP. 8F, No.

1 a-si TFT LCD Single Chip Driver Datasheet Version: V101 Document No.: _DTS_V101_ ILI TECHNOLOGY CORP. 8F, No. 38, Taiyuan St., Jhubei City, Hsinchu Country 302 Taiwan R.O.C. Tel ; Fax

2 Table of Contents Section Page 1. Introduction Features Block Diagram Pin Descriptions Pad Arrangement and Coordination Block Function Description Function Description MCU interfaces MCU interface selection Ⅰ Series Parallel Interface Write Cycle Sequence Read Cycle Sequence Ⅱ Parallel Interface Write Cycle Sequence Read Cycle Sequence Serial Interface Write Cycle Sequence Read Cycle Sequence Data Transfer Break and Recovery Data Transfer Pause Serial Interface Pause (3_wire) Parallel Interface Pause Data Transfer Mode Data Transfer Method Data Transfer Method RGB Interface RGB Interface Selection RGB Interface Timing VSYNC Interface Color Depth Conversion Look Up Table Display Data RAM (DDRAM) Display Data Format line Serial Interface line Serial Interface bit Parallel MCU Interface bit Parallel MCU Interface bit Parallel MCU Interface Page 2 of 235 Version: 100

3 bit Parallel MCU Interface bit Parallel RGB Interface bit Parallel RGB Interface bit Parallel RGB Interface Command Command List Description of Level 1 Command NOP (00h) Software Reset (01h) Read display identification information (04h) Read Display (09h) Read Display Power Mode (0Ah) Read Display MADCTL (0Bh) Read Display Pixel Format (0Ch) Read Display Image Format (0Dh) Read Display Signal Mode (0Eh) Read Display Self-Diagnostic Result (0Fh) Enter Sleep Mode (10h) Sleep Out (11h) Partial Mode ON (12h) Normal Display Mode ON (13h) Display Inversion OFF (20h) Display Inversion ON (21h) Gamma Set (26h) Display OFF (28h) Display ON (29h) Column Address Set (2Ah) Page Address Set (2Bh) Memory Write (2Ch) Color Set (2Dh) Memory Read (2Eh) Partial Area (30h) Vertical Scrolling Definition (33h) Tearing Effect Line OFF (34h) Tearing Effect Line ON (35h) Memory Access Control (36h) Vertical Scrolling Start Address (37h) Idle Mode OFF (38h) Idle Mode ON (39h) Page 3 of 235 Version: 100

4 COLMOD: Pixel Format Set (3Ah) Set_Tear_Scanline (44h) Get_Scanline (45h) Write Display Brightness (51h) Read Display Brightness (52h) Write CTRL Display (53h) Read CTRL Display (54h) Write Content Adaptive Brightness Control (55h) Read Content Adaptive Brightness Control (56h) Write CABC Minimum Brightness (5Eh) Read CABC Minimum Brightness (5Fh) Read Automatic Brightness Control Self-Diagnostic Result (68h) Read ID1 (DAh) Read ID2 (DBh) Read ID3 (DCh) Description of Level 2 Command RGB Interface Signal Control (B0h) Frame Rate Control (In Normal Mode/Full Colors) (B1h) Frame Rate Control (In Idle Mode/8 colors) (B2h) Frame Rate control (In Partial Mode/Full Colors) (B3h) Display Inversion Control (B4h) Blanking Porch Control (B5h) Display Function Control (B6h) Entry Mode Set (B7h) Backlight Control 1 (B8h) Backlight Control 2 (B9h) Backlight Control 3 (BAh) Backlight Control 4 (BBh) Backlight Control 5 (BCh) Backlight Control 6 (BDh) Backlight Control 7 (BEh) Power Control 1 (C0h) Power Control 2 (C1h) Power Control 3 (For Normal Mode) (C2h) Power Control 4 (For Idle Mode) (C3h) Power Control 5 (For Partial Mode) (C4h) VCOM Control 1(C5h) Get GPIO0~7 (C6h) Set GPIO0~7 (C7h) Page 4 of 235 Version: 100

5 Set EXTC (C8h) NV Memory Write (D0h) NV Memory Protection Key (D1h) NV Memory Read (D2h) Read ID4 (D3h) Get External Register for SPI (D9h) Positive Gamma Correction (E0h) Negative Gamma Correction (E1h) Digital Gamma Control 1 (E2h) Digital Gamma Control 2(E3h) Interface Control (F6h) Display Data RAM Configuration Memory to Display Address Mapping Normal Display ON or Partial Mode ON, Vertical Scroll Mode OFF Vertical Scroll Mode Vertical Scroll Example Case1: TFA+VSA+BFA < Case2: TFA+VSA+BFA = 240 (Rolling Scrolling) MCU to memory write/read direction Tearing Effect Output Tearing Effect Line Modes Tearing Effect Line Timings Sleep Out Command and Self-Diagnostic Functions of the Display Module Register loading Detection Functionality Detection Power ON/OFF Sequence Case 1 RESX line is held High or Unstable by Host at Power ON Case 2 RESX line is held Low by Host at Power ON Uncontrolled Power Off Power Level Definition Power Levels Power Flow Chart Gamma Curves Selection Gamma Default Values Gamma Curves Gamma Curve 1 (GC0), applies the function y=x Gamma Curve 2 (GC1), applies the function y=x Gamma Curve 3 (GC2), applies the function y=x Page 5 of 235 Version: 100

6 Gamma Curve 4 (GC3), applies the function y=x Reset Registers Output Pins, I/O Pins Input Pins Reset Timing Configuration of Power Supply Circuit NV Memory Programming Flow Electrical Characteristics Absolute Maximum Ratings DC Characteristics General DC Characteristics AC Characteristics Display Parallel 18/16/9/8-bit Interface Timing Characteristics (8080-Ⅰ system) Display Parallel 18/16/9/8-bit Interface Timing Characteristics(8080-Ⅱ system) Display Serial Interface Timing Characteristics (3-line SPI system) Display Serial Interface Timing Characteristics (4-line SPI system) Parallel 18/16/6-bit RGB Interface Timing Characteristics Revision History Page 6 of 235 Version: 100

7 1. Introduction a-si TFT LCD Single Chip Driver is a 262,144-color single-chip SOC driver for a-tft liquid crystal display with resolution of 320RGBx240 dots, comprising a 960-channel source driver, a 240-channel gate driver, 172,800 bytes GRAM for graphic display data of 320RGBx240 dots, and power supply circuit. supports parallel 8-/9-/16-/18-bit data bus MCU interface, 6-/16-/18-bit data bus RGB interface and 3-/4-line serial peripheral interface (SPI). The moving picture area can be specified in internal GRAM by window address function. The specified window area can be updated selectively, so that moving picture can be displayed simultaneously independent of still picture area. supports full color, 8-color display mode and sleep mode for precise power control by software and these features make the an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, MP3 and PMP where long battery life is a major concern. 2. Features Display resolution: [320xRGB](H) x 240(V) Output: 960 source outputs 240 gate outputs Common electrode output (VCOM) a-tft LCD driver with on-chip full display RAM: 172,800 bytes System Interface 8-bits, 9-bits, 16-bits, 18-bits interface with 8080-Ⅰ/8080-Ⅱ series MCU 6-bits, 16-bits, 18-bits RGB interface with graphic controller 3-line / 4-line serial interface Display mode: Full color mode (Idle mode OFF): 262K-color (selectable color depth mode by software) Reduce color mode (Idle mode ON): 8-color Power saving mode: Sleep mode On chip functions: VCOM generator and adjustment Timing generator Oscillator DC/DC converter Dot/Column inversion 4 preset Gamma curves with separate RGB Gamma correction Dynamic backlight control MTP : 8-bits for ID1, ID2, ID3 MADCTL (MX/MY/MV/RGB/REV) 7-bits for VCOM adjustment Low -power consumption architecture Low operating power supplies: Page 7 of 235 Version: 100

8 IOVCC = 1.65V ~ 2.8V (logic) VCI = 2.6V ~ 3.3V (analog) LCD Voltage drive: Source/VCOM power supply voltage DDVDH - GND = 4.5V ~ 6.0V DDVDL - GND = -4.5V ~ -6.0V Gate driver output voltage VGH - GND = 10.0V ~ 20.0V VGL - GND = -5.0V ~ -15.0V VGH - VGL 32.0V VCOM driver output voltage VCOM = -0.4 ~ -2.0 V Operate temperature range: -30 to 70 a-si TFT LCD storage capacitor : Cst on Common structure only Page 8 of 235 Version: 100

9 3. Block Diagram IOVCC IM[3:0] RESX 4 8/9/16/18-bit MCU I/F Index Register (IR) CSX WRX RDX D/CX D[17:0] TE SDA 18 3/4 Serial I/F 18 8 Control Register (CR) Address Counter (AC) LCD Source Driver S960 ~ S1 HSYNC VSYNC DOTCLK 6/16/18-bit RGB I/F 18 Graphics Operation 18 V63 ~ V0 DE 18 Read Latch 18 Write Latch 18 Grayscale Reference Voltage VREG1OUT VREG2OUT DUMMY Graphics RAM (GRAM) PWM_OUT LED Controller CABC Block VCORE Regulator RC-OSC. Timing Controller LCD Gate Driver G240 ~ G1 VCI AGND DGND Charge-pump Power Circuit VCOM Generator VCOM C11P C11N DDVDH C12P C12N C21P C21N C22P C22N VGH VGL C41P C41N DDVDL Page 9 of 235 Version: 100

10 4. Pin Descriptions a-si TFT LCD Single Chip Driver Power Supply Pins Pin Name I/O Type Descriptions IOVCC I P Low voltage power supply for interface logic circuits (1.65 ~ 2.8 V) VCI I Analog Power High voltage power supply for analog circuit blocks (2.6 ~ 3.3 V) VCORE O Digital Power Regulated Low voltage level for interface circuits DGND AGND P P Power supply Power supply - DGND for the digital side: DGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. - AGND for the analog side: AGND = 0V. In case of COG, connect to GND on the FPC to prevent noise. Test Pads Pin Name I/O Type Descriptions TEST_EN TEST_OSC I DGND TEST pin input TESTO1~O2 I/O Open TEST pin TEST0~8 I DGND TEST pin DUMMYR1 DUMMYR2 DUMMYR3 DUMMYR4 - Open DUMMY - Open GPIO0~7 I/O - Contact resistance measurement pad. In normal operation, leave this unconnected. These pads are at DGND level. When measuring an ohm resistance of the contact, do not apply any power. Input pads used only for test purpose at IC-side. During normal operation, leave these pads open. Standard input/output pin As for GPIO0~7 to terminal, setting of an input and output direction is possible Page 10 of 235 Version: 100

11 Interface Logic Signals Pin Name I/O Type Descriptions - Select the MCU interface mode IM[3:0] RESX CSX D/CX (SCL) RDX WRX (D/CX) I I I I I I (IOVCC/GND) MCU (IOVCC/GND) MCU (IOVCC/GND) MCU (IOVCC/GND) MCU (IOVCC/GND) MCU (IOVCC/GND) IM3 IM2 IM1 IM0 MCU-Interface Mode MCU 8-bit bus interface Ⅰ 80 MCU 16-bit bus interface Ⅰ 80 MCU 9-bit bus interface Ⅰ 80 MCU 18-bit bus interface Ⅰ 3-wire 9-bit data serial interface Ⅰ 4-wire 8-bit data serial interface Ⅰ 80 MCU 16-bit bus interface Ⅱ 80 MCU 8-bit bus interface Ⅱ 80 MCU 18-bit bus interface Ⅱ 80 MCU 9-bit bus interface Ⅱ DB Pin in use Register/Content Page 11 of 235 Version: 100 D[7:0] D[7:0] D[7:0] D[7:0] SDA: In/OUT SDA: In/OUT D[8:1] D[17:10] D[8:1] D[17:10] MPU Parallel interface bus and serial interface select If use RGB Interface must select serial interface. * : Fix this pin at IOVCC or GND. This signal will reset the device and must be applied to properly initialize the chip. Signal is active low. RESX1 is equal to RESX. GRAM D[7:0] D[15:0] D[8:0] D[17:0] D[17:10] D[8:1] D[17:10], D[17:0] D[17:9] Chip select input pin ( Low enable). This pin can be permanently fixed Low in MPU interface mode only. CSX1 is equal to CSX. * note1,2 This pin is used to select Data or Command in the parallel interface. When D/CX = 1, data is selected. When D/CX = 0, command is selected. This pin is used serial interface clock in 3-wire 9-bit / 4-wire 8-bit serial data interface. If not used, this pin should be connected to IOVCC or GND. DCX_SCL1 is equal to D/CX(SCL) Ⅰ/8080-Ⅱ system (RDX): Serves as a read signal and MCU read data at the rising edge. Fix to IOVCC or GND level when not in use Ⅰ/8080-Ⅱ system (WRX): Serves as a write signal and writes data at the rising edge. 4-line system (D/CX): Serves as command or parameter select. Fix to IOVCC or GND level when not in use.

12 D[17:0] SDA I/O I/O MCU (IOVCC/GND) MCU (IOVCC/GND) 18-bit parallel bi-directional data bus for MCU system and RGB interface mode Fix to GND level when not in use When IM[3] : High, Serial in/out signal. The data is applied on the rising edge of the SCL signal. If not used, fix this pin at IOVCC or GND. Tearing effect output pin to synchronize MPU to frame writing, TE O MCU (IOVCC/GND) activated by S/W command. When this pin is not activated, this pin is low. If not used, open this pin. TE1 is equal to TE. DOTCLK VSYNC HSYNC DE I I I I MCU (IOVCC/GND) MCU (IOVCC/GND) MCU (IOVCC/GND) MCU (IOVCC/GND) Dot clock signal for RGB interface operation. Fix to IOVCC or GND level when not in use. Frame synchronizing signal for RGB interface operation. Fix to IOVCC or GND level when not in use. Line synchronizing signal for RGB interface operation. Fix to IOVCC or GND level when not in use. Data enable signal for RGB interface operation. Fix to IOVCC or GND level when not in use. Note. 1. If CSX is connected to GND in Parallel interface mode, there will be no abnormal visible effect to the display module. Also there will be no restriction on using the Parallel Read/Write protocols, Power On/Off Sequences or other functions. Furthermore there will be no influence to the Power Consumption of the display module. 2. When CSX= 1, there is no influence to the parallel and serial interface. Page 12 of 235 Version: 100

13 LCD Driver Input/Output Pins Pin Name I/O Type Descriptions S960~S1 O Source G240~G1 O Gate Source output signals.. Leave the pin to open when not in use. Gate output signals. Leave the pin to open when not in use. DDVDH O Stabilizing capacitor Power supply for the source driver and VCOM driver DDVDL O Stabilizing capacitor Power supply for the source driver and VCOM driver VGH O Power VGL O Stabilizing capacitor Power supply for the gate driver. Adjust the VGH level with the BT[3:0] bits. Connect this pad with a stabilizing capacitor. Power supply for the gate driver. Adjust the VGL level with the BT[3:0] bits. Connect this pad with a stabilizing capacitor. C11P, C11N P Step-up capacitor Connect the charge-pumping capacitor on C11P/C11N for generating DDVDH level. C12P, C12N P Step-up capacitor - Connect the charge-pumping capacitor on C12P/C12N for generating DDVDH 3X level. C21P, C21N P Step-up capacitor Connect the charge-pumping capacitor on C21P/C21N for generating VGH, VGL level. C22P, C22N P Step-up capacitor Connect the charge-pumping capacitor on C22P/C22N for generating DDVDL 3X level. C41P, C41N P Step-up capacitor Connect the charge-pumping capacitor for generating DDVDL level. VREG1OUT O Power VREG2OUT O Power VGS I Power VCOM O Power - Internal generated stable power for source driver unit. - The voltage level can be set by VRH1[4:0]. - VREG1OUT is a positive grayscale reference voltage of source driver. - VREG1OUT =3.6~5.5V - Internal generated stable power for source driver unit. - The voltage level can be set by VRH2[4:0]. - VREG2OUT is a negative grayscale reference voltage of source driver. - VREG2OUT =-5.5~-3.6V Low reference voltage for grayscale voltage generator. Connect an external resistor or to system ground. - The power supply of common voltage in DC VCOM driving. - The voltage range is set between -0.4V to -2.0V. Page 13 of 235 Version: 100

14 PWM_OUT O Output pin for PWM (Pulse Width Modulation) signal of LED driving. If not used, open this pad. Pwm_OUT1 is equal to PWM_OUT. Page 14 of 235 Version: 100

15 Liquid crystal power supply specifications Table No. Item Description 1 TFT Source Driver 960 pins (320 x RGB) 2 TFT Gate Driver 240 pins 3 TFT Display s Capacitor Structure Cst structure only (Cs on Common) S1 ~ S960 V0 ~ V63 grayscales 4 Liquid Crystal Drive Output G1 ~ G240 VGH - VGL VCOM -0.4~-2.0V 5 Input Voltage IOVCC 1.65V ~2.80V VCI 2.60V ~ 3.30V DDVDH 4.5V ~ 6.0V DDVDL -6.0V ~ -4.5V 6 Liquid Crystal Drive Voltages VGH 10.0V ~ 20.0V VGL -5.0V ~ -15.0V VGH - VGL Max. 32.0V DDVDH VCI1 x2 7 Internal Step-up Circuits DDVDL -(VCI1-VCL) VGH VCI1 x4, x5, x6 VGL VCI1 x-3, x-4, x-5 Note: VCI1 is an internal reference voltage for the step-up circuit1. Page 15 of 235 Version: 100

16 5. Pad Arrangement and Coordination Page 16 of 235 Version: 100

17 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 1 VCOM IM DUMMY DB VCOM IOVCC DUMMY DB VCOM IM DUMMY DB VCOM DGND DUMMY DB DUMMYR IM DUMMY DB DUMMYR IOVCC DGND DB VCORE IM DGND DB VCORE DGND DGND DB VCORE DGND DGND DB VCORE TEST_EN DUMMY DB VCORE TESTOSC DUMMY DB VCORE TEST DUMMY DB VCORE DUMMY DGND DGND VCORE DUMMY DUMMY DB AGND DGND DUMMY DB AGND DUMMY DUMMY DB AGND IOVCC DGND DB AGND TEST DUMMY DB AGND DUMMY DUMMY DB AGND TEST DUMMY DB AGND DUMMY DGND DB AGND TEST DUMMY DB AGND DUMMY DUMMY DB AGND TEST DUMMY DB AGND DUMMY DGND DB AGND TEST TE DGND DGND DUMMY TE DB DGND TEST DGND DB DGND DUMMY DUMMY DB DGND TEST IOVCC DB DGND DUMMY DUMMY DB DGND TEST DGND DB DGND DGND RESX DB DGND DUMMY DUMMY DB DGND IOVCC DUMMY DB DGND CSX DUMMY DB DGND DCX_SCL DUMMY DB DGND SDA DUMMY DB IOVCC DUMMY DUMMY IOVCC IOVCC DUMMY DUMMY DUMMY IOVCC PWM_OUT DUMMY DGND IOVCC PWM_OUT IOVCC DGND IOVCC VSYNC IOVCC DGND IOVCC HSYNC IOVCC DGND IOVCC DOTCLK IOVCC DUMMY IOVCC DE RDX DUMMY IOVCC DGND WRX DUMMY IOVCC DUMMY DCX_SCL RESX DUMMY DUMMY CSX IOVCC DGND DUMMY DGND IOVCC Page 17 of 235 Version: 100

18 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 201 IOVCC DUMMY VGL C11P IOVCC DGND VGL C11P VCI VREG2_OUT VGL C11P VCI VREG2_OUT VGL C11P VCI VGS VGL C11P VCI DUMMY DUMMY C11P TE DUMMY DUMMY DUMMY TE DGND DUMMY DUMMY PWM_OUT DGND DUMMY DUMMY PWM_OUT DGND DUMMY VCI TESTO DGND DDVDH VCI DGND DGND DDVDH VCI GPIO AGND DDVDH VCI GPIO AGND DDVDH VCI GPIO AGND DDVDH VCI GPIO AGND DDVDH DUMMY DUMMY VGS C41N C12N TESTO DUMMY C41N C12N GPIO DUMMY C41N C12N GPIO DUMMY C41N C12N GPIO DUMMY C41N C12N GPIO DUMMY C41N C12N GPIO DUMMY C41N C12N GPIO DUMMY C41N C12N GPIO DUMMY C41N C12P GPIO DUMMY C41N C12P GPIO DUMMY C41P C12P GPIO DUMMY C41P C12P GPIO DUMMY C41P C12P GPIO DUMMY C41P C12P DUMMY VREG1_OUT C41P C12P DUMMY VREG1_OUT C41P C12P DUMMY DUMMY C41P C21N DUMMY DUMMY C41P C21N DUMMY DUMMY C41P C21N DUMMY DUMMY C41P C21N DUMMY DUMMY C11N C21N DUMMY DDVDL C11N C21N DUMMY DDVDL C11N C21N DUMMY DDVDL C11N C21N DGND DDVDL C11N C21N DGND DDVDL C11N C21N DGND DDVDL C11N C21N DGND VGH C11N C21N DGND VGH C11N C21P DGND VGH C11N C21P DUMMY VGH C11P C21P DUMMY VGH C11P C21P DGND VGH C11P C21P DUMMY VGL C11P C21P Page 18 of 235 Version: 100

19 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 401 C21P G G G C21P G G G C21P G G G C21P G G G C21P G G G C21P G G G C22N G G G C22N G G G C22N G G DUMMY C22N G G DUMMY C22N G G DUMMY C22N G G DUMMY C22N G G S C22N G G S C22N G G S C22N G G S C22N G G S C22N G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S C22P G G S DUMMYR G G S DUMMYR G G S VCOM G G S VCOM G G S VCOM G G S VCOM G G S DUMMY G G S DUMMY G G S G G G S G G G S G G G S G G G S G G G S G G G S G G G S G G G S G G G S G G G S G G G S G G G S Page 19 of 235 Version: 100

20 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 601 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 20 of 235 Version: 100

21 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 801 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 21 of 235 Version: 100

22 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 1001 S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S DUMMY S S S Page 22 of 235 Version: 100

23 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 1201 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 23 of 235 Version: 100

24 No. Pad name X Y No. Pad name X Y No. Pad name X Y No. Pad name X Y 1401 S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S S G S S DUMMY G S S DUMMY G S S DUMMY G S S DUMMY G Page 24 of 235 Version: 100

25 No. Pad name X Y No. Pad name X Y 1601 G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G DUMMY G DUMMY G G G G G G G G G G G G G G G G G G G G Alignment mark X Y 1643 G A G A G G G G G G Page 25 of 235 Version: 100

ILI9342. a-si TFT LCD Single Chip Driver 320RGBx240 Resolution and 262K color. Specification Preliminary

ILI9342. a-si TFT LCD Single Chip Driver 320RGBx240 Resolution and 262K color. Specification Preliminary a-si TFT LCD Single Chip Driver Specification Preliminary Version: V007 Document No.: _DS_V007.pdf ILI TECHNOLOGY CORP. 8F, No. 38, Taiyuan St., Jhubei City, Hsinchu Country 302 Taiwan R.O.C. Tel.886-3-5600099;