ILI9331. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K Color. Datasheet

Transcription

1 a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K Color Datasheet Version: V011 Document No: DS_V011pdf ILI TECHNOLOGY CORP 8F, No38, Taiyuan St, Jhubei City, Hsinchu County 302, Taiwan, ROC Tel ; Fax

2 Table of Contents Section Page 1 Introduction 7 2 Features 8 3 Block Diagram 10 4 Pin Descriptions 11 5 Pad Arrangement and Coordination 15 6 Block Description 25 7 System Interface Interface Specifications Input Interfaces i80/18-bit System Interface i80/16-bit System Interface i80/9-bit System Interface i80/8-bit System Interface Serial Peripheral Interface (SPI) VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface47 76 MDDI (Mobile Display Digital Interface) MDDI Specifications MDDI Link Protocol (Packets Supported by the ) MDDI Instruction Setting Interface Timing CABC (Content Adaptive Brightness Control) 64 8 Register Descriptions Registers Access Instruction Descriptions Index (IR) ID code (R00h) Driver Output Control (R01h) LCD Driving Wave Control (R02h) Entry Mode (R03h) Display Control 1 (R07h) 75 Page 2 of 135 Version: 011

3 827 Display Control 2 (R08h) Display Control 3 (R09h) Display Control 4 (R0Ah) RGB Display Interface Control 1 (R0Ch) Frame Marker Position (R0Dh) RGB Display Interface Control 2 (R0Fh) Power Control 1 (R10h) Power Control 2 (R11h) Power Control 3 (R12h) Power Control 4 (R13h) GRAM Horizontal/Vertical Address Set (R20h, R21h) Write Data to GRAM (R22h) Read Data from GRAM (R22h) Power Control 7 (R29h) Frame Rate and Color Control (R2Bh) Gamma Control (R30h ~ R3Dh) Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) Gate Scan Control (R60h, R61h, R6Ah) Partial Image 1 Display Position (R80h) Partial Image 1 RAM Start/End Address (R81h, R82h) Partial Image 2 Display Position (R83h) Partial Image 2 RAM Start/End Address (R84h, R85h) Panel Interface Control 1 (R90h) Panel Interface Control 2 (R92h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) OTP VCM Programming Control (RA1h) OTP VCM Status and Enable (RA2h) OTP Programming ID Key (RA5h) Write Display Brightness Value (RB1h) Read Display Brightness Value (RB2h) Write CTRL Display Value (RB3h) Read CTRL Display Value (RB4h) Write Content Adaptive Brightness Control Value (RB5h) Read Content Adaptive Brightness Control Value (RB6h) Write CABC Minimum Brightness (RBEh) Read CABC Minimum Brightness (RBFh) CABC Control 1 (RC8h) CABC Control 2 (RC9h) 100 Page 3 of 135 Version: 011

4 8246 CABC Control 3 (RCAh) CABC Control 4 (RCBh) CABC Control 5 (RCCh) CABC Control 6 (RCDh) CABC Control 7 (RCEh) OTP Programming Flow GRAM Address Map & Read/Write Window Address Function Gamma Correction Application Configuration of Power Supply Circuit Display ON/OFF Sequence Standby and Sleep Mode Power Supply Configuration Voltage Generation Applied Voltage to the TFT panel Partial Display Function Electrical Characteristics Absolute Maximum Ratings DC Characteristics Reset Timing Characteristics AC Characteristics i80-system Interface Timing Characteristics Serial Data Transfer Interface Timing Characteristics RGB Interface Timing Characteristics Revision History 134 Page 4 of 135 Version: 011

5 Figures FIGURE1 SYSTEM INTERFACE AND RGB INTERFACE CONNECTION 28 FIGURE2 18-BIT SYSTEM INTERFACE DATA FORMAT 29 FIGURE3 16-BIT SYSTEM INTERFACE DATA FORMAT 30 FIGURE4 9-BIT SYSTEM INTERFACE DATA FORMAT 31 FIGURE5 8-BIT SYSTEM INTERFACE DATA FORMAT 32 FIGURE 6 DATA FORMAT OF SPI INTERFACE 34 FIGURE7 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) 35 FIGURE8 DATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI), TRI= 1 AND DFM= 10 ) 36 FIGURE9 DATA TRANSMISSION THROUGH VSYNC INTERFACE) 37 FIGURE10 MOVING PICTURE DATA TRANSMISSION THROUGH VSYNC INTERFACE 37 FIGURE11 OPERATION THROUGH VSYNC INTERFACE 38 FIGURE12 TRANSITION FLOW BETWEEN VSYNC AND INTERNAL CLOCK OPERATION MODES 40 FIGURE13 RGB INTERFACE DATA FORMAT 41 FIGURE14 GRAM ACCESS AREA BY RGB INTERFACE 42 FIGURE15 TIMING CHART OF SIGNALS IN 18-/16-BIT RGB INTERFACE MODE 43 FIGURE16 TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MODE 44 FIGURE17 EXAMPLE OF UPDATE THE STILL AND MOVING PICTURE 45 FIGURE18 INTERNAL CLOCK OPERATION/RGB INTERFACE MODE SWITCHING 48 FIGURE19 GRAM ACCESS BETWEEN SYSTEM INTERFACE AND RGB INTERFACE 49 FIGURE20 MDDI ARCHITECTURE 50 FIGURE21 RELATIONSHIP BETWEEN RGB I/F SIGNALS AND LCD DRIVING SIGNALS FOR PANEL 63 FIGURE22 REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 65 FIGURE23 REGISTER SETTING WITH I80 SYSTEM INTERFACE 66 FIGURE 24 REGISTER READ/WRITE TIMING OF I80 SYSTEM INTERFACE 67 FIGURE25 GRAM ACCESS DIRECTION SETTING 73 FIGURE26 16-BIT MPU SYSTEM INTERFACE DATA FORMAT 74 FIGURE27 8-BIT MPU SYSTEM INTERFACE DATA FORMAT 75 FIGURE 28 DATA READ FROM GRAM THROUGH READ DATA REGISTER IN 18-/16-/9-/8-BIT INTERFACE MODE 85 FIGURE 29 GRAM DATA READ BACK FLOW CHART 86 FIGURE 30 GRAM ACCESS RANGE CONFIGURATION 89 FIGURE31 GRAM READ/WRITE TIMING OF I80-SYSTEM INTERFACE 107 FIGURE32 I80-SYSTEM INTERFACE WITH 18-/16-/9-BIT DATA BUS (SS= 0, BGR= 0 ) 109 FIGURE33 I80-SYSTEM INTERFACE WITH 8-BIT DATA BUS (SS= 0, BGR= 0 ) 110 FIGURE 34 I80-SYSTEM INTERFACE WITH 18-/9-BIT DATA BUS (SS= 1, BGR= 1 ) 111 FIGURE 35 GRAM ACCESS WINDOW MAP 112 FIGURE 36 GRAYSCALE VOLTAGE GENERATION 113 FIGURE 37 GRAYSCALE VOLTAGE ADJUSTMENT 114 FIGURE 38 GAMMA CURVE ADJUSTMENT 115 Page 5 of 135 Version: 011

6 FIGURE 39 EXAMPLE OF RMP(N)0~5 DEFINITION 117 FIGURE 40 RELATIONSHIP BETWEEN SOURCE OUTPUT AND VCOM 120 FIGURE 41 RELATIONSHIP BETWEEN GRAM DATA AND OUTPUT LEVEL 120 FIGURE 42 POWER SUPPLY CIRCUIT BLOCK 121 FIGURE 43 DISPLAY ON/OFF REGISTER SETTING SEQUENCE 123 FIGURE 44 STANY/SLEEP MODE REGISTER SETTING SEQUENCE 124 FIGURE 45 POWER SUPPLY ON/OFF SEQUENCE 125 FIGURE 46 VOLTAGE CONFIGURATION DIAGRAM 126 FIGURE 47 VOLTAGE OUTPUT TO TFT LCD PANEL 127 FIGURE 48 PARTIAL DISPLAY EXAMPLE 128 FIGURE 49 I80-SYSTEM BUS TIMING 131 FIGURE 50 SPI SYSTEM BUS TIMING 132 FIGURE51 RGB INTERFACE TIMING133 Page 6 of 135 Version: 011

7 1 Introduction a-si TFT LCD Single Chip Driver is a 262,144-color one-chip SoC driver for a-tft liquid crystal display with resolution of 240RGBx320 dots, comprising a 720-channel source driver, a 320-channel gate driver, 172,800 bytes RAM for graphic data of 240RGBx320 dots, and power supply circuit has five kinds of system interfaces which are i80-system MPU interface (8-/9-/16-/18-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [17:0]), serial data transfer interface (SPI), RGB 6-/16-/18-bit interface (DOTCLK, VSYNC, HSYNC, ENABLE, [17:0]) and MDDI In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 165V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LCD The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LCD driver for medium or small size portable products such as digital cellular phones, smart phone, PDA and PMP where long battery life is a major concern Page 7 of 135 Version: 011

8 2 Features a-si TFT LCD Single Chip Driver Single chip solution for a liquid crystal QVGA TFT LCD display 240RGBx320-dot resolution capable with real 262,144 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 720-channel source driver and 320-channel gate driver Internal 172,800 bytes graphic RAM CABC (Content Adaptive Brightness Control) System interfaces i80 system interface with 8-/ 9-/16-/18-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/16-/18-bit bus width (VSYNC, HSYNC, DOTCLK, ENABLE, [17:0]) VSYNC interface (System interface + VSYNC) MDDI (Mobile Display Digital Interface) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Bit operation function for facilitating graphics data processing Bit-unit write data mask function Pixel-unit logical/conditional write function Abundant functions for color display control γ-correction function enabling display in 262,144 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LCD panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVcc = 165V ~ 33 V (interface I/O) VCI = 25V ~ 33 V (analog) LCD Voltage drive: Source/VCOM power supply voltage DDVDH - GND = 45V ~ 60 VCL GND = -20V ~ -30V VCI VCL 60V Gate driver output voltage VGH - GND = 10V ~ 20V Page 8 of 135 Version: 011

9 VGL GND = -5V ~ -15V VGH VGL 30V VCOM driver output voltage VCOMH = (VCI+02)V ~ (DDVDH-02)V VCOML = (VCL+02)V ~ 0V VCOMH-VCOML 60V a-tft LCD storage capacitor: Cst only Page 9 of 135 Version: 011

10 3 Block Diagram IOVCC IM[3:0] nreset Index Register (IR) ncs nwr/scl n RS SDI SDO MPU I/F 18-bit 16-bit 9-bit 8-bit 18 7 Control Register (CR) Address Counter (AC) LCD Source Driver S[720:1] [17:0] SPI I/F HSYNC VSYNC DOTCLK ENABLE TEST1 TEST2 TEST3 TS[8:0] MDDI_DATA_N RGB I/F 18-bit 16-bit 6-bit VSYNC I/F MDDI Graphics Operation Read Latch Write Latch 18 V63 ~ 0 Grayscale Reference Voltage VREG1OUT VGS MDDI_DATA_P MDDI_STB_N MDDI_STB_P Graphics RAM (GRAM) DUMMY20~27 VCC VDDD GND LEDPWM Regulator Brightness control CABC Block RC-OSC Timing Controller LCD Gate Driver G[320:1] DUMMY1~15 VCI VCI1 Charge-pump Power Circuit VCOM Generator VCOM GND C11A C11B DDVDH C12A C12B C13A C13B VCL C21A C21B C22A C22B VGH VGL VCOMH VCOML Page 10 of 135 Version: 011

11 4 Pin Descriptions Pin Name I/O Type Descriptions Input Interface Select the MPU system interface mode IM3 IM2 IM1 IM0 MPU-Interface Mode Pin in use Setting invalid Setting invalid i80-system 16-bit interface [17:10], [8:1] i80-system 8-bit interface [17:10] IM3, IM2, IM1, IM0/ID I IOVcc ID Serial Peripheral Interface (SPI) SDI, SDO * Setting invalid MDDI Setting invalid i80-system 18-bit interface [17:0] i80-system 9-bit interface [17:9] 1 1 * * Setting invalid When the serial peripheral interface is selected, IM0 pin is used for the device code ID setting A chip select signal ncs I MPU IOVcc Low: the is selected and accessible High: the is not selected and not accessible Fix to the GND level when not in use A register select signal RS I MPU IOVcc Low: select an index or status register High: select a control register Fix to either IOVcc or GND level when not in use A write strobe signal and enables an operation to write data when the signal is low nwr/scl I MPU IOVcc Fix to either IOVcc or GND level when not in use SPI Mode: Synchronizing clock signal in SPI mode n I MPU IOVcc A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GND level when not in use nreset I MPU IOVcc A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SDI I MPU IOVcc SPI interface input pin The data is latched on the rising edge of the SCL signal SPI interface output pin SDO O MPU IOVcc The data is outputted on the falling edge of the SCL signal Let SDO as floating when not used An 18-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: [17:10] is used 9-bit I/F: [17:9] is used 16-bit I/F: [17:10] and [8:1] is used [17:0] I/O MPU IOVcc 18-bit I/F: [17:0] is used 18-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: [17:12] are used 16-bit RGB I/F: [17:13] and [11:1] are used 18-bit RGB I/F: [17:0] are used Unused pins must be fixed to GND level Page 11 of 135 Version: 011

12 Pin Name I/O Type Descriptions Data ENEABLE signal for RGB interface operation Low: Select (access enabled) ENABLE I MPU High: Not select (access inhibited) IOVcc The EPL bit inverts the polarity of the ENABLE signal Fix to either IOVcc or GND level when not in use DOTCLK I Dot clock signal for RGB interface operation Fix to the GND level when not in use MPU DPL = 0 : Input data on the rising edge of DOTCLK IOVcc DPL = 1 : Input data on the falling edge of DOTCLK VSYNC I Frame synchronizing signal for RGB interface operation Fix to the GND level when not in use MPU VSPL = 0 : Active low IOVcc VSPL = 1 : Active high HSYNC I Line synchronizing signal for RGB interface operation Fix to the GND level when not in use MPU HSPL = 0 : Active low IOVcc HSPL = 1 : Active high FMARK O Output a frame head pulse signal MPU The FMARK signal is used when writing RAM data in synchronization with frame Leave IOVcc the pin open when not in use MDDI data signal lines Data+ (MDDI_DATA_P) and data- (MDDI_DATA_M) are differential small swing MDDI_DATA_P MDDI signals Make the wiring as short as possible so that the COG resistance I/O MDDI_DATA_M becomes less 60 ohm The specifications of interface must be compliant with the MDDI specification NOTE: these pins are used the same pin in CPU mode MDDI strobe signal lines Stb+ (MDDI_STB_P) and Stb- (MDDI_STB_M) are differential small swing MDDI_STB_P MDDI signals Make the wiring as short as possible so that the COG resistance I MDDI_STB_M becomes less 100ohm The specifications of interface must be compliant with the MDDI specification NOTE: these pins are used the same pin in CPU mode MDDI_GNDDUM I GND When MDDI interface is selected, connect this pin to GND or leave it open NOTE: these pins are used the same pin in CPU mode LCD Driving signals S720~S1 O LCD Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS = 0, the data in the RAM address h00000 is output from S1 SS = 1, the data in the RAM address h00000 is output from S720 S1, S4, S7, display red (R), S2, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = 0) G320~G1 O LCD Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines VCOM O TFT common A supply voltage to the common electrode of TFT panel electrode VCOM is AC voltage alternating signal between the VCOMH and VCOML levels VCOMH O Stabilizing capacitor The high level of VCOM AC voltage Connect to a stabilizing capacitor VCOML O Stabilizing The low level of VCOM AC voltage Adjust the VCOML level with the VDV bits capacitor Connect to a stabilizing capacitor VGS I GND or Reference level for the grayscale voltage generating circuit The VGS level can be external changed by connecting to an external resistor resistor LEDPWM O IOVcc PWM signal output to control LED driver for LED brightness dimming Charge-pump and Regulator Circuit Page 12 of 135 Version: 011

13 Pin Name I/O Type Descriptions VCI I Power A supply voltage to the analog circuit Connect to an external power supply of 25 ~ supply 33V VCC I Power A supply voltage to the digital circuit Connect to an external power supply of 25 ~ supply 33V VCI1 O An internal reference voltage for the step-up circuit1 within the respective specification Stabilizing The amplitude between VCI and GND is determined by the VC[2:0] bits capacitor Make sure to set the VCI1 voltage so that the DDVDH, VGH and VGL voltages are set DDVDH O Stabilizing capacitor Power supply for the source driver and Vcom drive VGH O Stabilizing capacitor Power supply for the gate driver VGL O Stabilizing capacitor Power supply for the gate driver VCL O Stabilizing VCOML driver power supply capacitor VCL = 05 ~ VCI Place a stabilizing capacitor between GND C11A, C11B Step-up I/O C12A, C12B capacitor Capacitor connection pins for the step-up circuit 1 C13A, C13B Step-up C21A, C21B I/O capacitor C22A, C22B Capacitor connection pins for the step-up circuit 2 Output voltage generated from the reference voltage VREG1OUT I/O Stabilizing capacitor IOVCC I Power supply VDD O Power DGND I Power supply AGND I Power supply VGMMA1, 62 O - VGLDMY1~4 O Unused gate lines DUMMY3, 5~27,30, DUMMYR1,2, 28, The voltage level is set with the VRH bits VREG1OUT is (1) a source driver grayscale reference voltage, (2) VcomH level reference voltage, and (3) Vcom amplitude reference voltage Connect to a stabilizing capacitor VREG1OUT = 30 ~ (DDVDH 05)V Power Pads A supply voltage to the interface pins: IM[3:0], nreset, ncs, nwr, n, RS, [17:0], VSYNC, HSYNC, DOTCLK, ENABLE, SCL, SDI, SDO IOVcc = 165 ~ 33V In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise A supply voltage to the MDDI interface pins: MDDI_STB_M, MDDI_STB_P, MDDI_DATA_P and MDDI_DATA_M IOVcc = 25 ~ 33V In case of COG, connect to Vcc on the FPC if IOVcc=Vcc, to prevent noise Digital circuit power pad Connect these pins with the 1uF capacitor DGND for the digital side: DGND = 0V In case of COG, connect to GND on the FPC to prevent noise AGND for the analog side: AGND = 0V In case of COG, connect to GND on the FPC to prevent noise Test pad Leave these pins as open Connect unused gate lines to fix the level at VGL Test Pads Dummy pad Leave these pins as open Short circuited within the chip for COG contact resistance measurement DUMMYR pins are short circuited as below: DUMMYR1 and DUMMYR29 DUMMYR2 and DUMMYR28 IOVCCDUM O Connect unused interface and test pins to these pins on the glass to fix voltage Page 13 of 135 Version: 011

14 Pin Name I/O Type Descriptions AGNDDUM1~6 O - levels Leave open when not used DGNDDUM1~7 O - TESTO1~16 O Open Test pins Leave them open TEST1, 2, 3 I IOGND Test pins (internal pull low) Connect to GND or leave these pins as open TS0~8 I OPEN Test pins (internal pull low) Leave them open TSO O OPEN Test pins Leave it open or short to ground TEST_EN I OPEN Test pins Leave it open or short to ground Liquid crystal power supply specifications Table 1 No Item Description 1 TFT Source Driver 720 pins (240 x RGB) 2 TFT Gate Driver 320 pins 3 TFT Display s Capacitor Structure Cst structure only (Common VCOM) S1 ~ S720 V0 ~ V63 grayscales 4 Liquid Crystal Drive Output G1 ~ G320 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes 5 Input Voltage IOVcc 165 ~ 330V VCI 250 ~ 330V DDVDH 45V ~ 60V VGH 10V ~ 20V 6 Liquid Crystal Drive Voltages VGL -5V ~ -15V VCL -19V ~ -30V VGH - VGL Max 30V VCI - VCL Max 60V DDVDH VCI1 x2 7 Internal Step-up Circuits VGH VCI1 x4, x5, x6 VGL VCI1 x-3, x-4, x-5 VCL VCI1 x-1 Page 14 of 135 Version: 011

15 5 Pad Arrangement and Coordination Page 15 of 135 Version: 011

16 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1 DGNDDUM IOVCC VGS DUMMYR IOVCC AGND DUMMYR IOVCC AGND TESTO[1] IOVCC AGND TESTO[2] IOVCC AGND TESTO[3] IOVCC AGND TESTO[4] IOVCC AGND TESTO[5] IOVCC AGND TESTO[6] [8] / MDDI_GNDDUM AGND TESTO[7] [7] / MDDI_DATA_P VCOMH TESTO[8] [6] / MDDI_GNDDUM VCOMH LEDPWM TS[4] VCOMH LEDPWM TS[3] VCOMH TESTO[9] [5] / MDDI_GNDDUM VCOMH TESTO[10] [4] / MDDI_DATA_M VCOMH TESTO[11] [3] / MDDI_GNDDUM VCOM TESTO[12] TS[2] VCOM DGND TS[1] VCOM DGND [2] / MDDI_GNDDUM VCOM DGND [1] / MDDI_STB_P VCOM DGND [0] / MDDI_GNDDUM VCOM DGND TS[0] VCOML DGND TSO VCOML DGND DGNDDUM VCOML DGND ncs / MDDI_GNDDUM VCOML DGND RS / MDDI_STB_M VCOML DGND nwr/scl / MDDI_GNDDUM VCOML TESTO[13] n VCOML TESTO[14] nreset C11A DGNDDUM SDO C11A IM0/ID SDI C11A IM DGNDDUM C11A IM DUMMY C11A IM DUMMY C11B IOVCCDUM DUMMY C11B TESTO[15] DUMMY C11B TESTO[16] DUMMY C11B TEST DGNDDUM C11B TEST VCC C12B TEST VCC C12B DGNDDUM VCC C12B FMARK VCC C12B VSYNC VCC C12B HSYNC VCC C12A DOTCLK VDD C12A ENABLE VDD C12A TEST_EN VDD C12A [17] VDD C12A [16] VDD DDVDH [15] VDD DDVDH TS[8] VDD DDVDH TS[7] VDD DDVDH [14] DGND DDVDH [13] DGND DDVDH [12] DGND DDVDH TS[6] DGND DDVDH TS[5] DGND DDVDH [11] DGND DDVDH [10] DGND DUMMY [9] DGND VREG1OUT Page 16 of 135 Version: 011

17 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 181 DUMMY AGND G[71] DUMMY AGND G[73] AGNDDUM C21B G[75] AGNDDUM C21B G[77] VCI C21B G[79] VCI C21A G[81] VCI C21A G[83] VCI C21A G[85] VCI C22B G[87] VCI C22B G[89] VCI C22B G[91] VCI C22A G[93] VCI C22A G[95] VCI C22A G[97] VCI DUMMY G[99] VCI DUMMY G[101] VCI DUMMY G[103] VCI DUMMY G[105] VCI DUMMY G[107] VCI AGNDDUM G[109] VCI DUMMY G[111] AGNDDUM DUMMY G[113] VGH DUMMY G[115] VGH DUMMY G[117] VGH VGLDMY G[119] VGH G[1] G[121] VGH G[3] G[123] VGH G[5] G[125] AGNDDUM G[7] G[127] VGL G[9] G[129] VGL G[11] G[131] VGL G[13] G[133] VGL G[15] G[135] VGL G[17] G[137] VGL G[19] G[139] VGL G[21] G[141] VGL G[23] G[143] VGL G[25] G[145] VGL G[27] G[147] AGNDDUM G[29] G[149] VCL G[31] G[151] VCL G[33] G[153] VCL G[35] G[155] VCL G[37] G[157] C13B G[39] G[159] C13B G[41] G[161] C13B G[43] G[163] C13B G[45] G[165] C13A G[47] G[167] C13A G[49] G[169] C13A G[51] G[171] C13A G[53] G[173] AGND G[55] G[175] AGND G[57] G[177] AGND G[59] G[179] AGND G[61] G[181] AGND G[63] G[183] AGND G[65] G[185] AGND G[67] G[187] AGND G[69] G[189] Page 17 of 135 Version: 011

18 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 361 G[191] G[311] S[669] G[193] G[313] S[668] G[195] G[315] S[667] G[197] G[317] S[666] G[199] G[319] S[665] G[201] VGLDMY S[664] G[203] DUMMY S[663] G[205] DUMMY S[662] G[207] DUMMY S[661] G[209] S[720] S[660] G[211] S[719] S[659] G[213] S[718] S[658] G[215] S[717] S[657] G[217] S[716] S[656] G[219] S[715] S[655] G[221] S[714] S[654] G[223] S[713] S[653] G[225] S[712] S[652] G[227] S[711] S[651] G[229] S[710] S[650] G[231] S[709] S[649] G[233] S[708] S[648] G[235] S[707] S[647] G[237] S[706] S[646] G[239] S[705] S[645] G[241] S[704] S[644] G[243] S[703] S[643] G[245] S[702] S[642] G[247] S[701] S[641] G[249] S[700] S[640] G[251] S[699] S[639] G[253] S[698] S[638] G[255] S[697] S[637] G[257] S[696] S[636] G[259] S[695] S[635] G[261] S[694] S[634] G[263] S[693] S[633] G[265] S[692] S[632] G[267] S[691] S[631] G[269] S[690] S[630] G[271] S[689] S[629] G[273] S[688] S[628] G[275] S[687] S[627] G[277] S[686] S[626] G[279] S[685] S[625] G[281] S[684] S[624] G[283] S[683] S[623] G[285] S[682] S[622] G[287] S[681] S[621] G[289] S[680] S[620] G[291] S[679] S[619] G[293] S[678] S[618] G[295] S[677] S[617] G[297] S[676] S[616] G[299] S[675] S[615] G[301] S[674] S[614] G[303] S[673] S[613] G[305] S[672] S[612] G[307] S[671] S[611] G[309] S[670] S[610] Page 18 of 135 Version: 011

19 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 541 S[609] S[549] S[489] S[608] S[548] S[488] S[607] S[547] S[487] S[606] S[546] S[486] S[605] S[545] S[485] S[604] S[544] S[484] S[603] S[543] S[483] S[602] S[542] S[482] S[601] S[541] S[481] S[600] S[540] S[480] S[599] S[539] S[479] S[598] S[538] S[478] S[597] S[537] S[477] S[596] S[536] S[476] S[595] S[535] S[475] S[594] S[534] S[474] S[593] S[533] S[473] S[592] S[532] S[472] S[591] S[531] S[471] S[590] S[530] S[470] S[589] S[529] S[469] S[588] S[528] S[468] S[587] S[527] S[467] S[586] S[526] S[466] S[585] S[525] S[465] S[584] S[524] S[464] S[583] S[523] S[463] S[582] S[522] S[462] S[581] S[521] S[461] S[580] S[520] S[460] S[579] S[519] S[459] S[578] S[518] S[458] S[577] S[517] S[457] S[576] S[516] S[456] S[575] S[515] S[455] S[574] S[514] S[454] S[573] S[513] S[453] S[572] S[512] S[452] S[571] S[511] S[451] S[570] S[510] S[450] S[569] S[509] S[449] S[568] S[508] S[448] S[567] S[507] S[447] S[566] S[506] S[446] S[565] S[505] S[445] S[564] S[504] S[444] S[563] S[503] S[443] S[562] S[502] S[442] S[561] S[501] S[441] S[560] S[500] S[440] S[559] S[499] S[439] S[558] S[498] S[438] S[557] S[497] S[437] S[556] S[496] S[436] S[555] S[495] S[435] S[554] S[494] S[434] S[553] S[493] S[433] S[552] S[492] S[432] S[551] S[491] S[431] S[550] S[490] S[430] Page 19 of 135 Version: 011

20 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 721 S[429] S[369] S[311] S[428] S[368] S[310] S[427] S[367] S[309] S[426] S[366] S[308] S[425] S[365] S[307] S[424] S[364] S[306] S[423] S[363] S[305] S[422] S[362] S[304] S[421] S[361] S[303] S[420] VGMMA S[302] S[419] VGMMA S[301] S[418] S[360] S[300] S[417] S[359] S[299] S[416] S[358] S[298] S[415] S[357] S[297] S[414] S[356] S[296] S[413] S[355] S[295] S[412] S[354] S[294] S[411] S[353] S[293] S[410] S[352] S[292] S[409] S[351] S[291] S[408] S[350] S[290] S[407] S[349] S[289] S[406] S[348] S[288] S[405] S[347] S[287] S[404] S[346] S[286] S[403] S[345] S[285] S[402] S[344] S[284] S[401] S[343] S[283] S[400] S[342] S[282] S[399] S[341] S[281] S[398] S[340] S[280] S[397] S[339] S[279] S[396] S[338] S[278] S[395] S[337] S[277] S[394] S[336] S[276] S[393] S[335] S[275] S[392] S[334] S[274] S[391] S[333] S[273] S[390] S[332] S[272] S[389] S[331] S[271] S[388] S[330] S[270] S[387] S[329] S[269] S[386] S[328] S[268] S[385] S[327] S[267] S[384] S[326] S[266] S[383] S[325] S[265] S[382] S[324] S[264] S[381] S[323] S[263] S[380] S[322] S[262] S[379] S[321] S[261] S[378] S[320] S[260] S[377] S[319] S[259] S[376] S[318] S[258] S[375] S[317] S[257] S[374] S[316] S[256] S[373] S[315] S[255] S[372] S[314] S[254] S[371] S[313] S[253] S[370] S[312] S[252] Page 20 of 135 Version: 011

21 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 901 S[251] S[191] S[131] S[250] S[190] S[130] S[249] S[189] S[129] S[248] S[188] S[128] S[247] S[187] S[127] S[246] S[186] S[126] S[245] S[185] S[125] S[244] S[184] S[124] S[243] S[183] S[123] S[242] S[182] S[122] S[241] S[181] S[121] S[240] S[180] S[120] S[239] S[179] S[119] S[238] S[178] S[118] S[237] S[177] S[117] S[236] S[176] S[116] S[235] S[175] S[115] S[234] S[174] S[114] S[233] S[173] S[113] S[232] S[172] S[112] S[231] S[171] S[111] S[230] S[170] S[110] S[229] S[169] S[109] S[228] S[168] S[108] S[227] S[167] S[107] S[226] S[166] S[106] S[225] S[165] S[105] S[224] S[164] S[104] S[223] S[163] S[103] S[222] S[162] S[102] S[221] S[161] S[101] S[220] S[160] S[100] S[219] S[159] S[99] S[218] S[158] S[98] S[217] S[157] S[97] S[216] S[156] S[96] S[215] S[155] S[95] S[214] S[154] S[94] S[213] S[153] S[93] S[212] S[152] S[92] S[211] S[151] S[91] S[210] S[150] S[90] S[209] S[149] S[89] S[208] S[148] S[88] S[207] S[147] S[87] S[206] S[146] S[86] S[205] S[145] S[85] S[204] S[144] S[84] S[203] S[143] S[83] S[202] S[142] S[82] S[201] S[141] S[81] S[200] S[140] S[80] S[199] S[139] S[79] S[198] S[138] S[78] S[197] S[137] S[77] S[196] S[136] S[76] S[195] S[135] S[75] S[194] S[134] S[74] S[193] S[133] S[73] S[192] S[132] S[72] Page 21 of 135 Version: 011

22 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1081 S[71] S[11] G[230] S[70] S[10] G[228] S[69] S[9] G[226] S[68] S[8] G[224] S[67] S[7] G[222] S[66] S[6] G[220] S[65] S[5] G[218] S[64] S[4] G[216] S[63] S[3] G[214] S[62] S[2] G[212] S[61] S[1] G[210] S[60] DUMMY G[208] S[59] DUMMY G[206] S[58] DUMMY G[204] S[57] VGLDMY G[202] S[56] G[320] G[200] S[55] G[318] G[198] S[54] G[316] G[196] S[53] G[314] G[194] S[52] G[312] G[192] S[51] G[310] G[190] S[50] G[308] G[188] S[49] G[306] G[186] S[48] G[304] G[184] S[47] G[302] G[182] S[46] G[300] G[180] S[45] G[298] G[178] S[44] G[296] G[176] S[43] G[294] G[174] S[42] G[292] G[172] S[41] G[290] G[170] S[40] G[288] G[168] S[39] G[286] G[166] S[38] G[284] G[164] S[37] G[282] G[162] S[36] G[280] G[160] S[35] G[278] G[158] S[34] G[276] G[156] S[33] G[274] G[154] S[32] G[272] G[152] S[31] G[270] G[150] S[30] G[268] G[148] S[29] G[266] G[146] S[28] G[264] G[144] S[27] G[262] G[142] S[26] G[260] G[140] S[25] G[258] G[138] S[24] G[256] G[136] S[23] G[254] G[134] S[22] G[252] G[132] S[21] G[250] G[130] S[20] G[248] G[128] S[19] G[246] G[126] S[18] G[244] G[124] S[17] G[242] G[122] S[16] G[240] G[120] S[15] G[238] G[118] S[14] G[236] G[116] S[13] G[234] G[114] S[12] G[232] G[112] Page 22 of 135 Version: 011

23 NO Pad Name X Y NO Pad Name X Y NO Pad Name X Y 1261 G[110] G[70] G[30] G[108] G[68] G[28] G[106] G[66] G[26] G[104] G[64] G[24] G[102] G[62] G[22] G[100] G[60] G[20] G[98] G[58] G[18] G[96] G[56] G[16] G[94] G[54] G[14] G[92] G[52] G[12] G[90] G[50] G[10] G[88] G[48] G[8] G[86] G[46] G[6] G[84] G[44] G[4] G[82] G[42] G[2] G[80] G[40] VGLDMY G[78] G[38] DUMMYR G[76] G[36] DUMMYR G[74] G[34] DUMMY G[72] G[32] DUMMY S1 ~ S720 G1 ~ G320 DUMMY18~31 VGMMA1, 62 VGLDMY1~ Unit: um Page 23 of 135 Version: 011

24 I/O Pads Pad Pump Pad Pump 80 Min 70 Unit: um Alignment mark Alignment mark X Y Page 24 of 135 Version: 011

25 6 Block Description MPU System Interface supports three system high-speed interfaces: i80-system high-speed interfaces to 8-, 9-, 16-, 18-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:0] pins has a 16-bit index register (IR), an 18-bit write-data register (R), and an 18-bit read-data register (R) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The R is the register to temporarily store data read from the GRAM Data from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation Data are read via the R from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time Registers selection by system interface (8-/9-/16-/18-bit bus width) I80 Function RS nwr n Write an index to IR register Write to control registers or the internal GRAM by R register Read from the internal GRAM by R register Registers selection by the SPI system interface Function R/W RS Write an index to IR register 0 0 Write to control registers or the internal GRAM by R register 0 1 Read from the internal GRAM by R register 1 1 Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and DOTCLK In RGB interface mode, data (17-0) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal Display data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External Display Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Page 25 of 135 Version: 011