ILI9325D. a-si TFT LCD Single Chip Driver 240RGBx320 Resolution and 262K Color. Datasheet

Transcription

1 a-si TFT LC Single Chip river 4RGBx3 Resolution and 6K Color atasheet Version: V ocument No: _S_Vpdf ILI TECHNOLOGY CORP 8F, No38, Taiyuan St, Jhubei City, Hsinchu County 3, Taiwan, ROC Tel ; Fax

2 Table of Contents Section Page Introduction 7 Features 8 3 Block iagram 4 Pin escriptions 5 Pad Arrangement and Coordination 6 Block escription 3 7 System Interface 5 7 Interface Specifications 5 7 Input Interfaces 6 7 i8/8-bit System Interface 7 7 i8/-bit System Interface 8 73 i8/9-bit System Interface 9 74 i8/8-bit System Interface 3 73 Serial Peripheral Interface (SPI) bit 4 wires Serial Peripheral Interface wire 9-bit Serial Interface wire 8-bit Serial Interface VSYNC Interface RGB Input Interface RGB Interface RGB Interface Timing Moving Picture Mode bit RGB Interface bit RGB Interface bit RGB Interface Interface Timing 5 77 CABC (Content Adaptive Brightness Control) 53 8 Register escriptions 54 8 Registers Access 54 8 Instruction escriptions 57 8 Index (IR) 6 8 I code (Rh) 6 83 river Output Control (Rh) 6 84 LC riving Wave Control (Rh) 6 85 Entry Mode (R3h) 6 86 bits ata Format Selection (R5h) isplay Control (R7h) 66 Page of 5 Version:

3 88 isplay Control (R8h) isplay Control 3 (R9h) 68 8 isplay Control 4 (RAh) 69 8 RGB isplay Interface Control (RCh) 69 8 Frame Marker Position (Rh) 7 83 RGB isplay Interface Control (RFh) 7 84 Power Control (Rh) 7 8 Power Control (Rh) 7 8 Power Control 3 (Rh) 73 8 Power Control 4 (R3h) GRAM Horizontal/Vertical Address Set (Rh, Rh) Write ata to GRAM (Rh) 75 8 Read ata from GRAM (Rh) 75 8 Power Control 7 (R9h) 78 8 Frame Rate and Color Control (RBh) Gamma Control (R3h ~ R3h) Horizontal and Vertical RAM Address Position (R5h, R5h, R5h, R53h) Gate Scan Control (R6h, R6h, R6Ah) 8 86 SPI Read/Write Control (R66h, Write Only) Partial Image isplay Position (R8h) Partial Image RAM Start/End Address (R8h, R8h) Partial Image isplay Position (R83h) Partial Image RAM Start/End Address (R84h, R85h) Panel Interface Control (R9h) Panel Interface Control (R9h) Panel Interface Control 4 (R95h) Panel Interface Control 5 (R97h) OTP I Code Programming Control (RAh) OTP VCM Programming Control (RAh) OTP VCM Status and Enable (RAh) OTP Programming I Key (RA5h) Write isplay Brightness Value (RBh) Read isplay Brightness Value (RBh) Write CTRL isplay Value (RB3h) Read CTRL isplay Value (RB4h) Write Content Adaptive Brightness Control Value (RB5h) Read Content Adaptive Brightness Control Value (RB6h) Write CABC Minimum Brightness (RBEh) Read CABC Minimum Brightness (RBFh) 89 Page 3 of 5 Version:

4 847 CABC Control (RC7h) CABC Control (RC8h) CABC Control (RC9h) 9 85 CABC Control 3 (RCAh) 9 85 CABC Control 4 (RCBh) CABC Control 5 (RCCh) CABC Control 6 (RCh) igital Gamma Control (Rh, Write Only) igital Gamma Control (REh, Write Only) 96 9 OTP Programming Flow 97 GRAM Address Map & Read/Write 98 Window Address Function 3 Gamma Correction 4 3 Application 3 Configuration of Power Supply Circuit 3 isplay ON/OFF Sequence 4 33 Standby and Sleep Mode 34 Power Supply Configuration 35 Voltage Generation 36 Applied Voltage to the TFT panel 8 37 Partial isplay Function 8 4 Electrical Characteristics 4 Absolute Maximum Ratings 4 C Characteristics 43 Reset Timing Characteristics 44 AC Characteristics 44 i8-system Interface Timing Characteristics 44 Serial ata Transfer Interface Timing Characteristics RGB Interface Timing Characteristics 4 Revision History 5 Page 4 of 5 Version:

5 Figures FIGURE SYSTEM INTERFACE AN RGB INTERFACE CONNECTION 6 FIGURE 8-BIT SYSTEM INTERFACE ATA FORMAT 7 FIGURE 3 -BIT SYSTEM INTERFACE ATA FORMAT 8 FIGURE 4 9-BIT SYSTEM INTERFACE ATA FORMAT 9 FIGURE 5 8-BIT SYSTEM INTERFACE ATA FORMAT 3 FIGURE 6 ATA FORMAT OF SPI INTERFACE 3 FIGURE 7 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) () 33 FIGURE 8 ATA TRANSMISSION THROUGH SERIAL PERIPHERAL INTERFACE (SPI) () 34 FIGURE 9 ATA TRANSMISSION THROUGH VSYNC INTERFACE) 39 FIGURE MOVING PICTURE ATA TRANSMISSION THROUGH VSYNC INTERFACE 39 FIGURE OPERATION THROUGH VSYNC INTERFACE 4 FIGURE TRANSITION FLOW BETWEEN VSYNC AN INTERNAL CLOCK OPERATION MOES 4 FIGURE 3 RGB INTERFACE ATA FORMAT 43 FIGURE 4 GRAM ACCESS AREA BY RGB INTERFACE 44 FIGURE TIMING CHART OF SIGNALS IN 8-/-BIT RGB INTERFACE MOE 45 FIGURE TIMING CHART OF SIGNALS IN 6-BIT RGB INTERFACE MOE 46 FIGURE EXAMPLE OF UPATE THE STILL AN MOVING PICTURE 47 FIGURE 8 INTERNAL CLOCK OPERATION/RGB INTERFACE MOE SWITCHING 5 FIGURE 9 TRANSITION OF GRAM ACCESS BETWEEN SYSTEM INTERFACE AN RGB INTERFACE 5 FIGURE RELATIONSHIP BETWEEN RGB I/F SIGNALS AN LC RIVING SIGNALS FOR PANEL 5 FIGURE REGISTER SETTING WITH SERIAL PERIPHERAL INTERFACE (SPI) 54 FIGURE REGISTER SETTING WITH I8 SYSTEM INTERFACE 55 FIGURE 3 REGISTER REA/WRITE TIMING OF I8 SYSTEM INTERFACE 56 FIGURE 4 GRAM ACCESS IRECTION SETTING 6 FIGURE 5 -BIT MPU SYSTEM INTERFACE ATA FORMAT 63 FIGURE 6 8-BIT MPU SYSTEM INTERFACE ATA FORMAT 64 FIGURE 7 ATA REA FROM GRAM THROUGH REA ATA REGISTER IN 8-/-/9-/8-BIT INTERFACE MOE 76 FIGURE 8 GRAM ATA REA BACK FLOW CHART 77 FIGURE 9 GRAM ACCESS RANGE CONFIGURATION 8 FIGURE 3 GRAM REA/WRITE TIMING OF I8-SYSTEM INTERFACE 98 FIGURE 3 I8-SYSTEM INTERFACE WITH 8-/-/9-BIT ATA BUS (SS=, BGR= ) FIGURE 3 I8-SYSTEM INTERFACE WITH 8-BIT ATA BUS (SS=, BGR= ) FIGURE 33 I8-SYSTEM INTERFACE WITH 8-/9-BIT ATA BUS (SS=, BGR= ) FIGURE 34 GRAM ACCESS WINOW MAP 3 FIGURE 35 GRAYSCALE VOLTAGE GENERATION 4 FIGURE 36 GRAYSCALE VOLTAGE AJUSTMENT 5 FIGURE 37 GAMMA CURVE AJUSTMENT 6 FIGURE 38 EXAMPLE OF RMP(N)~5 EFINITION 8 Page 5 of 5 Version:

6 FIGURE 39 RELATIONSHIP BETWEEN SOURCE OUTPUT AN VCOM FIGURE 4 RELATIONSHIP BETWEEN GRAM ATA AN OUTPUT LEVEL FIGURE 4 POWER SUPPLY CIRCUIT BLOCK FIGURE 4 ISPLAY ON/OFF REGISTER SETTING SEQUENCE 4 FIGURE 43 STANY/SLEEP MOE REGISTER SETTING SEQUENCE FIGURE 44 POWER SUPPLY ON/OFF SEQUENCE FIGURE 45 VOLTAGE CONFIGURATION IAGRAM FIGURE 46 VOLTAGE OUTPUT TO TFT LC PANEL 8 FIGURE 47 PARTIAL ISPLAY EXAMPLE 9 FIGURE 48 I8-SYSTEM BUS TIMING FIGURE 49 SPI SYSTEM BUS TIMING 3 FIGURE 5 RGB INTERFACE TIMING 4 Page 6 of 5 Version:

7 Introduction a-si TFT LC Single Chip river is a 6,44-color one-chip SoC driver for a-tft liquid crystal display with resolution of 4RGBx3 dots, comprising a 7-channel source driver, a 3-channel gate driver,,8 bytes RAM for graphic data of 4RGBx3 dots, and power supply circuit has four kinds of transmission interfaces which are i8-system MPU interface (8-/9-/-/8-bit bus width), VSYNC interface (system interface + VSYNC, internal clock, [:]), serial data transfer interface (SPI), RGB 6-/-/8-bit interface (OTCLK, VSYNC, HSYNC, ENABLE, [:]) In RGB interface and VSYNC interface mode, the combined use of high-speed RAM write function and widow address function enables to display a moving picture at a position specified by a user and still pictures in other areas on the screen simultaneously, which makes it possible to transfer display the refresh data only to minimize data transfers and power consumption can operate with 5V I/O interface voltage, and an incorporated voltage follower circuit to generate voltage levels for driving an LC The also supports a function to display in 8 colors and a sleep mode, allowing for precise power control by software and these features make the an ideal LC driver for medium or small size portable products such as digital cellular phones, smart phone, PA and PMP where long battery life is a major concern Page 7 of 5 Version:

8 Features a-si TFT LC Single Chip river Single chip solution for a liquid crystal QVGA TFT LC display 4RGBx3-dot resolution capable with real 6,44 display color Support MVA (Multi-domain Vertical Alignment) wide view display Incorporate 7-channel source driver and 3-channel gate driver Internal,8 bytes graphic RAM CABC (Content Adaptive Brightness Control) System interfaces i8 system interface with 8-/ 9-/-/8-bit bus width Serial Peripheral Interface (SPI) RGB interface with 6-/-/8-bit bus width (VSYNC, HSYNC, OTCLK, ENABLE, [:]) VSYNC interface (System interface + VSYNC) Internal oscillator and hardware reset Reversible source/gate driver shift direction Window address function to specify a rectangular area for internal GRAM access Abundant functions for color display control γ-correction function enabling display in 6,44 colors Line-unit vertical scrolling function Partial drive function, enabling partially driving an LC panel at positions specified by user Incorporate step-up circuits for stepping up a liquid crystal drive voltage level up to 6 times (x6) Power saving functions 8-color mode standby mode sleep mode Low -power consumption architecture Low operating power supplies: IOVCC = 5V ~ 33 V (interface I/O) VCI = 5V ~ 33 V (analog) LC Voltage drive: Source/VCOM power supply voltage VH - GN = 45V ~ 6 VCL GN = -V ~ -3V VCI VCL 6V Gate driver output voltage VGH - GN = V ~ V VGL GN = -5V ~ -V VGH VGL 3V VCOM driver output voltage VCOMH = (VCI+)V ~ (VH-)V Page 8 of 5 Version:

9 VCOML = (VCL+)V ~ V VCOMH-VCOML 6V a-tft LC storage capacitor: Cst only Page 9 of 5 Version:

10 3 Block iagram IOVCC IM[3:] nreset Index Register (IR) ncs nwr/scl nr RS SI SO MPU I/F 8-bit -bit 9-bit 8-bit 8 7 Control Register (CR) Address Counter (AC) LC Source river S[7:] [:] HSYNC VSYNC OTCLK ENABLE TEST TEST TEST3 TS[8:] SPI I/F RGB I/F 8-bit -bit 6-bit VSYNC I/F 8 8 Graphics Operation Read Latch 8 8 Write Latch 8 V63 ~ Grayscale Reference Voltage VREGOUT VGS Graphics RAM (GRAM) UMMY~7 VCC V GN LEPWM LEON Regulator RC-OSC Timing Controller Brightness control CABC Block LC Gate river G[3:] UMMY~ VCI VCI Charge-pump Power Circuit VCOM Generator VCOM GN CA CB VH CA CB C3A C3B VCL CA CB CA CB VGH VGL VCOMH VCOML Page of 5 Version:

11 4 Pin escriptions Pin Name I/O Type escriptions Input Interface Select the MPU system interface mode IM3 IM IM IM MPU-Interface Mode Pin in use IM3, IM, IM, IM/I ncs RS nwr/scl nr nreset SI / SA SO [:] I I I I I I I/O O I/O IOVCC MPU IOVCC MPU IOVCC MPU IOVCC MPU IOVCC MPU IOVCC MPU IOVcc MPU IOVCC MPU IOVCC Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO 9-bit 3 wires Serial Peripheral Interface 8-bit 4 wires Serial Peripheral Interface Setting invalid Setting invalid SA, SCL, ncs i8-system 8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid SA, SCL, ncs, RS (/CX) When the serial peripheral interface is selected, IM pin is used for the device code I setting A chip select signal Low: the is selected and accessible High: the is not selected and not accessible Fix to the GN level when not in use A register select signal Low: select an index or status register High: select a control register Fix to either IOVCC or GN level when not in use A write strobe signal and enables an operation to write data when the signal is low Fix to either IOVCC or GN level when not in use SPI Mode: Synchronizing clock signal in SPI mode A read strobe signal and enables an operation to read out data when the signal is low Fix to either IOVcc or GN level when not in use A reset pin Initializes the with a low input Be sure to execute a power-on reset after supplying power SPI interface input pin The data is latched on the rising edge of the SCL signal In the 8/9-bit serial peripheral interface, this pin is used as bi-directional data pin SPI interface output pin The data is outputted on the falling edge of the SCL signal Let SO as floating when not used An 8-bit parallel bi-directional data bus for MPU system interface mode 8-bit I/F: [:] is used Page of 5 Version:

12 Pin Name I/O Type escriptions 9-bit I/F: [:9] is used -bit I/F: [:] and [8:] is used 8-bit I/F: [:] is used 8-bit parallel bi-directional data bus for RGB interface operation 6-bit RGB I/F: [:] are used -bit RGB I/F: [:3] and [:] are used 8-bit RGB I/F: [:] are used ENABLE I MPU IOVCC Unused pins must be fixed to GN level ata ENEABLE signal for RGB interface operation Low: Select (access enabled) High: Not select (access inhibited) The EPL bit inverts the polarity of the ENABLE signal OTCLK VSYNC HSYNC FMARK LEPWM/ TESTO LEON/ TESTO I I I O MPU IOVCC MPU IOVCC MPU IOVCC MPU IOVCC Fix to either IOVCC or GN level when not in use ot clock signal for RGB interface operation PL = : Input data on the rising edge of OTCLK PL = : Input data on the falling edge of OTCLK Fix to the GN level when not in use Frame synchronizing signal for RGB interface operation VSPL = : Active low VSPL = : Active high Fix to the GN level when not in use Line synchronizing signal for RGB interface operation HSPL = : Active low HSPL = : Active high Fix to the GN level when not in use Output a frame head pulse signal The FMARK signal is used when writing RAM data in synchronization with frame Leave the pin open when not in use O VCI PWM signal output to control LE driver for LE brightness dimming O VCI This pin is connected to external LE driver It s a LE driver control pin which is used for turning ON/OFF of LE backlight LC riving signals S7~S O LC Source output voltage signals applied to liquid crystal To change the shift direction of signal outputs, use the SS bit SS =, the data in the RAM address h is output from S SS =, the data in the RAM address h is output from S7 S, S4, S7, display red (R), S, S5, S8, display green (G), and S3, S6, S9, display blue (B) (SS = ) G3~G O LC Gate line output signals VGH: the level selecting gate lines VGL: the level not selecting gate lines VCOM O TFT common electrode A supply voltage to the common electrode of TFT panel VCOM is AC voltage alternating signal between the VCOMH and VCOML levels Adjust the VCOM amplitude with the VV bits VCOMH O - The high level of VCOM AC voltage VCOML O - The low level of VCOM AC voltage VGS I GN or Reference level for the grayscale voltage generating circuit The VGS external level can be changed by connecting to an external resistor resistor Charge-pump and Regulator Circuit Page of 5 Version:

13 Pin Name I/O Type escriptions VCI I Power A supply voltage to the analog circuit Connect to an external power supply supply of 5 ~ 33V GN I Power GN for the analog side: GN = V In case of COG, connect to GN supply on the FPC to prevent noise An internal reference voltage for the step-up circuit VCI O - The amplitude between VCI and GN is determined by the VC[:] bits Make sure to set the VCI voltage so that the VH, VGH and VGL voltages are set within the respective specification VH O Stabilizing capacitor Power supply for the source driver and VCOM drive VGH O Stabilizing capacitor Power supply for the gate driver VGL O Stabilizing capacitor Power supply for the gate driver VCL O Stabilizing VCOML driver power supply capacitor VCL = 5 ~ VCI Place a stabilizing capacitor between GN C+, C- I/O Step-up capacitor Capacitor connection pins for the step-up circuit C3+, C3- Step-up C+, C- I/O capacitor C+, C- Capacitor connection pins for the step-up circuit Output voltage generated from the reference voltage VREGOUT IOVCC I/O I Stabilizing capacitor Power supply The voltage level is set with the VRH bits VREGOUT is () a source driver grayscale reference voltage, () VCOMH level reference voltage, and (3) VCOM amplitude reference voltage Connect to a stabilizing capacitor VREGOUT = 3 ~ (VH )V Power Pads A supply voltage to the interface pins: IM[3:], nreset, ncs, nwr, nr, RS, [:], VSYNC, HSYNC, OTCLK, ENABLE, SCL, SI, SO IOVCC = 5 ~ 33V and VCI IOVcc In case of COG, connect to VCI on the FPC if IOVCC=VCI, to prevent noise igital circuit power pad Connect these pins with the uf capacitor V O Step-up capacitor GN I Power supply GN = V Test Pads UMMY3~ ummy pad - - UMMY~7 Leave these pins as open TEST_EN I IOGN Test pins (internal pull low) Connect to GN or leave these pins as open TEST,, 3 I IOGN Test pins (internal pull low) Connect to GN or leave these pins as open TS~8 I OPEN Test pins (internal pull low) Leave them open IOGNUM O GN GN pin TSO O OPEN Test pins Leave them open TESTO~ O Open Test pins Leave them open Page 3 of 5 Version:

14 Liquid crystal power supply specifications Table No Item escription TFT Source river 7 pins (4 x RGB) TFT Gate river 3 pins 3 TFT isplay s Capacitor Structure Cst structure only (Common VCOM) S ~ S7 V ~ V63 grayscales 4 Liquid Crystal rive Output G ~ G3 VGH - VGL VCOM VCOMH - VCOML: Amplitude = electronic volumes 5 Input Voltage IOVCC 5 ~ 33V VCI 5 ~ 33V VH 45V ~ 6V VGH V ~ V 6 Liquid Crystal rive Voltages VGL -5V ~ -V VCL -9V ~ -3V VGH - VGL Max 3V VCI - VCL Max 6V VH VCI x 7 Internal Step-up Circuits VGH VCI x4, x5, x6 VGL VCI x-3, x-4, x-5 VCL VCI x- Page 4 of 5 Version:

15 a-si TFT LC Single Chip river 5 Pad Arrangement and Coordination Chip Size: 8um x 7um Chip thickness : 8um (typ) Pad Location: Pad Center Coordinate Origin: Chip center Au bump height: um (typ) Au Bump Size: um x 98um Gate: G ~ G3 Source: S ~ S7 5um x 8um Input Pads Pad to 43 Alignment Marks UMMY TEST IOGNUM LEPWM LEON TESTO3 IM/I IM IM IM3 TEST TESTO4 TESTO5 TESTO6 TESTO7 TESTO8 TESTO9 TESTO nreset nreset VSYNC HSYNC OTCLK ENABLE 4 3 TESTO 9 8 TEST3 TESTO TESTO3 SO SI nr nwr/scl RS ncs TESTO4 TESTO FMARK TESTO TS8 TS7 TS6 TS5 TS4 TS3 TS TS TS UMMY IOVCC IOVCC IOVCC IOVCC IOVCC IOVCC V V V V V V V V V V V UMMY3 GN GN GN GN GN GN GN GN VGS VGS GN GN GN GN GN GN GN GN GN GN UMMY4 UMMY5 UMMY6 VCOM VCOM VCOM VCOM VCOM VCOM VCOM VCOMH VCOMH VCOMH VCOMH VCOMH VCOMH Face Up (Bump View) UMMY7 G39 G3 G3 G33 G3 G39 G37 G35 G33 G G G3 G G9 G7 G5 G3 G UMMY 6 UMMY5 S S S3 S4 S5 S6 S7 S8 S9 S353 S354 S355 S356 S357 S358 S359 S36 UMMY4 Alignment Mark: A VCOML VCOML VCOML VCOML VREGOUT VREGOUT VREGOUT UMMY7 UMMY8 UMMY9 VCL VCL VCL VCL VCL VH VH VH VH VH x y UMMY3 S36 S36 S363 S364 S365 S366 S367 S368 S369 VH VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI VCI UMMY UMMY C- C- C- C- C- C+ C+ C+ C+ C+ C- C- C- C- C- C+ C+ C+ C+ C+ VGL VGL VGL VGL VGL VGL Alignment Mark: A VGL VGL VGL VGL GN GN GN VGH VGH VGH VGH VGH VGH UMMY UMMY3 C3- C3- C3- C3- C3+ C3+ C3+ C3+ C- C- C- C- C- C- C- C+ C+ C+ C+ C+ C+ C+ C- C- C- S7 S73 S74 S7 S7 S7 S78 S79 S7 UMMY UMMY G G4 G6 G8 G G G4 G G8 Bump View C- C- C- C- C+ C+ C+ C+ C+ C+ C+ UMMY4 UMMY G34 G36 G38 G3 G3 G34 G3 G38 G3 UMMY Page of 5 Version:

16 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y TEST_EN TS VCOML C C TEST TS VCOML C UMMY IOGNUM TS VCOML C UMMY LEPWM / TESTO TS VCOML C UMMY LEON / TESTO TS VREGOUT VGL G TESTO TSO VREGOUT VGL G IM/I IOVCC VREGOUT VGL G IM IOVCC UMMY VGL G IM IOVCC UMMY VGL G IM IOVCC UMMY VGL G TEST IOVCC VCL VGL G TESTO IOVCC VCL VGL G TESTO V VCL VGL G TESTO V VCL VGL G TESTO V VCL GN G TESTO V VH GN G TESTO V VH GN G TESTO V VH VGH G nreset V VH VGH G nreset V VH 4-54 VGH G VSYNC V VH VGH G HSYNC V VCI 4-54 VGH G OTCLK V VCI VGH G ENABLE UMMY VCI UMMY G GN VCI UMMY G GN VCI C G GN VCI C G GN VCI C G GN VCI C G TESTO GN VCI -54 C G GN VCI -54 C G GN VCI 4-54 C G VGS VCI C G VGS VCI C G GN VCI C G TEST GN VCI 5-54 C G TESTO GN VCI C G GN VCI C G GN VCI C G GN VCI 8-54 C G GN VCI C G GN VCI C G GN UMMY C G GN UMMY C G UMMY C C G TESTO UMMY C C G SO UMMY C C G SI VCOM C C G nr VCOM C C G nwr/scl VCOM C C G RS VCOM C C G ncs VCOM C C G TESTO VCOM C C G TESTO VCOM C C G FMARK VCOMH C C G TESTO VCOMH C C G TS VCOMH C C G TS VCOMH C C G TS VCOMH C C G TS VCOMH C C G Page of 5 Version:

17 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 3 G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G UMMY S S S G UMMY S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S Page of 5 Version:

18 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 6 S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S UMMY S S S S UMMY S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S Page 8 of 5 Version:

19 No Name X Y No Name X Y No Name X Y No Name X Y No Name X Y 9 S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S S G S S S UMMY G S S S UMMY G S S S G G S7-3 8 S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G S S S G G Page 9 of 5 Version:

20 No Name X Y No Name X Y G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G UMMY G G G G G G G G G G G G G G G G G G G G G G G G G G G G G Page of 5 Version:

21 S ~ S7 G ~ G3 UMMY~7 (No 44 ~ 9) Unit: um 5 x 5 I/O Pads (No ~ 43) P a d P ump P a d P ump 8 y X=, 3, 35 Y=7, 8, 85 Unit: um Page of 5 Version:

22 Alignment mark Alignment mark X Y Page of 5 Version:

23 6 Block escription MPU System Interface supports two system high-speed interfaces: i8-system high-speed interfaces to 8-, 9-, -, 8-bit parallel ports and serial peripheral interface (SPI) The interface mode is selected by setting the IM[3:] pins has a -bit index register (IR), an 8-bit write-data register (R), and an 8-bit read-data register (RR) The IR is the register to store index information from control registers and the internal GRAM The R is the register to temporarily store data to be written to control registers and the internal GRAM The RR is the register to temporarily store data read from the GRAM ata from the MPU to be written to the internal GRAM are first written to the R and then automatically written to the internal GRAM in internal operation ata are read via the RR from the internal GRAM Therefore, invalid data are read out to the data bus when the read the first data from the internal GRAM Valid data are read out after the performs the second read operation Registers are written consecutively as the register execution time Registers selection by system interface (8-/9-/-/8-bit bus width) I8 Function RS nwr nr Write an index to IR register Write to control registers or the internal GRAM by R register Read from the internal GRAM by RR register Registers selection by the SPI system interface Function R/W RS Write an index to IR register Write to control registers or the internal GRAM by R register Read from the internal GRAM by RR register Parallel RGB Interface supports the RGB interface and the VSYNC interface as the external interface for displaying a moving picture When the RGB interface is selected, display operations are synchronized with externally supplied signals, VSYNC, HSYNC, and OTCLK In RGB interface mode, data (-) are written in synchronization with these signals according to the polarity of enable signal (ENABLE) to prevent flicker on display while updating display data In VSYNC interface mode, the display operation is synchronized with the internal clock except frame synchronization, where the operation is synchronized with the VSYNC signal isplay data are written to the internal GRAM via the system interface In this case, there are constraints in speed and method in writing data to the internal RAM For details, see the External isplay Interface section The allows for switching between the external display interface and the system interface by instruction so that the optimum interface is selected for the kind of picture to be displayed on the screen (still and/or moving picture(s)) The RGB interface, by writing all display data to the internal RAM, allows for transferring data only when updating the frames of a moving picture, contributing to low power requirement for moving picture display Page 3 of 5 Version:

24 Address Counter (AC) The address counter (AC) gives an address to the internal GRAM When the index of the register for setting a RAM address in the AC is written to the IR, the address information is sent from the IR to the AC As writing data to the internal GRAM, the address in the AC is automatically updated plus or minus The window address function enables writing data only in the rectangular area arbitrarily set by users on the GRAM Graphics RAM (GRAM) GRAM is graphics RAM storing bit-pattern data of,8 (4 x 3x 8/8) bytes with 8 bits per pixel Grayscale Voltage Generating Circuit The grayscale voltage generating circuit generates a liquid crystal drive voltage according to grayscale data set in the γ-correction register to display in 6,44 colors For details, see the γ-correction Register section Timing Controller The timing generator generates a timing signal for operation of internal circuits such as the internal GRAM The timing for the display operation such as RAM read operation and the timing for the internal operation such as access from the MPU are generated in the way not to interfere each other Oscillator (OSC) generates RC oscillation with an internal oscillation resistor The frame rate is adjusted by the register setting LC river Circuit The LC driver circuit of consists of a 7-output source driver (S ~ S7) and a 3-output gate driver (G~G3) isplay pattern data are latched when the 7 th bit data are input The latched data control the source driver and generate a drive waveform The gate driver for scanning gate lines outputs either VGH or VGL level The shift direction of 7 source outputs from the source driver is set with the SS bit and the shift direction of gate outputs from the gate driver is set with the GS bit The scan mode by the gate driver is set with the SM bit These bits allow setting an appropriate scan method for an LC module LC river Power Supply Circuit The LC drive power supply circuit generates the voltage levels VREGOUT, VGH, VGL and Vcom for driving an LC Page 4 of 5 Version:

25 7 System Interface 7 Interface Specifications has the system interface to read/write the control registers and display graphics memory (GRAM), and the RGB Input Interface for displaying a moving picture User can select an optimum interface to display the moving or still picture with efficient data transfer All display data are stored in the GRAM to reduce the data transfer efforts and only the updating data is necessary to be transferred User can only update a sub-range of GRAM by using the window address function also has the RGB interface and VSYNC interface to transfer the display data without flicker the moving picture on the screen In RGB interface mode, the display data is written into the GRAM through the control signals of ENABLE, VSYNC, HSYNC, OTCLK and data bus [:] In VSYNC interface mode, the internal display timing is synchronized with the frame synchronization signal (VSYNC) The VSYNC interface mode enables to display the moving picture display through the system interface In this case, there are some constraints of speed and method to write data to the internal RAM operates in one of the following 4 modes The display mode can be switched by the control register When switching from one mode to another, refer to the sequences mentioned in the sections of RGB and VSYNC interfaces Operation Mode RAM Access Setting (RM) isplay Operation Mode (M[:]) Internal operating clock only (isplaying still pictures) RGB interface () (isplaying moving pictures) RGB interface () (Rewriting still pictures while displaying moving pictures) VSYNC interface (isplaying moving pictures) System interface (RM = ) RGB interface (RM = ) System interface (RM = ) System interface (RM = ) Internal operating clock (M[:] = ) RGB interface (M[:] = ) RGB interface (M[:] = ) VSYNC interface (M[:] = ) Note ) Registers are set only via the system interface Note ) The RGB-I/F and the VSYNC-I/F are not available simultaneously Page 5 of 5 Version:

26 Figure System Interface and RGB Interface connection 7 Input Interfaces The following are the system interfaces available with the The interface is selected by setting the IM[3:] pins The system interface is used for setting registers and GRAM access IM3 IM IM IM/I Interface Mode Pin Setting invalid Setting invalid i8-system -bit interface [:], [8:] i8-system 8-bit interface [:] I Serial Peripheral Interface (SPI) SI, SO ([:]) 9-bit 3 wires Serial Peripheral Interface SA, SCL, ncs 8-bit 4 wires Serial Peripheral Interface SA, SCL, ncs, RS (/CX) Setting invalid Setting invalid i8-system8-bit interface [:] i8-system 9-bit interface [:9] * * Setting invalid Page 6 of 5 Version:

27 7 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as levels Host System 8 ncs RS nwr nr [:] 8-bit System Interface (6K colors) TRI=, FM= Input ata Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 8-bit System Interface ata Format Page 7 of 5 Version:

28 7 i8/-bit System Interface The i8/-bit system interface is selected by setting the IM[3:] as levels The 6K or 65K color can be display through the -bit MPU interface When the 6K color is displayed, two transfers ( st transfer: bits, nd transfer: bits or st transfer: bits, nd transfer: bits) are necessary for the -bit CPU interface Host System ncs RS nwr nr [:], [8:] 9, TRI FM -bit MPU System Interface ata Format system -bit interface ( transfers/pixel) 65,536 colors (EPF default setting= ) * 4 3 st Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,44 colors 4 3 st Transfer nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system -bit interface ( transfers/pixel) 6,44 colors st Transfer 4 3 nd Transfer R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 3 -bit System Interface ata Format Page 8 of 5 Version:

29 73 i8/9-bit System Interface The i8/9-bit system interface is selected by setting the IM[3:] as and the ~9 pins are used to transfer the data When writing the 8-bit register, the data is divided into upper byte (9 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (9 bits) and lower byte, and the upper byte is transferred first The unused [8:] pins must be tied to GN Host System 9 ncs RS nwr nr [:9] 9 [8:] 9-bit System Interface (6K colors) TRI=, FM= Input ata st Transfer (Upper bits) nd Transfer (Lower bits) Write ata Register GRAM ata & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 4 9-bit System Interface ata Format Page 9 of 5 Version:

30 74 i8/8-bit System Interface The i8/8-bit system interface is selected by setting the IM[3:] as and the ~ pins are used to transfer the data When writing the -bit register, the data is divided into upper byte (8 bits and LSB is not used) lower byte and the upper byte is transferred first The display data is also divided in upper byte (8 bits) and lower byte, and the upper byte is transferred first The written data is expanded into 8 bits internally (see the figure below) and then written into GRAM The unused [9:] pins must be tied to GN Host System 8 ncs RS nwr nr [:] [9:] TRI FM 8-bit MPU System Interface ata Format system 8-bit interface ( transfers/pixel) 65,536 colors * st Transfer 4 3 nd Transfer 4 3 R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system 8-bit interface (3 transfers/pixel) 6,44 colors st Transfer nd Transfer 4 3 3rd Transfer 4 3 R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 8-system 8-bit interface (3 transfers/pixel) 6,44 colors st Transfer 4 3 nd Transfer 4 3 3rd Transfer 4 3 R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 5 8-bit System Interface ata Format Page 3 of 5 Version:

31 73 Serial Peripheral Interface (SPI) 73 -bit 4 wires Serial Peripheral Interface The Serial Peripheral Interface (SPI) is selected by setting the IM[3:] pins as x level The chip select pin (ncs), the serial transfer clock pin (SCL), the serial data input pin (SI) and the serial data output pin (SO) are used in SPI mode The I pin sets the least significant bit of the identification code The [:] pins, which are not used, must be tied to GN The SPI interface operation enables from the falling edge of ncs and ends of data transfer on the rising edge of ncs The start byte is transferred to start the SPI interface and the read/write operation and RS information are also included in the start byte When the start byte is matched, the subsequent data is received by The seventh bit of start byte is RS bit When RS =, either index write operation or status read operation is executed When RS =, either register write operation or RAM read/write operation is executed The eighth bit of the start byte is used to select either read or write operation (R/W bit) ata is written when the R/W bit is and read back when the R/W bit is After receiving the start byte, starts to transfer or receive the data in unit of byte and the data transfer starts from the MSB bit All the registers of the are -bit format and receive the first and the second byte datat as the upper and the lower eight bits of the -bit register respectively In SPI mode, 5 bytes dummy read is necessary and the valid data starts from 6 th byte of read back data Start Byte Format Transferred bits S Start byte format Transfer start evice I code RS R/W I / / Note: I bit is selected by setting the IM/I pin RS and R/W Bit Function RS R/W Function Set an index register Read a status Write a register or GRAM data Read a register or GRAM data Page 3 of 5 Version:

32 S e ria l P e riphe ra l Inte rfa ce for re gis te r a cce s s S P I Input a ta Register a ta IB IB 4 IB 3 IB IB IB IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB IB IB S e ria l P e riphe ra l Inte rfa ce 65K colors Input a ta Write a ta Register GRAM a ta RGB ma pping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 6 ata Format of SPI Interface Page 3 of 5 Version:

33 (a) Basic data transmission through SPI ncs (Input) Start End SCL (Input) SI (Input) I RS RW Start Byte Index register, registers setting, and GRAM write SO (Output) Status, registers read and GRAM read (b) Register write through SPI Start End ncs (Input) SCL (Input) SI (Input) Start Byte Register index upper eight bits Register index lower eight bits Start Byte Parameter upper eight bits Parameter lower eight bits Note: The first byte after the start byte is always the upper eight bits (c) Consecutive data transmission through SPI ncs (Input) Start End SCL (Input) SI (Input) Start Byte Pixel (Parameter ) upper eight bits Pixel (Parameter ) lower eight bits Pixel (Parameter ) upper eight bits Pixel (Parameter ) lower eight bits Note: The first byte after the start byte is always the upper eight bits Figure 7 ata transmission through serial peripheral interface (SPI) () Page 33 of 5 Version:

34 (d) GRAM data read transmission Start ncs (Input) End SCL (Input) SI (Input) Start Byte RS=, RW= SO (Output) ummy read ummy read ummy read 3 ummy read 4 ummy read 5 RAM read upper byte RAM read lower byte Note: Five bytes of invalid dummy data read after the start byte (e) Status/registers read transmission Start ncs (Input) End SCL (Input) SI (Input) Start Byte SO (Output) ummy read Parameter upper eight bits Parameter lower eight bits Note: One byte of invalid dummy data read after the start byte Figure 8 ata transmission through serial peripheral interface (SPI) () Page 34 of 5 Version:

35 73 3-wire 9-bit Serial Interface This SPI mode uses a 3-wire 9-bit serial interface The chip-select ncs (active low) enables and disables the serial interface SCL is the serial data clock and SA is serial data Serial data must be input to SA in the sequence /CX, 7 to The reads the data at the rising edge of SCL signal The first bit of serial data /CX is data/command flag When /CX = "", 7 to bits are display RAM data or command parameters When /CX = "" 7 to bits are commands Register Write Mode: Using the 9-bit serial interface to write register parameter or GRAM data, the register R66h must be set as (R66h default = ) nc S SC L S A /CX () /CX () /CX () /CX=: Register Index (command) /CX=: Register parameter or GRAM data +8 bits Command +8 bits ata (High Byte) +8 bits ata (Low Byte) +8 bits Command +8 bits ata (High Byte) +8 bits ata (Low Byte) Register Read Mode: When users need to read back the register parameter or GRAM data, the register R66h must be set as first, and then write the register index to read back the register parameter or GRAM data The following timing diagrams show examples to read back the register parameter ncs SCL SA (Host) /CX () SA (river IC) ummy data read byte => for register read 5 bytes => for GRAM data read -bit register parameter or -pixel GRAM data (65K colors) Page 35 of 5 Version:

36 ncs SCL SA (Host) /CX () SA (river IC) 7 6 ummy data byte data dummy read before register parameter read 5 byte data dummy read before GRAM data read -bit register parameter or -pixel GRAM data (65K colors) Note:One byte of invalid dummy data read is needed before register parameter read Five bytes of invalid dummy data read is needed before GRAM data read 3-Wire Serial Interface and GRAM ata Stream (65K colors) (Set TRI =, FM =) ncs SCL SA /CX () R 4 R 3 R R R G 5 G 4 G 3 /CX () G G G B 4 B 3 B B B /CX () R 4 R 3 R R R G 5 G 4 G 3 /CX () G G G 3-Wire Serial Interface and GRAM ata Stream (6K colors) (Set TRI =, FM =) ncs SCL SA /CX () R 5 R 4 R 3 R R R - - /CX () G 5 G 4 G 3 G G G - - /CX () B 5 B 4 B 3 B B B - - /CX () R 5 R 4 R 3 Page 36 of 5 Version:

37 733 4-wire 8-bit Serial Interface This SPI mode uses a 4-wire 8-bit serial interface The chip-select ncs (active low) enables and disables the serial interface /CX is the command or data select signal, SCL is the serial data clock and SA is serial data Serial data must be input to SA in the sequence 7 to The reads the data at the rising edge of SCL signal The /CX signal indicates data/command When /CX = "", 7 to bits are display RAM data or command parameters When /CX = "" 7 to bits are commands Register Write Mode: Using the 8-bit serial interface to write register parameter or GRAM data, the register R66h must be set as (R66h default = ) ncs RS (/CX) Register Index (Command) Register Parameter or GRAM ata SCL SA RS(/CX) = (low): Register Index (command) RS(/CX)= (high): Register parameter or GRAM data Register Read Mode: When users need to read back the register or GRAM data, the register R66h must be set as first, and then write the register index to read back the register or GRAM data The following timing diagrams show examples to read back the register parameter or GRAM data ncs RS (/CX) SCL SA (Host) SA (river IC) ummy data read byte => for register read 5 bytes => for GRAM data read -bit register parameter or -pixel GRAM data (65K colors) Page 37 of 5 Version:

38 ncs RS (/CX) SCL SA (Host) SA (river IC) 7 6 ummy data byte data dummy read before register parameter read 5 byte data dummy read before GRAM data read -bit register parameter or -pixel GRAM data (65K colors) Note:One byte of invalid dummy data read is needed before register parameter read Five bytes of invalid dummy data read is needed before GRAM data read 4-Wire Serial Interface and GRAM ata Stream (65K colors) (TRI =, FM =) ncs RS (/CX) SCL SA R 4 R 3 R R R G 5 G 4 G 3 G G G B 4 B 3 B B B R 4 R 3 R R R G 5 G 4 G 3 G G G B 4 B 3 B B 4-Wire Serial Interface and GRAM ata Stream (6K colors) (TRI =, FM =) ncs RS (/CX) SCL SA R 5 R 4 R 3 R R R - - G 5 G 4 G 3 G G G - - B 5 B 4 B 3 B B B - - R 5 R 4 R 3 R R R - Page 38 of 5 Version:

39 74 VSYNC Interface supports the VSYNC interface in synchronization with the frame-synchronizing signal VSYNC to display the moving picture with the i8 system interface When the VSYNC interface is selected to display a moving picture, the minimum GRAM update speed is limited and the VSYNC interface is enabled by setting M[:] = and RM = VSYNC MPU ncs RS nwr [:] Figure 9 ata transmission through VSYNC interface) In the VSYNC mode, the display operation is synchronized with the internal clock and VSYNC input and the frame rate is determined by the pulse rate of VSYNC signal All display data are stored in GRAM to minimize total data transfer required for moving picture display VSYNC Write data to RAM through system interface isplay operation synchronized with internal clocks Rewriting screen data Rewriting screen data Figure Moving picture data transmission through VSYNC interface Page 39 of 5 Version:

40 VSYNC Back porch (4 lines) RAM Write isplay operation isplay (3 lines) Front porch ( lines) Black period Figure Operation through VSYNC Interface The VSYNC interface has the minimum speed limitation of writing data to the internal GRAM via the system interface, which are calculated from the following formula Internal clock frequency (fosc) [Hz] = FrameFrequency x (isplayline (NL) + FrontPorch (FP) + BackPorch (BP)) x ClockCyclePerLines (RTN) x FrequencyFluctuation Minimum RAM write speed ( HZ ) 4 x isplaylines ( NL ) [( BackPorch ( BP )+ isplaylines ( NL ) - margins ] x ( clocks ) x / fosc Note: When the RAM write operation does not start from the falling edge of VSYNC, the time from the falling edge of VSYNC until the start of RAM write operation must also be taken into account An example of minimum GRAM writing speed and internal clock frequency in VSYNC interface mode is as below [Example] isplay size: 4 RGB 3 lines Lines: 3 lines (NL = ) Back porch: 4 lines (BP = ) Front porch: lines (FP = ) Frame frequency: 6 Hz Frequency fluctuation: % Page 4 of 5 Version:

41 Internal oscillator clock (fosc) [Hz] = 6 x [3+ + 4] x clocks x (/9) 394KHz When calculate the internal clock frequency, the oscillator variation is needed to be taken into consideration In the above example, the calculated internal clock frequency with ±% margin variation is considered and ensures to complete the display operation within one VSYNC cycle The causes of frequency variation come from fabrication process of LSI, room temperature, external resistors and VCI voltage variation Minimum speed for RAM writing [Hz] > 4 x 3 x 394K / [ (4 + 3 )lines x clocks] 57 MHz The above theoretical value is calculated based on the premise that the starts to write data into the internal GRAM on the falling edge of VSYNC There must at least be a margin of lines between the physical display line and the GRAM line address where data writing operation is performed The GRAM write speed of 57MHz or more will guarantee the completion of GRAM write operation before the starts to display the GRAM data on the screen and enable to rewrite the entire screen without flicker Notes in using the VSYNC interface The minimum GRAM write speed must be satisfied and the frequency variation must be taken into consideration The display frame rate is determined by the VSYNC signal and the period of VSYNC must be longer than the scan period of an entire display 3 When switching from the internal clock operation mode (M[:] = ) to the VSYNC interface mode or inversely, the switching starts from the next VSYNC cycle, ie after completing the display of the frame 4 The partial display, vertical scroll, and interlaced scan functions are not available in VSYNC interface mode and set the AM bit to to transfer display data Page 4 of 5 Version:

42 System Interface Mode to VSYNC interface mode System Interface VSYNC interface mode to System Interface Mode Opeartion through VSYNC interface Set AM= Set GRAM Address Set M[:]=, RM= for VSYNC interface mode Set index register to Rh Wait more than frame Write data to GRAM through VSYNC interface isplay operation in synchronization with internal clocks M[:], RM become enable after completion of displaying frame isplay operation in synchronization with VSYNC Set M[:]=, RM= for system interface mode Wait more than frame System Interface isplay operation in synchronization with VSYNC M[:], RM become enable after completion of displaying frame isplay operation in synchronization with internal clocks Note: input VSYNC for more than frame period after setting the M, RM register Opeartion through VSYNC interface Figure Transition flow between VSYNC and internal clock operation modes Page 4 of 5 Version:

43 75 RGB Input Interface The RGB Interface mode is available for and the interface is selected by setting the RIM[:] bits as following table RIM RIM RGB Interface pins 8-bit RGB Interface [:] -bit RGB Interface [:3], [:] 6-bit RGB Interface [:] Setting prohibited 8-bit RGB Inte rfa ce (6 6K colors ) Input a ta Write a ta Re gis te r GRAM a ta & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B -bit RGB Inte rfa ce (65K colors ) Input a ta Write a ta Re gis te r GRAM a ta & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B 6-bit RGB Inte rfa ce (6 K colors ) Input a ta st Trans fer 4 3 nd Transfer 4 3 3rd Transfer 4 3 Write a ta Re gis te r GRAM a ta & RGB Mapping R5 R4 R3 R R R G5 G4 G3 G G G B5 B4 B3 B B B Figure 3 RGB Interface ata Format Page 43 of 5 Version:

44 75 RGB Interface The display operation via the RGB interface is synchronized with the VSYNC, HSYNC, and OTCLK signals The RGB interface transfers the updated data to GRAM and the update area is defined by the window address function The back porch and front porch are used to set the RGB interface timing VSYNC Back porch period (BP[3:]) RAM data display area Moving picture display area isplay period (NL[4:] Front porch period (FP[3:]) HSYNC OTCLK ENABLE [:] Note : Front porch period continues until the next input of VSYNC Note : Input OTCLK throughout the operation Note 3: Supply the VSYNC, HSYNC and OTCLK with frequency that can meet the resolution requirement of panel Figure 4 GRAM Access Area by RGB Interface Page 44 of 5 Version:

45 75 RGB Interface Timing The timing chart of 8-/-bit RGB interface mode is shown as follows frame Back porch Front porch VSYNC VLW >= H HSYNC OTCLK ENABLE [:] HSYNC HLW >= 3 OTCLK // H OTCLK // TST >= HLW ENABLE // [:] Valid data VLW: VSYNC low period HLW: HSYNC low period TST: data transfer startup time Figure Timing Chart of Signals in 8-/-bit RGB Interface Mode Page 45 of 5 Version:

46 The timing chart of 6-bit RGB interface mode is shown as follows Figure Timing chart of signals in 6-bit RGB interface mode Page 46 of 5 Version:

47 753 Moving Picture Mode has the RGB interface to display moving picture and incorporates GRAM to store display data, which has following merits in displaying a moving picture The window address function defined the update area of GRAM Only the moving picture area of GRAM is updated When display the moving picture in RGB interface mode, the [:] can be switched as system interface to update still picture area and registers, such as icons RAM access via a system interface in RGB-I/F mode allows GRAM access via the system interface in RGB interface mode In RGB interface mode, data are written to the internal GRAM in synchronization with OTCLK and ENABLE signals When write data to the internal GRAM by the system interface, set ENABLE to terminate the RGB interface and switch to the system interface to update the registers (RM = ) and the still picture of GRAM When restart RAM access in RGB interface mode, wait one read/write cycle and then set RM = and the index register to Rh to start accessing RAM via the RGB interface If RAM accesses via two interfaces conflicts, there is no guarantee that data are written to the internal GRAM The following figure illustrates the operation of the when displaying a moving picture via the RGB interface and rewriting the still picture RAM area via the system interface Still Picture Area Moving Picture Area Update a frame Update a frame VSYNC ENABLE OTCLK [:] Set IR to Rh Update moving picture area Set RM= Set A[:] Set IR to Rh Update display data in other than the moving picture area Set A[:] Set RM= Set IR to Rh Update moving picture area Figure Example of update the still and moving picture Page 47 of 5 Version: