The process. Sensitivity lists

The process process itself is a concurrent statement but the code inside the process is executed sequentially Process label (optional) Process declarative region Process body entity Test is, : in bit; X, : out bit); end Test; architecture Proc of Test is P1: process (, ) -- signal declarations not allowed if = 1 and = 0 then X <= ; <= 1 ; X <= ; <= 0 ; end Proc; Sensitivity list Process is activated whenever an event occurs on signal or Statements in the process body are executed sequentially! 0 1 X Sensitivity lists For a process that models combinational logic, the sensitivity list must be complete! ll signals that are read ( inputs to the process) must be in the sensitivity list. What does this process model? process() <= or or or ; Our synthesis tool Synplify will assume that the sensitivity list is complete. The function of the synthesized logic will not match the function of the VHL model you simulated. Process execution and suspension process is executed with its initial conditions until it reaches a wait statement. In the wait statement the process suspends and updates signals that has been assigned new values. In the code below, the process resumes whenever there is an event on either or P1 : process 1 <= or ; 2 <= and ; wait on, ; This form of process is so common that there exist a shorthand notation P1 : process(, ) We We always always use use 1 <= or ; the the shorthand shorthand 2 <= and ; notation! notation! Multiple processes interact concurrently entity Test is port (, : in bit; X, : out bit); end Test; architecture Proc of Test is signal Internal : bit; P1 : process (, ) if = '1' and = then X <= ; Internal <= ; X <= ; Internal <= '1'; P2 : process (,, Internal) if Internal = '1' then <= ; <= ; end process P2; end Proc; Process 1 Process 2 Each process execute its statements sequentially. Each process execute when there is an event on one of the signals on its sensitivity list. This may cause an event on another signal that triggers another process and another 0 1 0 1 X

The process itself is a concurrent statement architecture RTL of Nisse is P1 : process (, ) S <= xor ; end RTL; Two equivalent descriptions architecture RTL of Nisse is P1 : S <= xor ; end RTL; ou may (should) label processes, Ss (concurrent signal assignments) etc. Useful for debugging and understanding tool outputs. oncurrent vs. sequential execution architecture oncurrent of Test is <= or ; <= and ; end oncurrent;? Resolution function Synplify will report errors! Multiple non-tristate drivers for net architecture Sequential of Test is process (,,, ) <= or ; <= and ; end process ; end Sequential; signal that is assigned to within a process is not updated until the process is suspended. The two architectures are not equivalent. The signal is updated with the last value assigned to it Signals Signal attributes Holds a list of values, which include the current value, past value and a set of possible scheduled values that are to appear on the signal. Future values can be assigned to the signal using the signal assignment operator. signal shiftreg : std_logic_vector(7 downto 0); shiftreg <= shiftreg(6 downto 0) & Input; May be assigned initial values when declared: signal ount : std_logic_vector(3 downto 0) := 0101 ; ut this is not meaningful for synthesis! Signals can represent wires and memory holders (flip-flops, latches). S delayed(t) S stable(t) S quiet(t) S transaction S event S active S last_event S last_active S last_value signal that takes the same value as S but is delayed by time T oolean signal that is true if there has been no event on S in the time interval T up to current time, otherwise false oolean signal that is true if there has been no transaction on S in the time interval T up to current time, otherwise false signal of type bit that changes value from 0 to 1 or vice versa if there is an transaction on S True if there is an event on signal S in the current simulation cycle otherwise false True if there is a transaction on signal S in the current simulation cycle otherwise false The time interval since the last event on S The time interval since the last transaction on S The value of S just before the last event on S

Signal declaration Internal signals Internal signals can be declared in the declarative region of the architecture entity Test is, : in bit; X, : out bit); end Test; architecture Internal of Test is signal Int : bit; Int <= xor ; X <= not Int ; <= Int and ; end Internal; Internal signal can be read and be assigned new values. X and is not readable! Int X Variables variable is locally declared in a process or subprograms and can only be used locally. Variables are more abstract compared to signals. Variable assignments are immediately and not scheduled. variable ShiftReg : std_logic_vector(7 downto 0); Shiftreg := shiftreg(6 downto 0) & Input; Use variable whenever possible since a variable uses less simulation resources than a signal. Variables do not have histories. Variable declaration Variables in processes variable is declared inside the process and is not visible outside the process. variable is updated immediately. Retains its value through the simulation architecture Var of Test is process(,,, ) variable Temp : std_logic; temp := ; temp := temp xor ; temp := temp xor ; temp := temp xor ; temp := temp xor ; <= temp; end Var; Some common concurrent and sequential statements Sequential oncurrent If-then- Process statement ase When- Variable declaration With-select Variable assignment Signal declaration Loop lock statement Null omponent instantiation Wait Return oth Sequential and oncurrent Signal assignment eclaration of types and constants Function and procedure calls ssert statement fter Signal attributes

If-then- SE if = then if = then S <= 1; elsif = then S <= 2; S <= 3; The if statement corresponds to the concurrent statement when- signal Nisse : std_logic_vector(1 downto 0);... process(nisse) case Nisse is when 00 01 => O <= 1; when 10 11 => O <= S1; when others => O <= X ; end case; The others clause is needed as all possible representations of Nisse must be covered SE Four different ways of modeling a 4-1 Mux type States is (Idle, S0, S1); signal PresentState, NextState : States;... process(presentstate) case PresentState is when Idle => NextState <= S0; when S0 => NextState <= S1; when S1 => NextState <= Idle; end case; No others clause is needed as all possible representations of PresentState is covered M1 : process(,,,, Sel) if Sel = "00" then 1 <= ; elsif Sel = "01" then 1 <= ; elsif Sel = "10" then 1 <= ; elsif Sel = "11" then 1 <= ; 1 <= 'X'; -- oncurrent M2 : 2 <= when Sel = "00" when Sel = "01" when Sel = "10" when Sel = "11" 'X'; M3 : process(,,,, Sel) case Sel is when "00" => 3 <= ; when "01" => 3 <= ; when "10" => 3 <= ; when "11" => 3 <= ; when others => 3 <= 'X'; end case; -- oncurrent M4 : with Sel select 4 <= when "00", when "01", when "10", when "11", 'X' when others;

WIT process may be suspended by means of a sensitivity list. sensitivity list is an implicit wait statement. When a process have a sensitivity list it always suspends after executing the last sequential statement and then the signals that have been assign new values are updated. The wait statement provides an alternative form for suspending a process. Examples wait until a = 1; -- a = 1 and a event wait on a, b; -- a event or b event wait for 10 ns; Three kinds of loop statements Loops [ label: ] loop sequence-of-statements -- use exit statement to get out end loop [ label ] ; [ label: ] for variable in range loop sequence-of-statements end loop [ label ] ; [ label: ] while condition loop sequence-of-statements end loop [ label ] ; Exit statement may be used in a loop to immediately exit the loop [ label: ] exit [ label2 ] [ when condition ] ; Next statement may be used in a loop to cause next iteration [ label: ] next [ label2 ] [ when condition ] ; entity Ex is : in bit_vector(7 downto 0); O1 : out bit; O2 : out bit ); end Ex; architecture Loppa of Ex is process () variable temp : bit; temp := ; L1 : for i in 'range loop temp := temp xor (i); end loop; O1 <= temp; temp := ; L2 : for i in 'range loop next L2 when i = 2; temp := temp xor (i); end loop; O2 <= temp; [7:0] [7:0] end Loppa; [7] [6] [5] [4] LUT4_6996 G_9_5 Loops While loops are not supported for synthesis and the range in for loops needs to be statically defined - known at compile time. We need to generate a fixed amount of hardware. [3] [1] [0] LUT4_6996 G_9 [2] LUT2_6 O1_0_and2 O1 O2 Modeling combinational logic Multiplexers Encoders Priority encoders ecoders

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Encoder is : in unsigned(7 downto 0); : out unsigned(2 downto 0)); end Encoder; architecture Logic1 of Encoder is with select <= "000" when 1, "001" when 2, "010" when 4, "011" when 8, "100" when 16, "101" when 32, "110" when 64, "111" when 128, "XXX" when others; end Logic1; 8-3 binary encoder Note Note the the use use of of numeric_std numeric_stdand and unsigned unsigned architecture Logic of Encoder is P1: process() if = "00000001" then <= "000"; elsif = "00000010" then <= "001"; elsif = "00000100" then <= "010"; elsif = "00010000" then <= "011"; elsif = "00010000" then <= "100"; elsif = "00100000 then <= "101"; elsif = "01000000" then <= "110"; elsif = "10000000" then <= "111"; <= "XXX"; end Logic; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; 8-3 binary encoder entity Encoder is : in unsigned(7 downto 0); : out unsigned(2 downto 0)); end Encoder; architecture Logic2 of Encoder is P1 : process() <= "XXX"; L1: for i in 0 to 7 loop if = 2**i then <= to_unsigned(i, 3); end loop L1; end Logic2; More More compact code. code. Must Must have have default default assignment <= <= "XXX"; or or latches latches will will be be inferred. Priority encoder architecture L2 of PriEncoder is P1: process() variable Temp : integer; Valid <= '1'; Temp := to_integer(); case Temp is when 8 to 15 => <= "11"; when 4 to 7 => <= "10"; when 2 to 3 => <= "01"; when 1 => <= "00"; when others => Valid <= ; <= "XXX"; end case; end L2; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity PriEncoder is : in unsigned(3 downto 0); : out unsigned(1 downto 0); Valid : out std_logic); end PriEncoder; architecture L1 of PriEncoder is architecture L3 of PriEncoder is P1: process() P1 : process() Valid <= '1'; <= "XXX"; if (3) = '1' then Valid <= ; <= "11"; for i in 'range loop elsif (2) = '1' then if (i) = '1' then <= "10"; <= to_unsigned(i, 2); elsif (1) = '1' then Valid <= '1'; <= "01"; exit; elsif (0) = '1' then <= "00"; end loop; Valid <= ; end L3; <= "XXX"; end L1; Inefficient Inefficient for for synthesis synthesis infers infers comparators comparators VHL simulation In order to write VHL code that simulate and synthesize well we must understand how VHL code is executed How does the tools in the lab actually work? good book on VHL is esigners Guide to VHL by Peter shenden. The next few following slides are adapted from VHL Quick Start Guide by shenden

nalysis (ncvhdl) heck for syntax and semantic errors» syntax: grammar of the language» semantics: the meaning of the model nalyze each design unit separately» entity declaration» architecture body» etc» best if each design unit is in a separate file nalyzed design units are placed in a library» current library is called work Elaboration (ncelab) Flattening the design hierarchy» create ports» create signals and processes within architecture body» for each component instance, copy instantiated entity and architecture body» repeat recursively bottom out at purely behavioral architecture bodies (no component instantiations) Final result of elaboration» flat collection of signal nets and processes Simulation (ncsim) Execution of the processes in the elaborated model iscrete event simulation» time advances in discrete steps» when signal values change events processes is sensitive to events on input signals» specified in wait statements» a process sensitivity list is an implicit wait statement» resumes and schedules new values on output signals schedules transactions (transaction, an input change that may lead to an event) event on a signal if new value different from old value Initialization phase Simulation algorithm» each signal is given its initial value (start value from declaration or first value from type definition type left)» simulation time set to 0» for each process (a concurrent signal assignment is in fact a process) activate execute until a wait statement, then suspend since a sensitivity list is an implicit wait statement a process with a wait statement suspends at the end of the process execution usually involves scheduling transactions on signals for later times

Simulation cycle Simulation algorithm» advance simulation time to time of next transaction» for each transaction at this time update signal value event if new value is different from old value» for each process sensitive to any of these events, or whose wait for time-out has expired resume execute until a wait statement, then suspend Simulation finishes when there are no further scheduled transactions elta delays delta delay can be thought of as an infinitesimal unit of time orthogonal to simulation time Zero delays are modeled as delta delays, so that any events generated with zero delay are scheduled to occur one delta delay later. elta delays are used to order events elta Time Simulation - an example ombinational feedback loops architecture sim of Test is signal,,, : std_logic := 0 ; signal S1, S2, : std_logic; <= 0 after 5 ns, 1 after 10 ns; <= 1 after 5 ns; <= 0 after 5 ns, 1 after 10 ns; <= 1 after 5 ns; S1 <= xor ; S2 <= xor ; <= S1 and S2; end Sim; S1 S2 '1' 10ns '1' 10ns '1' '1' 5ns 5ns 5ns 5ns In a synchronous design combinational feedback loops must be avoided. (There are some rare exceptions though.) ssume S = 0 and = 1. What will happen in simulation? S <= S xor ; t (ns) S1 S2 0 +0 0 0 0 0 U U U 0 +1 0 0 0 0 0 0 U 0 +2 0 0 0 0 0 0 0 5 +0 0 1 0 1 0 0 0 5 +1 0 1 0 1 1 1 0 5 +2 0 1 0 1 1 1 1 10 +0 1 1 1 1 1 1 1 10 +1 1 1 1 1 0 0 1 10 +2 1 1 1 1 0 0 0 Simulation will never advance in time! S

When should we simulate? VHL RTL description RTL simulation VHL testbench Emacs - design entry adence N VHL Synthesis library RTL synthesis Structural VHL Structural simulation Synplify Pro Simulation library EIF netlist Xilinx lliance Place and route. ack annotation SF timing information. Structural VHL Simulation library Timing simulation adence N VHL onfiguration data Netlist with delay information Static timing analysis Xilinx lliance