ECE4401 / CSE3350 ECE280 / CSE280 Digital Design Laboratory

Transcription

1 ECE4401 / CSE3350 ECE280 / CSE280 Digital Design Laboratory

2 Instructor John Chandy Office: ITEB 437 Office Hours: W10-12 Tel: (860) Class home page: HuskyCT

3 TA Ajith Thamarakuzhi Office: BECAT A65 Office Hours: W2-5 Tel: (860) uconn.edu

4 Grading Labs: 60 % Quizzes: 10 % Final Design Project : 30 %

5 Course Requirements References: Circuit Design with VHDL, Volnei Pedroni,, MIT Press. VHDL Starter s s Guide, Sudhakar Yalamanchili The Student s s Guide to VHDL, Peter J. Ashenden, Morgan Kaufmann Computer Software: Xilinx ISE with Modelsim Available from xilinx.com/ise/logic_design_prod/webpack.htm

6 What is a Digital System? A collection of interconnected digital modules designed to perform a particular service or function Applications Computers Microprocessors Embedded Systems - appliances, automobiles Special purpose - military chips, high performance computing

7 Digital Systems High Level Digital Modules Microprocessors/Microcontrollers PLDs ASICs Low Level Digital Modules Gates - AND, OR, NOR, etc. Blocks - Adder, subtractor,, shifter, etc.

8 Digital Systems Implementations PCB - printed circuit board FPGA - field programmable gate array VLSI - very large scale integration SoC - system on a chip

9 Digital Systems Printed Circuit Board

10 Digital Systems FPGA Digilent PCB using Xilinx FPGA

11 Digital Systems ASIC Intel Pentium IV

12 Digital Systems SoC Reusable IP Embedded processor cores Philips Nexperia PNX831 Set Top Digital Video Chip

13 Field Programmable Gate Array (FPGA) Basics Collection of programmable gates embedded in a flexible interconnect network. a user programmable alternative to gate arrays.? Programmable Gate

14 FPGA Basics LUT for compute FF for timing/retiming Programmable interconnect Everything we need to build fixed logic circuits latches can be built from gates

15 Look-Up Table (LUT) In Out Mem Out 2-LUT In1 In2

16 What is Digital Systems Design? Digital Systems Design is a process that entails a systematic development of an idea into an architecture that can be implemented digitally. Design Specification Architecture Verify Implement Hardware

17 Hardware Description Languages Two primary choices VHDL (VHSIC (Very high-speed IC) hardware description language) Verilog HDL Can be used for behavioral specification, architectural definition, implementation, and verification Other HDLs used in specific areas include SystemC, HandelC, Rosetta

18 VHDL Overview Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL): Modeling of digital systems Concurrent and sequential statements Machine-readable specification Man- and machine-readable documentation International Standards: IEEE Std IEEE Std

19 Concepts of VHDL Execution of assignments: Sequential: Executed one after another, like in software programming languages. Can override the effects of previous statements. Concurrent: Active continuously. The order of statements is not relevant. Suited to model the parallelism of hardware.

20 Concepts of VHDL Methodologies: Abstraction: description of different parts of a system. On every abstraction level, only the essential information is considered, nonessential information is left out. Modularity: : split big functional blocks and to write a model for each part. Hierarchy: build a design out of submodules.. Each level of hierarchy may contain modules of different abstraction levels.

21 Digital Systems Modeling Gajski and Kuhn Y Chart Behavioral/Functional Architectural Algorithmic Structural Processor Systems Functional Block Hardware Modules Algorithms Logic ALUs, Registers Register Transfer Circuit Gates, FFs Logic Transfer Functions Transistors Rectangles Cell, Module Plans Floor Plans (Adapted from RASSP Module 10, Slide 11) Clusters Physical Partitions Physical/Geometry

22 Abstraction levels in Digital Design Behavioral level: Functional description of the model is outlined. No system clock and signal transitions are asynchronous with respect to the switching time. Simulation only, but typically not synthesizable.

23 Abstraction levels in Digital Design Register level (RTL): The design is divided into combinational logic and storage elements. Storage elements (Flip-Flops, latches) are controlled by a system clock. Synthesizable. Logic level: The design is represented as a netlist with logic gates (AND, OR, NOT,...) and storage elements.

24 VHDL Language & Syntax (General) Example VHDL Code signal mysignal: bit; Signal assignment: ' <= ' User defined names: Letters, numbers, underscores. Start with a letter. No VHDL keyword may be used. -- an example signal MYsignal <= '0', -- start with '0' '1' after 10 ns, -- and toggle '0' after 10 ns, -- every 10 ns '1' after 10 ns; Case insensitive Comments: '--' until end of line Statements are terminated by ';' (may span multiple lines) List delimiter: ','

25 VHDL Language & Syntax (Identifier) MySignal_23 -- normal identifier Normal Identifier: rdy, RDY, Rdy -- identical identifiers Letters, numbers, underscores vector_&_vector -- X : special character last of Zout -- X : white spaces Uppercase and lowercase letters are equivalent when used in identifiers (Case insensitive) idle state -- X : consecutive underscores 24th_signal -- X : begins with a numeral The first character must be a letter. open, register -- X : VHDL keywords The last character cannot be an underscore. \mysignal_23\ -- extended identifier \rdy\, \RDY\, \Rdy\ -- different identifiers \vector_&_vector\ -- legal \last of Zout\ -- legal \idle state\ -- legal \24th_signal\ -- legal \open\, \register\ -- legal No two consecutive underscores. VHDL reserved words may not be used as identifiers. Extended Identifier (VHDL93) Enclosed in back slashes Case sensitive Graphical characters allowed May contain spaced and consecutive underscores. VHDL keywords allowed

26 Legal and Illegal Identifiers Legal Identifiers: Uconn_huskies ECE_252 Sel6B Illegal Identifiers: _time_is_9am -- an identifier must start with a letter. 8thsemester -- an identifier must start with a letter. Homework#1 -- letter, digits, and underscore only. final example -- two underscore in succession not allowed Entity -- keyword cannot be used as identifier Time_out_ -- last character cannot be an underscore.

27 VHDL Reserved Words VHDL Reserved Words xor xor signal signal is is xnor xnor shared shared out out inout inout constant constant with with severity severity others others inertial inertial configuration configuration while while select select or or in in component component when when ror ror open open impure impure case case wait wait rol rol on on if if bus bus variable variable return return of of guarded guarded buffer buffer use use report report null null group group body body until until rem rem not not generic generic block block units units reject reject nor nor generate generate begin begin unaffected unaffected register register next next function function attribute attribute type type record record new new for for assert assert transport transport range range nand nand file file array array to to pure pure mod mod exit exit architecture architecture then then protected protected map map entity entity and and subtype subtype process process loop loop end end all all srl srl procedure procedure literal literal elsif elsif alias alias sra sra postponed postponed linkage linkage else else after after sll sll port port library library downto downto access access sla sla package package label label disconnect disconnect abs abs

28 VHDL Structural Elements Entity: description of interface consisting of the port list. Architecture: description of the function of the corresponding module. Configuration: used for simulation purposes. Process: allows for a sequential execution of the assignments. Package: hold the definition of commonly used data types, constants and subprograms. Library: the logical name of a collection of compiled VHDL units (object code). Mapped by the simulation or synthesis tools.

29 Entity statement entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit); end HALFADDER; entity ADDER is port( A, B: in integer range 0 to 3; SUM: out integer range 0 to 3; CARRY: out bit ); end entity ADDER; Interface description Linking via port signals Data types Signal width Signal direction Port clause identifies ports used by "entity" to communicates with its environment.

30 Entity Port Modes in: signal values are read-only out: signal values are write-only multiple drivers buffer: comparable to out signal values may be read as well only 1 driver inout: bidirectional port

31 Architecture Body Statement entity HALFADDER is port( A, B: in bit; SUM, CARRY: out bit); end HALFADDER; -- Architecture body -- "Hadd" is user defined name architecture Hadd of HALFADDER is begin SUM <= A xor B; CARRY <= A and B; end RTL; end architecture Hadd ; An architecture defines an entity's behavior from a simulation point of view. Implementation of design Always connected with a specified entity One entity can have several architectures Entity ports are available as signals within the architecture. Contains concurrent statements.

32 Architecture Body Structure -- architecture Body Declarative part: architecture EXAMPLE of STRUCTURE is data types -- Declarative part subtype DIGIT is integer range 0 to constants 9; additional signals ("actual" constant BASE: integer := 10; signals) signal DIGIT_A, DIGIT_B: DIGIT; components signal CARRY: DIGIT;... begin -- Statement part DIGIT_A <= 3; SUM <= DIGIT_A + DIGIT_B; DIGIT_B <= 7; CARRY <= 0 when SUM < BASE else 1; end EXAMPLE ; Statement part (after 'begin'): signal assignments processes component instantiations concurrent statements can be placed within the statement part..

33 Data Objects Data objects hold a value of specified type. They belong to one of three classes: Constants Signals Variables Must be declared before they are used Signals are typically used to model wires and flip-flops, while constants and variables are typically used to model the behavior of the circuit.

34 Signals Signal data objects represent the logic signals or wires in a circuit. Signals can also represent the state of a memory There are three places in which signals can be declared in a VHDL code In an entity declaration In the declarative part of an architecture In the declarative part of a package.

35 Signals A signal has to be declared with an associated TYPE as follows: SIGNAL signal_name : type_name; The signal s type_name determines the legal values that the signal can have and its legal use in VHDL code. Signal types: (1) bit (2) bit_vector (3) std_logic (4) std_logic_vector (5) std_ulogic (6) signed (7) unsigned (8) integer (9) enumeration (10) boolean

36 Logic Operators and, or, xor, xnor, nand,, nor, not Example: Z <= A and B and C; Z <= (not( A and B) or (A and not B);

37 Concurrency VHDL concurrent statements execute in a concurrent fashion. That is, statements execute only when associated signals change value. There is no master, procedural flow of control; each concurrent statement execute in a nonprocedural stimulus/response. ENTITY example1 IS PORT (x1, x2, x3 : IN f : OUT END example1; BIT; BIT); ARCHITECTURE logicfunc OF example1 IS SIGNAL a1, b2: BIT; BEGIN -- Concurrent signal assignment statements a1 <= x1 AND x2; b1 <= NOT x2 AND x3; f <= a1 NOR b1; END logicfunc;

38 Process Statement PROCESS statement: basic building block for behavioral modeling of digital systems. concurrent shell in which a sequential statement can be executed. appears inside an architecture body, and it encloses other statements within it. IF, CASE,, and LOOP statements can appear only inside a process. All statements with a process are executed sequentially when the process becomes active.

39 Process Statement Format [Process_label]] : PROCESS [(sensitivity_list sensitivity_list)] Process_declarative_region BEGIN process_statement_region END PROCESS [Process_label] The keyword PROCESS in the first line is the beginning delimiter of the process. The optional label allows for a user_defined name for the process. The END PROCESS is the ending delimiter of the process statement. If the label is included in the END PROCESS clause, it must match the process label.

40 Process Statement Sensitivity List The process statement may include an optional sensitivity list.. A sensitivity list contains the signals that trigger the process. The process statement begins to execute if any of the signals sensitivity list contains an event. Once activated by a sensitivity list event,, the process statement executes statements in a sequential manner. Upon reaching the end of the process execution suspends until another event occurs from the sensitivity list.

41 Variables A variable,, unlike a SIGNAL, does not necessarily represent a wire in a circuit. Variables can be used in sequential areas only- - i.e. processes and subprograms. The scope of a variable is the process or the subprogram. A variable in a subprogram does not retain its value between calls. Variable assignment is immediate, not scheduled.

42 Modeling of Flip-Flops Library IEEE; use IEEE.Std_Logic_1164.all; entity FLOP is port (D, CLK : in std_logic; Q : out std_logic); end FLOP; architecture A of FLOP is begin process(clk) begin if CLK event and CLK= 1 ; Q <= D; end if; end process; end A; D Flip-flop controlled by a clock pulse edge. If an event occurs at the clock signal and this event has the value ONE, the value of the pin D will be transferred to the pin Q.

43 Lab 1 Design a digital system that can display a counter on a set of 7-segment LCD displays Switches control hex or decimal display

44 Lab1 1 millisecond pulse