CHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS

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Contents i SYLLABUS osmania university UNIT - I CHAPTER - 1 : BASIC VERILOG HDL Introduction to HDLs, Overview of Digital Design With Verilog HDL, Basic Concepts, Data Types, System Tasks and Compiler Directives, Gate Level Modeling, Hierarchical Structural Modeling, Dataflow Modeling, Continuous Assignments, Timing and Delays, Programming Language Interface. CHAPTER - 2 : DESIGN OF ARITHMETIC CIRCUITS Using Vectored Signals, Using a Generic Specification, Nets and Variables, Arithmetic Assignment Statements, Representation of Numbers in Verilog Code, Gate Level and Hierarchical Modeling of 4-bit Binary and BCD Adders and 8-bit Comparators. Verification : Functional Verification, Simulation Types, Design of Stimulus Block. UNIT - II CHAPTER - 3 : BEHAVIOURAL MODELING Switch Level Modeling and Examples, Behavioral Modeling, Structured Procedures, Procedural Assignments, Timing Controls and Conditional Statements, Multi-way, Branching, Loops, Sequential and Parallel Blocks, Generate Blocks, Tasks and Functions. CHAPTER - 4 : BEHAVIOURAL/D VIOURAL/DATA A FLOW MODELING OF BASIC MSI COMBINATIO TIOAL LOGIC MODULES ALUs, Encoders, Decoders, Multiplexers, Demultiplexers, Parity Generator/Checker Circuits, Bus Structure, Reaction Timer, Static Timing Analysis, Logic Synthesis and Register Transfer Level (RTL) Code.

ii Contents UNIT - III CHAPTER - 5 : BEHAVIOURAL/D VIOURAL/DATAFL AFLOW MODELING OF SEQUENTIAL LOGIC MODULES Latches, Flip Flops, Counters and Shift Registers. CHAPTER - 6 : SYNCHRONOUS SEQUENTIAL CIRCUITS Analysis and Synthesis of Synchronous Sequential Circuits, Mealy and Moore FSM Models for Completely and Incompletely Specified Circuits, State Minimization, Partitioning Minimization Procedure, Sequence Detector, One Hot Encoding, Synthesizable Verilog HDL Models fpr Sequence Detector Using Moore and Mealy Models, Design of a Modulo-8 Counter Using the Sequential Circuit Approach and its Verilog Implementation, FSM as an Arbiter Circuit. UNIT - IV CHAPTER - 7 : ALGORITHMIC STATE MACHINES (ASMS) ASM Chart, ASM Block, Simplifications and Timing Considerations With Design Example, ASMD Chart for Binary Multiplier and Verilog HDL Code, One Hot State Controller. Asynchronous Sequential Logic : Analysis Procedure Transition Table, Flow Table, Race Conditions, Hazards With Design Example of Vending Machine Controller. UNIT - V CHAPTER - 8 : MEMORY DEVICES Types of Memories, RAM BJT Cell and 6-T MOS RAM Cell, Organization of a RAM, Expanding Word Size and Capacity. Introduction to ASIC s : Full Custom, Standard Cell and Gate Array Based ASICs, SPLDs, PROM, PAL, GAL, PLA, FPGA and CPLD Simplified Architecture and Applications, ASIC/FPGA Design Flow, CAD Tools, Combinational Circuit Design With Programmalbe Logic Devices (PLDs).

Contents iii Digital System Design With Verilog HDL FOR b.e. (o.u) Iii year i semester (ELECTRONICS AND COMMUNICATION ENGINEERING) CONTENTS UNIT - I [CH. H. - 1] ] [BASIC VERILOG HDL]... 1-1 OVERVIEW OF DIGITAL AL DESIGN WITH VERILOG HDL... 1 Evolution of Computer-Aided Digital Design... 2 Emergence of HDLs... 3 Typical Design Flow (VLSI Design Flow)... 4 Importance of HDLs... 5 Popularity of Verilog HDL... 6 Trends in HDLs... 7 Major Capabilities of Verilog... 2 BASIC CONCEPTS OF VERILOG... 1 Laxical Conventions... 1 White Space... 2 Comments... 3 Operators... 4 Number Specification... 5 Strings... 6 Identifiers and Keywords... 7 Escaped Identifiers...

iv Contents 3 DATA A TYPES... 1 Value System... 2 Data Declaration... 3 Reg Declaration... 4 Net Declaration... 5 Syntax... 6 Port Types... 7 Delays on Nets... 8 Integer and Time... 9 Hierarchical Names... 10 Arrays... 11 Strings... 4 SYSTEM TASKS AND COMPILER DIRECTIVES... 1 System Tasks... 2 Compiler Directives... 5 GATE TE LEVEL MODELING... 1 Gate Types... 1 And/Or Gates... 2 BUF/NOT T Gates... 3 Array of Instances... 4 Examples... 2 Gate Delays... 1 Rise, Fall and Turnurn-off Delays... 2 Min/Typ/Max Values alues... 3 Delay Example... 6 DATAFL AFLOW MODELING... 6.1 Continuous Assignments...

Contents v 6.1 Implicit Continuous Assignment... 6.2 Implicit Net Declaration... 6.2 Delays... 6.1 Regular Assignment Delay... 6.2 Implicit Continuous Assignment Delay... 6.3 Net Declaration Delay... 7 HIERARCHICAL STRUCTURAL MODELING... 7.1 Design Methodologies... 7.1 4-Bit Ripple Carry Counter (Example For Design Hierarchy)... 7.2 Modules... 7.3 Components of a Simulation... 7.4 Example... 7.1 Design Block... 7.2 Stimulus Block... 8 TIMING AND DELAYS YS... 8.1 Delay Types... 8.1 Lumped Delay... 8.2 Distributed Delay... 8.3 Path ath Delay (Pin in to Pin in Delay)... 8.2 Classify Delay by Rise/Fall and Min/Max... 8.1 Rise and Fall Times... 8.2 Process Dependent Triads... 8.3 Complex Delays... 8.3 Verilog Specify Block... 8.1 Specparams... 8.2 Parallel Connection... 8.3 Fully Connected...

vi Contents 8.4 Conditional Path Delays... 8.5 Timing Checks... 8.1 Setup Time... 8.2 Hold Time... 8.3 Width... 8.4 Recovery... 8.4 Verilog Back Annotation... 9 PROGRAMMING LANGAUGE INTERFACE CE... 9.1 Uses of PLI... 9.2 Linking and Invocation of PLI Tasks... 9.1 Linking PLI Tasks... 9.2 Invoking PLI Tasks... 9.3 General Flow of PLI Task ask Addition and Invocation... 9.3 PLI Library Routines... 9.1 Access Routines... Short Questions and Answers... 1 - Expected University Questions with Solutions... 1 - UNIT - I [CH. - 2] ] [DESIGN OF ARITHMETIC CIRCUITS]... 1-1 USING VECTOREED SIGNALS... 2 USING A GENERIC SPECIFICATION... 3 NETS AND VARIABLES... 1 Nets... 2 Variables ariables... 4 ARITHMETIC ASSIGNMENT STATEMENTS TEMENTS... 5 REPRESENTATION TION OF NUMBERS IN VERILOG CODE... 6 GATE LEVEL MODELING OF 4-BIT BINARY ADDER... 6.1 Hierarchical Modeling of 4-bit Binary Adder...

Contents vii 7 GATE LEVEL MODELING OF BCD ADDER... 7.1 Hierarchical Modeling of BCD Adder... 8 GATE LEVEL MODELING OF 8-BIT COMPARA ARATORS... 8.1 Hierarchical Modeling of 8 Bit Comparator... 9 VERIFICATION... 9.1 Architectural Modeling... 9.2 Functional Verification Environment... 9.3 Simulation... Short Questions and Answers... 1 - Expected University Questions with Solutions... 1 - UNIT - II [CH. - 3] ] [BEHAVIOURAL MODELING]... 1-1 BEHAVIOURAL MODELING... 2 STRUCTURED PROCEDURES... 1 Initial Statement... 2 Always Statement... 3 In One Module... 3 PROCEDURAL ASSIGNMENTS... 1 Blocking Assignment... 2 Non-blocking Assignment... 4 TIMING CONTROLS... 1 Delay-Based Timing Control... 2 Event-Based Timing Control... 3 Level-Sensitive Timing Control... 5 CONDITIONAL STATEMENTS TEMENTS... 6 SEQUENTIAL AND PARALLEL BLOCKS OCKS... 6.1 Sequential Blocks... 6.2 Parallel Blocks...

viii Contents 7 GENERATE BLOCKS OCKS... 7.1 Generate Loop... 7.2 Generate Conditional... 7.3 Generate Case... 8 SWITCH LEVEL MODELING... 8.1 Switch-Modeling Elements... 8.1 MOS Switches... 8.2 CMOS Switches... 8.3 Bidirectional Switches... 8.4 Power and Ground... 8.5 Resistive Switches... 8.6 Delay Specification on Switches... 8.2 Examples... 8.1 CMOS NOR Gate... 8.2 2-to-1 Multiplexer... 8.3 Simple CMOS Latch... 9 TASKS... 9.1 Task Declaration and Invocation... 9.2 Task Examples... 9.3 Automatic (Re-Entrant) Tasks... 10 FUNCTIONS... 10.1 Function Declaration and Invocation... 10.2 Function Examples... 10.3 Automatic (Recursive) Functions... 10.4 Constant Functions... 10.5 Signed Functions... 10.6 Differences Between Tasks and Functions...

Contents ix 11 MULTIW TIWAY BRANCHING... 11 If Else If... 12 Case... 13 Comparison of Case and If-Else-If... 14 Casez and Casex... 12 LOOPS... Short Questions and Answers... 21 - Expected University Questions with Solutions... 1 - UNIT - II [CH. H. - 4] ] [BEHAVIOURAL/DATA FLOW MODELING OF BASIC MSI COMBINATIOAL LOGIC MODULES]... 1-1 ALUs... 2 MULTIPLEXERS... 1 2 to 1 Multiplexer... 2 4 to 1 Multiplexer... 3 8 to 1 Multiplexer... 4 Multiplexer Synthesis Using Shannon s s Expansion... 5 Expanding Multiplexers... 6 Applications of Multiplexers... 3 DEMULTIPLEXERS... 1 1 to 2 Demultiplexer... 2 1 to 4 Demultiplexer... 3 1 to 8 Demultiplexer... 4 Cascading of Demultiplexers... 5 Applications of Demultiplexers... 4 DECODERS... 1 2 Line to 4 Line Decoders... 2 3 Line to 8 Line Decoders...

x Contents 5 ENCODERS... 1 Binary Encoder... 1 4 to 2 Encoder... 2 8 to 3 Encoder (Octal to Binary Encoder)... 3 Decimal to BCD Encoder... 2 Priority Encoder... 1 Decimal to BCD Priority Encoder... 2 Octal to Binary Priority Encoder... 6 PARITY GENERATOR... 7 PARITY CHECKER... 8 BUS STRUCTURE... 8.1 Using a Shift Register for Control... 8.2 USING MULTIPLEXER TO O IMPLEMENT A BUS... 9 REACTION TIMER... 10 STATIC TIC TIMING ANALYSIS YSIS... 10.1 Pre-Layout Static Timing Analysis... 10.2 Post ost-l -Layout Static Timing Analysis... 10.3 Setup Time... 10.4 Hold Time... 11 LOGIC SYNTHESIS... 11 What is Logic Synthesis... 12 Impact of Logic Synthesis... 13 Verilog HDL Synthesis... 11 Verilog Constructs... 12 Verilog Operators... 13 Interpretation of a Few Verilog Constructs... 12 REGISTER TRANSFER LEVEL (RTL) CODE... Short Questions and Answers... 1 - Expected University Questions with Solutions... 1 -

Contents xi UNIT - III [CH. H. - 5] ] [BEHAVIOURAL/DATAFLOW MODELING OF SEQUENTIAL LOGIC MODULES]... 1-1 LATCHES - BASIC LATCH... 1 SR Latch... 1 NOR S-R Latch... 2 NAND S-R Latch... 3 NAND S-R Latch... 4 Clocked RS Flip-flop... 2 GATED SR LATCH CH... 3 GATED D LATCH... 4 FLIP FLOPS... 1 Triggering of Flip Flops... 1 Edge Triggering riggering... 2 Level Triggering... 2 SR Flip Flop... 1 Characteristic Table (or) Truth Table of SR Flip-flop -flop...... 3 JK Flip-flop... 1 Characteristic Table of JK Flip-flop... 2 Race Around Condition... 4 D Flip Flop... 1 Characteristic Table of D Flip-flop... 5 T Flip Flop... 1 Characteristic Table of T Flip Flop... 6 Applications of Flip-Flops... 5 SHIFT REGISTERS... 1 Frequency Division... 6 COUNTERS...

xii Contents 7 MASTER-SLAVE AND EDGE TRIGGERED FLIPFLOPS... 7.1 Master Slave SR Flip-Flop... 7.2 Master-Slave JK Flip-Flop... 7.3 Master-Slave D Flip-Flop... 7.4 Master Slave T Flip-Flop... 7.5 Edge Triggered SR Flip-Flop... 7.6 Edge Triggered JK Flip-Flop -Flop... 7.7 Edge Triggered D Flip-Flop -Flop... 7.8 Edge Triggered T Flip-Flop... Short Questions and Answers... 31 - Expected University Questions with Solutions... 1 - UNIT - III [CH. - 6] ] [I]... 1-6.1 ANALYSIS AND SYNTHESIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS... 6.1 Analysis of Sequential Circuits With ith Various Flip-Flops... 6.2 MELAY Y AND MOORE FSM MODELS FOR COMPLETELY Y AND INCOMPLETELY Y SPECIFIED CIRCUITS... 6.1 K-equivalence and K-distinguishable distinguishable... 6.2 Partition Techniques... 6.3 Machine Equivalence... 6.4 Simplification of Incompletely Specified Machines... 6.3 STATE TE MINIMIZATION... 6.1 Partitioning Minimization Procedure rocedure... 6.2 Incompletely Specified FSMs... 6.4 SEQUENCE DETECTOR...

Contents xiii 6.5 ONE HOT ENCODING... 6.6 SYNTHESIZABLE VERILOG HDL MODEL FPR SEQUENCE... DETECTOR USING MOORE MODEL... 6.7 SYNTHESIZABLE VERILOG HDL MODEL FOR SEQUENCE... DETECTOR USING MELAY MODEL... 6.8 DESIGN OF A MODULO-8 COUNTER USING THE SEQUENTIAL CIRCUIT APPROACH... 6.8.1 State Diagram and State Table for a Modulo-8 Counter... 6.8.2 State Assignment... 6.8.3 Example-A Different Counter... 6.9 FSM AS AN ARBITER CIRCUIT... Short Questions and Answers... 1 - Expected University Questions with Solutions... 1 - UNIT - IV [CH. - 7] ] [ALGORITHMIC [ STATE MACHINES (ASMS)]... 1-7.1 ALGORITHMIC STATE TE MACHINE (ASM) CHARTS TS... 7.1 ASM Block... 7.2 ASM Block Diagram of Mealy Circuit... 7.3 ASM Block Diagram of Moore Circuit... 7.4 Comparison between ASM Charts and State Diagrams... 7.5 Design Examples... 7.6 ASM Chart Implied Timing Information... 7.6.1 Data Path Circuit... 7.6.2 Control Circuit... 7.6.3 VHDL Code... 7.2 ASMD CHART FOR BINARY MULTIPLIER AND VERILOG HDL CODE...

xiv Contents 7.1 Datapath Circuit... 7.2 Control Circuit... 7.3 VHDL Code... 7.3 ONE HOT STATE TE CONTROLLER... 7.4 ASYNCHRONOUS SEQUENTIAL LOGIC... 7.5 ANALYSIS OF ASYNCHRONOUS SEQUENTIAL CIRCUIT... 7.1 Transition Table... 7.2 Flow Table able... 7.6 Race Conditions... 7.6.1 Types of Races aces... 7.6.1 Non-Critical Races... 7.6.2 Critical Races... 7.6.2 Cycles... 7.7 HAZARDS... 7.7.1 Hazards in a Combinational Circuits... 7.7.2 Hazards in a Sequential Circuits... 7.7.3 Types of Hazards... 7.7.1 Static Hazards... 7.7.2 Dynamic Hazards... 7.7.3 Essential Hazards... 7.7.4 Significance Hazards... 7.8 A COMPLETE DESIGN EXAMPLE... 7.8.1 The Vending Machine Controller... Short Questions and Answers... 1 - Expected University Questions with Solutions... 1 -

Contents xv UNIT - V [CH. H. - 8] ] [MEMORY DEVICES]....1-8.1 TYPES OF MEMORIES... 8.2 TYPES OF ROMS... 8.1 Masked ROMs... 8.2 Programmable Read Only Memory (PROM)... 8.3 Erasable Programmable Read Only Memory (EPROM)... 8.4 Electrically Erasable Programmable Read Only Memory (E 2 PROM)... 8.5 Advantages of ROM... 8.6 Disadvantages of ROM... 8.7 Applications of ROM... 8.3 RAM (RANDOM ACCESS MEMORY)... 8.1 Types of RAMs... 8.1 Static RAM... 8.1 Read Cycle... 8.2 Write Cycle... 8.2 Dynamic RAM... 8.1 Read Cycle... 8.2 Write Cycle... 8.2 Advantages of RAM... 8.3 Disadvantages of RAM... 8.4 6-Transistor SRAM... 8.4 EXPANDING WORD SIZE AND CAPACITY CITY... 8.5 ASIC S...

xvi Contents 8.6 SPLD S... 8.6.1 PROM... 8.7 PROGRAMMABLE LOGIC ARRAY (PLA)... 8.7.1 General Structure of PLA... 8.7.2 Gate Level Diagram of PLA... 8.7.3 Types of PLA... 8.7.1 Mask-programmable PLA... 8.7.2 Field-programmable PLA... 8.7.4 PLA Program Table... 8.7.5 Advantages of PLA... 8.7.6 Disadvantages of PLA... 8.7.7 Applications of PLA... 8.8 PROGRAMMABLE ARRAY Y LOGIC (PAL) AL)... 8.8.1 General Structure of PAL AL... 8.8.2 Gate Level Diagram of PAL AL... 8.8.3 Realization of Switching Functions Using PAL AL... 8.8.4 Advantages of PAL AL... 8.8.5 Disadvantages of PAL AL... 8.9 COMPARISON BETWEEN PROM, PLA AND PAL AL... 8.10 GENERIC ARRAY LOGIC (GAL)... 8.11 COMPLEX PROGRAMMABLE LOGIC DEVICES (CPLDS)...

Contents xvii 8.11 General Structure... 8.12 Basic Construction Using CPLDs... 8.13 Construction of Different Devices Using CPLDs... 8.14 Advantages of CPLDs... 8.15 Disadvantages of CPLDs... 8.12 FIELD PROGRAMMABLE GATE ARRAY (FPGAS)... 8.11 General Structure of FPGAs... 8.12 FPGA Placement Problem... 8.13 FPGA Routing Problem... 8.14 Versatile Place and Route... 8.15 Optimization by Simulated Annealing... 8.16 FPGA Routing With ith PathF athfinder... 8.17 Motivation... 8.18 Primary Modifications... 8.19 Advantages of FPGAs... 8.110 Disadvantages FPGAs... 8.111 Applications of FPGAs... 8.13 COMBINATIONAL CIRCUIT DESIGN WITH PROGRAMMABLE LOGIC DEVICES (PLDS)... 8.11 Advantages of PLDs... 8.12 Disadvantages of PLDs...

xviii Contents 8.14 CAD TOOLS... 8.11 VLSI Design using Computer-aided Design Tools... 8.11 Functional Specification and Verification erification... 8.12 Logical Design and Verification... 8.13 Circuit Design and Verification erification... 8.14 Physical Design and Verification... Short Questions and Answers... 1 - Expected University Questions with Solutions... 1 -

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