Programovatelné obvody a SoC. PI-PSC

Evropský sociální fond Praha & EU: Investujeme do vaší budoucnosti Programovatelné obvody a SoC. PI-PSC doc. Ing. Hana Kubátová, CSc. Katedra číslicového návrhu Fakulta informačních technologií ČVUT v Praze Hana Kubátová PI-PSC 2011 1

Testování systémů na čipu Přednáší a konzultuje: H.Kubátová Hana Kubátová PI-PSC 2011 2

Základní terminologie wiki SoC (system-on-a-chip) testing is the testing of system-ona-chip (SoC) devices. Testing then becomes an increasing challenge as these devices become more complex. An SoC design is typically built block by block; efficient testing is also best done block by block. Today, designers can install a specialized, pre-designed, configurable embedded system to test and debug each block. Using such an embedded system, a designer can specify the test speed, fault coverage, diagnostic options, and test length for testing any random logic block. Hana Kubátová PI-PSC 2011 3

Obsah SoC Test Problems/Requirements IEEE P1500 Standard http://grouper.ieee.org/groups/1500/ SoC Test Methodology Testable SoC Design Flow zdroje: Y. Zorian, ITC conf., Date conf., http://secs.ceas.uc.edu/~wjone/soc.pdf Samiha Mourad, Digital testing course, Santa Clara University, 2001 Hana Kubátová PI-PSC 2011 4

Problémy testování SoC Deeply embedded cores More, higher-performance core pins than SOC pins External ATE inefficiency Mixing technologies: logic, processor, memory, analog components Multiple hardware description levels for cores Different core providers and SOC test developers /test reuse Hierarchical core reuse IP protection Hana Kubátová PI-PSC 2011 5

SOC Test Requirements Deeply embedded cores Need Test Access Mechanism More, higher-performance core pins than SOC pins Need on-chip, at-speed testing External ATE inefficiency Need on-chip ATE Mixing technologies: logic, processor, memory, analog components Need various DFT/BIST/ techniques Hana Kubátová PI-PSC 2011 6

SOC Test Requirements ctd Multiple hardware description level for cores Need to insert DFT/BIST at various levels Different core providers and SOC test developers Need standard for test integration /test reuse Need plug-and-play test mechanism Hierarchical core reuse Need hierarchical test management IP protection Need core test standard/document Hana Kubátová PI-PSC 2011 7

Testování jader.. techniky Single scan Multiple scan Broadcast scan Enabled ATPG Scan insertion Reusable ATPG Access & isolation Test point insertion Shadow register Enabled BIST Scan, test points Embedded BIST Serial or parallel, local controller, TPG and SA Boundary scan (BS) Hana Kubátová PI-PSC 2011 8

Testy jedn. komponent DSP/CPU cores: BS supporting BIST, Scan, test point, shadow register. ASIC cores: BIST, Scan, shadow register, w/wo BS. Memory: Embedded BIST Analog: Test points, DSP, BIST, ad hoc Hana Kubátová PI-PSC 2011 9

SoC RAM Interface Block (RT Level ) Controller (algorithm) Micropro. (Layout) UDL FPGA DSP (Netlist) UDL RAM Hana Kubátová PI-PSC 2011 10

Hierarchie jader UDL SOC UDL Hana Kubátová PI-PSC 2011 11

Poměr typů jader Flexibil lity Soft Firm Hard Predictability, Performance, and complexity Hana Kubátová PI-PSC 2011 12

DFT - cyklus návrhu Behavioural Description Gate Behavioral DFT Synthesis Technology Mapping Libraries RTL Description Layout Logic DFT Synthesis Parameter Extraction Manufacturing Libraries Gate Description Product Test Pattern Generation Test Application low Fault Coverage? high Good Product Hana Kubátová PI-PSC 2011 13

Test access mechanismus, wrapery System IC System IC Isolation embedded core Embedded functional input functional output Ring (a) (b) scan chain scan chain scan chain core A l Test Rail Test Shell scan chain scan chain core B l Test Rail scan chain scan chain core C bypass Test Rail bypass (c) Test Rail Hana Kubátová PI-PSC 2011 14 bypass

Schema pro přímý přístup testu (direct access test scheme - DATS) TMODE TSEL TMODE TSEL cnt3 Test Control Logic Test Control Logic UI1 cnt1 cnt2 Input cnt3 User Output TI1 cnt3 = TMODE + TSEL cnt1 = TMODE cnt2 = TMODE + TSEL Block Output Hana Kubátová PI-PSC 2011 15

Přímý přístup testu TSEL EMBEDDED OUPUT TMODE USER IN TEST IN PRIMARY INPUT 10 S0 MUX O1 I1 INPUT USER LOGIC BLOCK BIDIRECTIONAL TEST PARTITION BOUNDARY BUFTE BUFTD EMBEDDED BIDIRECTIONAL EMBEDDED BIDIRECTIONAL CONTROL PRIMARY OUTPUT PRIMARY BIDIRECTIONAL Hana Kubátová PI-PSC 2011 16

BLOCK 1 SP8237 UIN1 TIN1 OUT1 DBUS TSEL DBUS0 OUTPUT PAD I/O PAD PIN 4 PIN 5 TMODE CNTL1 PIN 1 INPUT PAD BLOCK 2 USER PARTITION UIN2 TIN2 TMODE BLOCK OUT2 TSEL USER SIGNAL 12 MUX O1 L1 SEL OUTPUT PAD PIN 6 PIN 2 BLOCK 3 SP8259 UIN3 DBUS CNTL2 Příklad implementace INPUT PAD TIN3 TMODE OUT3 TSEL T S E L 3 T S E L 1 T S E L 2 PIN 3 TMODE INPUT PAD TEST CONTROL LOGIC 17

IC se 4 Test Access Ports C B S R NTC NTC NTC TAP 1 CBSR CBSR CBSR TAP'd X TAP 2 TAP'd Y TAP 3 TAP'd Z TAP 4 C B S R TDI TCK TMS TRST* TDO Hana Kubátová PI-PSC 2011 18

C B S R NTC NTC NTC CBSR TAP'd X CBSR CBSR TAP'd Y TAP'd Z C B S R TAP 1 TAP 2 TAP 3 SEL ENA SEL ENA SEL ENA TAP Linking Module TAP 4 SEL ENA TDI TCK TMS TRST* TDO 10/16/2011 Copyright(c)2001Samiha Mourad

Reusable TLM architecture C B S R NTC NTC NTC CBSR CBSR CBSR Multi TAP'd Multi TAP' d Multi TAP' d TAP 1 TLM TLM TLM SEL ENA SEL ENA SEL ENA SEL ENA C B S R TAP Linking Module TDI TCK TMS TRST* TDO 10/16/2011 Copyright(c)2001Samiha Mourad

Space Compaction U 1 2 3 4 Compact Sel B C U 1 2 3 4 (a) Space Compaction B Sel Reducing the external bandwidth Weighted Decoder (b) Weighted Decoder C Mode U MISR B C (c) BIST Application 10/16/2011 Copyright(c)2001Samiha Mourad

IEEE std 1500 - Standard for Embedded Test serial and parallel test access mechanisms (TAMs) rich set of instructions suitable for testing cores, SoC interconnect, and circuitry defines features that enable core isolation and protection reduces test cost through improved automation, promote good (DFT) technique, and improve test quality through improved 10/16/2011 Copyright(c)2001Samiha Mourad access

IEEE std 1500 test language (CTL) is the official mechanism for describing IEEE 1500 wrappers and test data associated with cores. CTL is defined in IEEE P1450.6 and was originally begun as part of the development of IEEE Std 1500. Hana Kubátová PI-PSC 2011 27

IEEE std 1500 Vychází z IEEE Std 1149.1.. wrapper architektura a access mechanismus navržený pro účely testování komponent na desce (IEEE Std 1500 podobná struktura pro testování jader SoC) Hana Kubátová PI-PSC 2011 28

IEEE std 1500 Approved 30 June 2005 American National Standards Institute Approved 20 March 2005 IEEE-SA Standards Board Sponsor Test Technology Technical Council of the IEEE Computer Society IEEE std 1500 Chair Yervant Zorian Hana Kubátová PI-PSC 2011 29

IEEE std 1500 cíle Standardize a Test Architecture which: Defines a core test interface between an embedded core and the system chip. Facilitate test reuse for embedded cores through core access and isolation mechanisms Provide testability for system chip interconnect and logic. Facilitates core test interoperability, with plug-andplay protocols, to improve the efficiency of test. Hana Kubátová PI-PSC 2011 30

IEEE std 1500 základní principy Embedded core test requires the following hardware components: A Wrapper (around the core) A Source/Sink for test patterns (on or off-chip) An on-chip Test Access Mechanism (TAM) to connect the Wrapper to the Source/Sink. Faciliate test reuse for "non-merged cores. Define the behavior of a standard Wrapper per core and its interface with a Test Access Mechanism (TAM). Hana Kubátová PI-PSC 2011 31

Závěry. SOC testing is a must Standard not defined yet Even standard is defined, many details need to be implemented Component testing needs to consider test reuse Automation of wrapper generation & system chip interface must be done Tools for linking design flow Test access mechanism is to be user-defined, hence test engineer will not lost job Mixed-mode testing in SOC is urgent Hana Kubátová PI-PSC 2011 32