DATASHEET ALLEGRO PCB SI 630 VIRTUAL PROTOTYPING ENVIRONMENT FOR DESIGNS WITH MULTI-GIGAHERTZ SIGNALS Cadence Allegro PCB SI 630 a key PCB Signal Integrity tool within the Allegro system interconnect design platform provides a virtual prototyping environment for designs with signals operating in the Multi-GigaHertz (MGH) frequency range. It is a completely integrated MGH signal design and analysis solution built on top of the proven and familiar Allegro PCB SI environment (formerly Cadence SPECCTRAQuest). Allegro PCB SI 630 introduces leading-edge technology to shorten design cycle time and eliminate the need to do multiple lab qualifications with full functional physical prototypes. Package design-in kit Interconnect models I/O buffer IP IC package and SiP design I/O buffer design Implement Design Eplore Verify Virtual system interconnect model Specify The Allegro system interconnect design platform PCB design Build Correlate IC design Silicon design-in kit On-target, on-time system interconnect THE ALLEGRO SYSTEM INTERCONNECT DESIGN PLATFORM The Cadence Allegro system interconnect design platform enables collaborative design of high-performance interconnect across IC, package, and PCB domains. The platform s unique co-design methodology optimizes system interconnect between I/O buffers and across ICs, packages, and PCBs to eliminate hardware re-spins, decrease costs, and reduce design cycles. The Allegro constraint-driven flow offers advanced capabilities for design capture, signal integrity, and physical implementation. With silicon design-in kits, IC companies shorten new device adoption time and systems companies accelerate PCB design cycles for rapid time to profit. Supported by the Cadence Encounter and Virtuoso platforms, the Allegro co-design methodology ensures effective design chain collaboration.
ALLEGRO PCB SI 630 The need to provide ultra high bandwidth for data transfer coupled with pressures to get products to market faster has added many challenges for system designers. While technological advances such as differential signals with embedded clocks (serial links), drivers with pre-emphasis, and receivers with equalization allow engineers to architect systems that have higher performance and throughput, the tools to design such systems have not kept pace. This situation has forced engineers to use disparate standalone tools to design systems with high-speed signals, particularly those that operate in MGH range. For differential signals used in serial link designs, system designers must ensure that timing and voltage margins are met (also known as achieving acceptable eye opening ). Traditional circuit simulators are limited to about 1024 bits of custom stimulus pattern length. This means that the effect of Inter Symbol Interference (ISI) is not adequately modeled by traditional simulation solutions. To accurately predict the eye opening, you need tools that can simulate stimulus patterns of over 1 million bits. Signals operating in MGH range require a new generation of design tools to manage challenges introduced in the design process. You need a set of tools that model each element of the signal s path quickly and accurately. At high frequencies, the losses on a signal mount as the signal travels through different discontinuities such as vias, connectors and different layers in one or more printed circuit boards. At GigaHertz frequencies, the loss in a transmission line can approimately be 0.25+ db/inch, creating challenges for longer interconnects on PCB systems. Bandwidth/Pin (MB/s/pins) 100 80 60 40 20 0 PCI 1.58 PCI-X 7.09 AGP4X 9.85 Ensuring that losses in critical signals are acceptable is an important step in the design of MGH signals. To accomplish this, you need a way to do loss budget trade-offs using S-Parameters quickly and iteratively. You also need a way to change the MGH signals topology and within seconds be able to view the epected loss through the system interconnect. Engineers need a way to perform loss budget trade-offs using S-Parameters, while achieving faster simulation of comple devices. MGH design further requires technology for simulating tens of thousands of bits quickly, and determining optimal configuration ( tap settings ) of comple drivers/ receivers. Engineers need a system that addresses their major design challenges in an integrated environment that is simple to use, and has productivity capabilities built in. Allegro PCB SI 630 offers engineers an easy-to-use and highly integrated virtual prototyping environment to meet today s MGH design challenges. HL1 11.57 100X Price/Performance BENEFITS HL2 26.60 PCI Epress 100 Serial data increases the throughput per pin, reducing the real estate required on printed circuit boards Complete integrated S-Parameter support Perform multiple loss budget trade-offs using S-Parameter quickly and easily Simulate S-Parameter in time domain Simulate 10,000 bits in seconds, millions of bits in hours with unprecedented simulation capacity and performance Model comple drivers with preemphasis and receivers with equalization using proven macro modeling capability to perform accurate simulations 20 to 400X faster than transistor level simulations Perform accurate simulation of highspeed signals using a SPICE-based engine Proven Allegro PCB SI technology and PCB analysis environment 2
KEY FEATURES Complete, fully integrated S-Parameter support allows you to: Generate S-Parameters from PCB signal topologies ( Stack-up to S ) Plot S-Parameters for any number of elements in the topology in SigWave quickly and easily Concatenate multiple S-Parameters into one Incorporate S-Parameters for an object into the topology, then generate S-Parameter for the entire topology Change topology or stack-up and do quick iterative loss budget trade-offs Correlate S-Parameters for different sources (e.g., generated vs. measured) Simulate S-Parameters in time domain Any portion of the passive interconnect can be plotted as S-Parameter in SigWave topology eplorer Unprecedented capabilities for high-capacity and high-performance simulation allow you to: Simulate tens of thousands of bits in seconds (or millions in an hour) using high-capacity simulation Optimize MGH I/O buffer configurations tap settings through channel analysis Fleible S-Parameter support allows you to: Incorporate measurement-based S-Parameter models in native Touchstone format Incorporate measured or imported S-Parameters with other interconnect topologies Proven Macro Modeling capabilities allow you to: Model and simulate MGH drivers and receivers faster and more accurately Achieve simulation performance improvement of 20 to 400X over transistor-level simulation Create new comple models quickly using available templates Eye shrinks with number of bits in stimulus pattern. Good eye diagram is important for accurate jitter, insertion loss, and BER prediction 3
Via model generator allows you to: Create accurate via models quickly (wide band, narrow band, S-Parameter) to simulate via stub effects at MGH frequencies for single vias, differential vias, and vias coupled with Ground/ Power vias Specify start frequency, end frequency, and number of frequency points Reuse eisting board layout for stackup/padstack information or point to a technology file with that information T De-emphasis Multi-tap High-pass filter DSP techniques R Supported I/O buffer model formats include: Cadence Allegro PCB SI Device Modeling Language (DML) Synopsys HSPICE transistor-level models (requires HSPICE simulator and license, which is NOT included with Allegro PCB SI 630) Cadence Spectre transistor-level models (available on Sun Solaris, HP UX, and Linu RHEL 3.0 platforms only). This utilizes an integrated and limited capability version of the Spectre simulator, which is included with Allegro PCB SI 630. IBIS 4.0 Mentor/Quad XTK Users need proven advanced macro modeling capabilities for devices with pre-emphasis or receiver equalization without sacrificing simulation performance. Complete library management through Model Integrity allows you to: Read and write touchstone format S-Parameters Check passivity of S-Parameters Plot S-Parameters with simply a click of a button Convert comple numbers with simply a click of a button Create and edit IBIS or Cadence DML models in an easy to use Model Integrity environment Convert HSPICE models to IBIS easily Via model generator allows users to model stub effects at MGH frequencies during pre-route eploration and analysis phase of the design process 4
Proven Allegro PCB SI technology using SPICE-based simulation engine provides: Integrated solution space eploration through SigXplorer topology editor and simulation cockpit Model frequency-dependent losses and skin effect accurately for MGH signals with integrated field solver Constraint-driven PCB design flow (with the same Allegro Constraint Manager used throughout the Allegro PCB design solution) Quick trial implementation using tightly integrated Allegro PCB Router 610 (formerly known as SPECCTRA Epert Autorouter) Integration and interfaces Reads and writes Allegro PCB database (.brd files) Provides interface to Mentor BoardStation layout database ALLEGRO PCB SI 630 COMPONENTS Allegro PCB SI 630 includes the following modules: SIGXPLORER TOPOLOGY EXPLORATION ENVIRONMENT You can use SigXplorer for pre-route topology design and analysis even before a schematic is created. This type of analysis is common at the earliest stages of the design cycle, when designers assess the impact of using a new device technology or increasing bus transfer rate. You can use SigXplorer to build and validate detailed electrical topology models and prove the viability of a new technology before the detailed design process begins. Key features of SigXplorer include A graphical environment for eploring, analyzing, and defining interconnect strategies that provides an electrical view of the physical interconnect Advanced capabilities for generating S-Parameters for loss budget trade-offs from interconnect topologies in SigXplorer (Plotting of S-Parameter is done through SigWave) Model Integrity provides complete support for S-Parameters from passivity checks to right mouse click plotting to conversions of comple numbers in an easy-to-use environment A via model generator for MGH signals Solution space eploration that allows you to develop an optimum set of constraints to ensure reliable performance under a wide range of operating conditions. SigXplorer provides a graphical environment to perform what if analysis and determines the effects of different routing strategies, component values, and design tolerances. Swept-parameter analysis is used to model the behavior of the circuit under a variety of conditions, and is used to develop optimum design constraints for the final design. For eample, you can sweep design parameters such as differential impedance and delay/length. Once design parameters are chosen, you can then eplore physical implementation parameters such as trace width, gap, and maimum uncoupled length for differential signals. This capability allows users to trade-off electrical performance with reliability as well as the cost of manufacturing the final PCB system. The results of the swept-parameter analysis are displayed in a spreadsheet format within the SigXplorer window. You can select any of the different simulation cases and view the associated simulation waveforms. The spreadsheet data can be sorted within the SigXplorer interface, or eported in a standard tab-delimited format for use with other spreadsheet and data post-processing programs. Built-in timing measurements and a graphical user interface allow you to develop custom measurements associated with the topology that you are simulating or eploring. These custom timing measurements give you the capability to use basic arithmetic functions such as addition, subtraction, multiplication, and division. These custom measurements can be developed during pre-layout eploration and embedded within the ECSet for use during the post-layout verification stage. Capacity to capture design constraints as an electrical constraint set (ECSet) that will be saved in the PCB database and used to drive the physical design process. ECSets can be thought of as a constraint template that is applied to a group of nets. ECSets can also include routing strategy for a signal or a group of signals. Once assigned to a group of nets within a layout design, the ECSet stays with the design and continues to guide interactive and automatic routing. 5
LEADING-EDGE HIGH CAPACITY, HIGH PERFORMANCE SIMULATION The Channel Analysis plug-in module within Allegro PCB SI 630 addresses users need for high capacity simulation to ensure timing and voltage margins are met for MGH signals. The Channel Analysis module allows users to simulate up to 10 million bits fast. It takes seconds to simulate 10,000 bits, an hour to simulate a million bits on a typical PC/Windows platform. In addition, the Channel Analysis module allows users to develop meaningful configurations ( tap settings ) for a comple driver or receiver quickly. Users get a recommendation for a specific topology in seconds saving weeks of simulation time to determine the optimal settings. PROVEN SPICE-BASED SIMULATION SUBSYSTEM Allegro PCB SI simulation environment for signal integrity, crosstalk, and EMI analysis includes the Tlsim simulation engine, the SigWave waveform display, the DML modeling language, translators from other modeling formats, and a library model editing/management subsystem. The Tlsim engine is a SPICE-based simulator that combines the advantages of traditional SPICE-based structural modeling with the speed of behavioral analysis. Tlsim includes an IBIS-style behavioral driver element that models I/O behavior based on the V-I and V-T data provided by behavioral modeling techniques. Tlsim in PCB SI 630 also includes the capability to simulate S-Parameters in time domain. By combining both structural and behavioral modeling techniques, Tlsim enables you to accurately and efficiently model comple device behavior. Tlsim also includes a lossy, coupled, frequency-dependent transmission line model that accurately predicts the distributed behavior of PCB traces into the GHz range. An integrated electrical field solver is used to determine the electrical characteristics of routed etch. The SigWave waveform display can present simulation results in multiple formats, including S-Parameters. The oscilloscope mode allows you to turn the display of individual waveforms on and off, provides markers for use in making on-screen measurements, and lets you add notes to the display. The logic-analyzer mode presents waveforms alongside each other, so that logic behavior and bus transactions are easier to observe. The spectrum analyzer mode displays signal behavior in the frequency domain using one of several different FFT techniques. The eye-diagram mode is useful for viewing patterns in long simulation sequences and enables you to interactively define the signal period and starting offset. SigWave allows you to import waveform data directly from various standard test equipment formats as well as from the output formats of popular SI analysis tools. ALLEGRO CONSTRAINT MANAGER Allegro Constraint Manager allows users to capture, manage, and validate various rules in a hierarchical fashion. It provides a real-time display of highspeed rules and their status based on the current state of design. Constraint Manager enables you to group all of the high-speed constraints for a collection of signals, and to form an electrical constraint set (ECset) that is then associated with those nets to manage their actual implementation. ECSets can be used to drive PCB layout design process, shortening the design cycle time. Constraint Manager is completely integrated with the Allegro PCB Editor design-rules checking system. As a result, you can check the different high-speed rules in real time as the design process proceeds, viewing results presented as part of the Constraint Manager spreadsheets. Any design parameters that do not meet their associated constraint values are also highlighted. Constraint Manager integrates the results of SI analysis, allowing designers to manage simulation-based electrical constraints. ALLEGRO MODEL INTEGRITY Allegro PCB SI accepts device models from a variety of different high-speed digital modeling formats. Support for the IBIS 4.0 modeling standard allows Allegro PCB SI to use models created by most semiconductor manufacturers. You can also translate models from the Mentor/Quad XTK simulator format, or create Allegro PCB SI models from SPICE device models. In addition, Allegro PCB SI provides users with a net generation modeling language for more comple devices the Cadence Device Modeling Language (DML). The model integrity module within Allegro PCB SI allows you to create, manipulate, and validate models quickly in an easy-to use editing environment. Model integrity provides a model browser and synta checker for models written in IBIS as well as for advanced models written in Cadence DML. The marker navigation functionality provides an easy way to fi synta errors. You can verify models using SigXplorer with simple test circuits. Model integrity also provides an HSPICE-to-IBIS module to assist users in creating IBIS models from HSPICE models. With the output of the HSPICE simulation run, IBIS, and buffer options file, users can quickly create IBIS models. Model integrity identifies V-I and V-T tables for typical, maimum, and minimum corner cases from the HSPICE run file. Since the number of points in an HSPICE simulation run could be far greater than the maimum number of points allowed in IBIS, the model integrity HSPICE-to-IBIS module applies an intelligent and proven best-curvefitting algorithm to provide an accurate IBIS model. A leading semiconductor company has used the algorithms contained in the HSPICE-to- IBIS model for many years. 6
FLOORPLANNER/EDITOR AND PCB ROUTER The Allegro PCB SI floorplanner provides a graphical view of the PCB database allowing you to view, simulate, and edit the PCB design. Designers can quickly and easily evaluate the effects of different placement strategies on design behavior. You can perform test routing using proposed electrical constraints to ensure high-speed design rules are achievable before passing them on to the PCB layout designer. The Constraint Manager allows you to view different electrical rules in the database, and it updates a net s adherence to the rules in real time as components are moved and nets are routed. By showing the electrical design rules associated with each component, a Constraint Manager timing spreadsheet helps you to optimize multiple tradeoffs associated with the placement of each component. This timing spreadsheet integrates SI analysis with component timing information, providing bus-level timing analysis directly from the PCB database. It combines component-level timing information (device output delay, setup/hold requirements) with the results of SI analysis (min/ma flight time) and system-level information (clock period and clock jitter/skew budgets) to provide system level, post layout timing analysis directly from the Allegro PCB database. EMCONTROL By applying a combination of standard rules and user-defined rules, EMControl can eliminate weeks of manual checking and improve product quality and reliability. Standard rule set EMControl provides comprehensive, knowledge based design-rules checking for common EMI-related placement and routing issues. EMControl rule checking replaces traditional errorprone manual inspection with automated analysis of the layout based on a set of best known design practices. EMControl flags potential problem areas, automatically zooming and panning the display of the PCB to highlight the area in question and then identifies the issue to the designer and recommends a solution. User-defined rules EMControl allows you to create new custom rules that fit well within your company s design guidelines. These rules allow for customization and more importantly, capture the high-speed design eperience as customized rules, which in turn can be reused on all future designs. The EMControl design rule checker also furnishes differential-mode EMI analysis in the Allegro PCB SI design environment. EMControl predicts farfield differential-mode radiated emissions in both SigXplorer and the Allegro PCB SI floorplanner. Simulation of differential emissions helps designers identify which nets are likely to cause EMI problems. It also allows you to eplore design strategies required to keep radiation within acceptable levels. Near-field EMI analysis, available within the Allegro PCB SI floorplanner, can predict radiated energy immediately above the board surface. By analyzing near-field EMI patterns, you can identify which portions of a routed trace are producing the most radiated energy and adapt the design accordingly. OPERATING SYSTEM SUPPORT Red Hat Linu 7.3, 8.0, RHEL 3.0 Windows 2000 with Service Pack 4, XP Professional Sun Solaris 8, 9 HP-UX 11.0, 11.11i IBM AIX 5.1 CADENCE SERVICES AND SUPPORT Cadence application engineers can answer your technical questions by telephone, email, or Internet they can also provide technical assistance and custom training Cadence certified instructors teach over 70 courses and bring their realworld eperience into the classroom Over 25 Internet Learning Series (ils) online courses allow you the fleibility of training at your own computer via the Internet SourceLink online customer support gives you answers to your technical questions 24 hours a day, 7 days a week including the latest in quarterly software rollups, product change release information, technical documentation, solutions, software updates, and more 7
ALLEGRO PCB SI FEATURES Major feature summary for SI, Allegro Design Entry HDL SI 610, Allegro PCB SI 630, and Allegro PCB PI option 610 Allegro PCB Allegro Design Entry Allegro PCB Allegro PCB PI SI 610 HDL SI 610 SI 630 option 610 Allegro Design Entry HDL 610 Assign models in schematics Create Xnets in schematics Apply constraints and topologies to schematic for single-ended and differential nets Single-line topology editor (graphical canvas) Simulation setup advisor Model integrity: model development environment Model integrity: synta checking for IBIS 3.2 and DML Model integrity: HSPICE-to-IBIS conversion IBIS 4.0 models support Quad models translator Spectre transistor-level models Macro-models support (DML) Simulation control: single-line simulation Waveform Viewer Detailed simulation reports (such as flight time, overshoot, noise margin) Coupled (3 net) simulation Coupled (>3nets) simulation Single net pre-layout etraction from Allegro Design Entry HDL Allegro Physical Viewer Plus Differential pair eploration and simulation Differential pair pre- and postlayout etraction from Allegro PCB Editor Differential pair pre-layout etraction from Allegro Design Entry HDL Differential signal constraint capture Coupled line simulations Crosstalk simulation Sweep simulations Current probes Multiterminal black boes in topologies Constraint development and capture of topologies Custom measurement Custom stimulus Batch simulation EMControl: rules development EMControl: rules checking EMI differential simulation Allegro Constraint Manager Color-coded real-time feedback on violations Apply constraints and topologies to board for single-ended and differential nets Floorplanner Constraint-driven floorplanning and routing Allegro PCB Router 610 HSPICE simulator interface S-Parameter generation from stackup S-Parameter plotting in SigWave Time domain simulation of S-Parameters Library management of S-Parameters in model integrity Coupled via model generator for pre-layout eplorations High capacity simulation using Channel Analysis overlay Optimum pre-emphasis bit configurations ( tap settings ) Power integrity: design and analysis environment Power integrity: decoupling capacitor database Setup Wizard Power integrity: impedance requirements calculator Power integrity: decoupling capacitor selection and placement environment Power integrity: VRM Editor Power integrity: decoupling capacitor library editor Power integrity: cross-probing between waveform Allegro PCB SI floorplanner Power integrity: frequency domain analysis FOR MORE INFORMATION Contact Cadence sales at 1.800.746.6223 or visit www.cadence.com for additional information. To locate a Cadence sales office or value-added reseller (VAR) in your area, visit www.cadence.com/contact_us. 2005 Cadence Design Systems, Inc. All rights reserved. Cadence and the Cadence logo are registered trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders. 5585D 06/05